LocalApic = 0,
IOApic = 1,
IRQSourceOverride = 2,
- NMI = 3,
+ NMIType = 3,
LocalApicNMI = 4,
LApicAddressOverride = 5,
IOSApic = 6,
#include <console/console.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
extern const unsigned char AmlCode[];
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
extern const unsigned char AmlCode_ssdt5[];
#endif
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
extern const unsigned char AmlCode_ssdt5[];
#endif
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
extern const unsigned char AmlCode[];
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdk8_sysconf.h>
#include "northbridge/amd/amdk8/amdk8_acpi.h"
-
#include "mb_sysconf.h"
#define DUMP_ACPI_TABLES 0
extern const unsigned char AmlCode_ssdt4[];
#endif
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
smp_write_bus(mc, m->bus_isa, "ISA ");
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, m->apicid_8111, 0x11, 0xfec00000); //8111
+ smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
{
device_t dev;
struct resource *res;
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
extern const unsigned char AmlCode_ssdt5[];
#endif
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
smp_write_bus(mc, m->bus_isa, "ISA ");
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, m->apicid_8111, 0x11, 0xfec00000); //8111
+ smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
{
device_t dev;
struct resource *res;
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
extern const unsigned char AmlCode_ssdt5[];
#endif
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
smp_write_bus(mc, bus_isa, "ISA ");
/* IOAPIC handling */
- smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000);
+ smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
extern const unsigned char AmlCode_ssdt5[];
#endif
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
#include <string.h>
#include <arch/acpi.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/device.h>
#include <device/pci_ids.h>
#include "southbridge/via/vt8237r/vt8237r.h"
/* Write SB IOAPIC. */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- VT8237R_APIC_ID, VT8237R_APIC_BASE, 0);
+ VT8237R_APIC_ID, IO_APIC_ADDR, 0);
/* Write NB IOAPIC. */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
#include <string.h>
#include <stdint.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include "southbridge/via/vt8237r/vt8237r.h"
#include "southbridge/via/k8t890/k8t890.h"
smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VT8237R_APIC_BASE);
+ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);
smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE);
mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
#include <string.h>
#include <arch/acpi.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/device.h>
#include <device/pci_ids.h>
#include "southbridge/via/vt8237r/vt8237r.h"
/* Write SB IOAPIC. */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- VT8237R_APIC_ID, VT8237R_APIC_BASE, 0);
+ VT8237R_APIC_ID, IO_APIC_ADDR, 0);
/* Write NB IOAPIC. */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdfam10_sysconf.h>
-
#include "mb_sysconf.h"
#define DUMP_ACPI_TABLES 0
extern const unsigned char AmlCode_ssdt5[];
#endif
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
smp_write_bus(mc, 2, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
+ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
smp_write_bus(mc, 1, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
+ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
/* IOAPIC handling */
- smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
+ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
{
struct resource *res;
device_t dev;
#include <console/console.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
/* Reserve space for the IOAPIC. This should be in the Southbridge,
* but I couldn't tell which device to put it in. */
res = new_resource(dev, 2);
- res->base = 0xfec00000UL;
+ res->base = IO_APIC_ADDR;
res->size = 0x100000UL;
res->limit = 0xffffffffUL;
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
#include <string.h>
#include <console/console.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <arch/acpigen.h>
#include <arch/smp/mpspec.h>
#include <device/device.h>
return header->length;
}
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_madt(unsigned long current)
{
/* Local APICs */
* MA 02110-1301 USA
*/
-
#include <device/device.h>
#include <device/pci.h>
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
smp_write_bus(mc, isa_bus, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
+ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
extern const unsigned char AmlCode_ssdt5[];
#endif
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdfam10_sysconf.h>
-
#define DUMP_ACPI_TABLES 0
#if DUMP_ACPI_TABLES == 1
extern const unsigned char AmlCode_ssdt5[];
#endif
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, apicid_8111, 0x20, 0xfec00000);
+ smp_write_ioapic(mc, apicid_8111, 0x20, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
#include <string.h>
#include <console/console.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <arch/acpigen.h>
#include <arch/smp/mpspec.h>
#include <device/device.h>
acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
}
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_madt(unsigned long current)
{
/* Local APICs */
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
#include <device/device.h>
#include <device/pci.h>
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
/* I/O APICs: APIC ID Version State Address */
ioapic_id = 2;
- smp_write_ioapic(mc, ioapic_id, 0x20, 0xfec00000);
+ smp_write_ioapic(mc, ioapic_id, 0x20, IO_APIC_ADDR);
/* Legacy Interrupts */
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
smp_write_bus(mc, bus_isa, "ISA ");
/* Legacy IOAPIC #2 */
- smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
+ smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
smp_write_bus(mc, bus_isa, "ISA ");
/* Legacy IOAPIC #2 */
- smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
+ smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
extern const unsigned char AmlCode_ssdt5[];
#endif
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
+#include <arch/ioapic.h>
#include "dmi.h"
#define OLD_ACPI 0
acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
}
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_madt(unsigned long current)
{
/* Local APICs */
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
#include <device/device.h>
#include <device/pci.h>
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
smp_write_bus(mc, isa_bus, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
+ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
/* Legacy Interrupts */
#include <string.h>
#include <console/console.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#define IO_APIC0 2
#define IO_APIC1 3
-#define IO_APIC0_ADDR 0xfec00000UL
-#define IO_APIC1_ADDR 0xfec10000UL
unsigned long acpi_fill_madt(unsigned long current)
{
current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 2, 1);
/* IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, IO_APIC0, IO_APIC0_ADDR, irq_start);
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, IO_APIC0, IO_APIC_ADDR, irq_start);
irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, IO_APIC1, IO_APIC1_ADDR, irq_start);
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, IO_APIC1, IO_APIC_ADDR + 0x10000, irq_start);
irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
#include <console/console.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <string.h>
smp_write_bus(mc, bus_isa, "ISA ");
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
+ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
/*
{
device_t dev;
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
/* IOAPIC handling */
- smp_write_ioapic(mc, 8, 0x20, 0xfec00000);
+ smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR);
{
struct resource *res;
device_t dev;
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
smp_write_bus(mc, bus_isa, "ISA ");
/* IOAPIC handling */
- smp_write_ioapic(mc, 0x01, 0x20, 0xfec00000);
+ smp_write_ioapic(mc, 0x01, 0x20, IO_APIC_ADDR);
mptable_add_isa_interrupts(mc, bus_isa, 0x1, 0);
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
smp_write_bus(mc, bus_isa, "ISA ");
/* IOAPIC handling */
- smp_write_ioapic(mc, 0x8, 0x20, 0xfec00000);
+ smp_write_ioapic(mc, 0x8, 0x20, IO_APIC_ADDR);
mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <assert.h>
// Southbridge IOAPIC
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH3, 0xfec00000, irq_start);
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH3, IO_APIC_ADDR, irq_start);
irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
// P64H2#2 Bus A IOAPIC
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
// TODO: Gack. This is REALLY ugly.
// Southbridge IOAPIC
- smp_write_ioapic(mc, IOAPIC_ICH3, 0x20, 0xfec00000); // APIC ID, Version, Address
+ smp_write_ioapic(mc, IOAPIC_ICH3, 0x20, IO_APIC_ADDR); // APIC ID, Version, Address
// P64H2#2 Bus A IOAPIC
dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdk8_sysconf.h>
#include "northbridge/amd/amdk8/amdk8_acpi.h"
-
#include "mb_sysconf.h"
#define DUMP_ACPI_TABLES 0
extern const unsigned char AmlCode_ssdt5[];
#endif
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
smp_write_bus(mc, m->bus_isa, "ISA ");
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, m->apicid_8111, 0x11, 0xfec00000); //8111
+ smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
{
device_t dev;
struct resource *res;
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
smp_write_bus(mc, bus_isa, "ISA ");
/* IOAPIC handling */
- smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
+ smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
smp_write_bus(mc, bus_isa, "ISA ");
/* IOAPIC handling */
- smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
+ smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
extern const unsigned char AmlCode_ssdt5[];
#endif
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
#include <string.h>
#include <console/console.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <arch/acpigen.h>
#include <arch/smp/mpspec.h>
#include <device/device.h>
acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
}
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_madt(unsigned long current)
{
/* Local APICs */
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
#include <device/device.h>
#include <device/pci.h>
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
/* I/O APICs: APIC ID Version State Address */
ioapic_id = 2;
- smp_write_ioapic(mc, ioapic_id, 0x20, 0xfec00000);
+ smp_write_ioapic(mc, ioapic_id, 0x20, IO_APIC_ADDR);
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
extern const unsigned char AmlCode[];
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
/* IOAPIC handling */
- smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
+ smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
#include <string.h>
#include <console/console.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <arch/smp/mpspec.h>
acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
}
-
-
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_madt(unsigned long current)
{
/* Local APICs */
* MA 02110-1301 USA
*/
-
#include <device/device.h>
#include <device/pci.h>
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
smp_write_bus(mc, isa_bus, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
+ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
/* IOAPIC handling */
- smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
- smp_write_ioapic(mc, 3, 0x20, 0xfec10000);
+ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000);
mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
/* IOAPIC handling */
- smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
- smp_write_ioapic(mc, 3, 0x20, 0xfec10000);
+ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000);
{
struct resource *res;
device_t dev;
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
/* IOAPIC handling */
- smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
- smp_write_ioapic(mc, 3, 0x20, 0xfec10000);
+ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000);
{
struct resource *res;
device_t dev;
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
/* IOAPIC handling */
- smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
+ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
{
struct resource *res;
device_t dev;
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
/* IOAPIC handling */
- smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
+ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
{
struct resource *res;
device_t dev;
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
extern const unsigned char AmlCode[];
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
extern const unsigned char AmlCode[];
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &isa_bus);
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, 8, 0x20, 0xfec00000);
+ smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
#endif
apicid_8111 = apicid_base+0;
- smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000);
+ smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
#endif
apicid_8111 = apicid_base+0;
- smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000);
+ smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
apicid_8111 = apicid_base+0;
apicid_8131_1 = apicid_base+1;
apicid_8131_2 = apicid_base+2;
- smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000);
+ smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
{
device_t dev;
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000);
+ smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <string.h>
apicid_8131_1 = apicid_base+1;
apicid_8131_2 = apicid_base+2;
- smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000);
+ smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
smp_write_bus(mc, bus_isa, "ISA ");
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); //8111
+ smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); //8111
{
device_t dev;
struct resource *res;
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
apicid_8131_1 = apicid_base+1;
apicid_8131_2 = apicid_base+2;
- smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000);
+ smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
apicid_8111 = apicid_base+0;
apicid_8131_1 = apicid_base+1;
apicid_8131_2 = apicid_base+2;
- smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000);
+ smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
/* Write SB IOAPIC. */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- VT8237R_APIC_ID, VT8237R_APIC_BASE, gsi_base);
+ VT8237R_APIC_ID, IO_APIC_ADDR, gsi_base);
/* IRQ0 -> APIC IRQ2. */
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
#include <device/pci.h>
#include <device/pci_ids.h>
#include <boot/tables.h>
+#include <arch/ioapic.h>
#include <southbridge/via/vt8237r/vt8237r.h>
#include "chip.h"
{
#if CONFIG_IOAPIC == 1
lb_add_memory_range(mem, LB_MEM_RESERVED,
- VT8237R_APIC_BASE, 0x1000);
+ IO_APIC_ADDR, 0x1000);
lb_add_memory_range(mem, LB_MEM_RESERVED,
0xFEE00000ULL, 0x1000);
lb_add_memory_range(mem, LB_MEM_RESERVED,
/* as modified by RGM for coreboot */
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
mptable_write_buses(mc, NULL, &isa_bus);
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
+ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
#include <console/console.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VT8237R_APIC_BASE);
+ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);
/* Now, assemble the table. */
mptable_add_isa_interrupts(mc, isa_bus, VT8237R_APIC_ID, 0);
#include <string.h>
#include <console/console.h>
#include <arch/acpi.h>
+#include <arch/ioapic.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
}
-
-
-#define IO_APIC_ADDR 0xfec00000UL
-
unsigned long acpi_fill_madt(unsigned long current)
{
/* Local Apic */
#include <device/device.h>
#include <device/pci.h>
#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <string.h>
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 17, 0xfec00000);
+ smp_write_ioapic(mc, 2, 17, IO_APIC_ADDR);
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
#include <arch/io.h>
#include <console/console.h>
-
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
-
#include <pc80/mc146818rtc.h>
#include <pc80/i8259.h>
#include <pc80/keyboard.h>
#include <pc80/isa-dma.h>
-
#include <cpu/x86/lapic.h>
#include <arch/ioapic.h>
#include <stdlib.h>
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
#define SB_EHCI_REG 0,0x10, 4,
#define VX800SB_APIC_ID 0x4
-#define VX800SB_APIC_BASE 0xfec00000ULL
#define VX800SB_APIC_DATA_OFFSET 0x10
#define VX800SB_APIC_ENTRY_NUMBER 0x40
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
#include <console/console.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
*/
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
#include <pc80/isa-dma.h>
#include <bitops.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "sb600.h"
static void lpc_init(device_t dev)
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* apic */
res = new_resource(dev, 0x74);
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 256 * 0x10;
res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */
res->align = 8;
#include <pc80/isa-dma.h>
#include <bitops.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "sb700.h"
static void lpc_init(device_t dev)
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* apic */
res = new_resource(dev, 0x74);
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 256 * 0x10;
res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */
res->align = 8;
#include <pc80/isa-dma.h>
#include <bitops.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "bcm5785.h"
static void lpc_init(device_t dev)
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
value |= (1 << 8)|(1<<7);
value |= (6 << 0)|(1<<13)|(1<<11);
pci_write_config32(dev, 0xd0, value);
- setup_ioapic(0xfec00000, 0); // don't rename IO APIC ID
+ setup_ioapic(IO_APIC_ADDR, 0); // don't rename IO APIC ID
/* disable reset timer */
pci_write_config8(dev, 0xd4, 0x02);
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
pci_write_config8(dev, 0x3c, 0xff);
/* Setup the ioapic */
- clear_ioapic(0xfec10000);
+ clear_ioapic(IO_APIC_ADDR + 0x10000);
}
static void pic_read_resources(device_t dev)
/* Report the pic1 mbar resource */
res = new_resource(dev, 0x44);
- res->base = 0xfec10000;
+ res->base = IO_APIC_ADDR + 0x10000;
res->size = 256;
res->limit = res->base + res->size -1;
res->align = 8;
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
#include <device/pci_ids.h>
#include <pc80/isa-dma.h>
#include <pc80/mc146818rtc.h>
+#include <arch/ioapic.h>
#include "i82371eb.h"
static void isa_init(struct device *dev)
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "i82801ax.h"
#define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */
static void i82801ax_enable_apic(struct device *dev)
{
u32 reg32;
- volatile u32 *ioapic_index = (volatile u32 *)0xfec00000;
- volatile u32 *ioapic_data = (volatile u32 *)0xfec00010;
+ volatile u32 *ioapic_index = (volatile u32 *)IO_APIC_ADDR;
+ volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
/* Set ACPI base address (I/O space). */
pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "i82801bx.h"
#define NMI_OFF 0
static void i82801bx_enable_apic(struct device *dev)
{
uint32_t reg32;
- volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000;
- volatile uint32_t *ioapic_data = (volatile uint32_t *)0xfec00010;
+ volatile uint32_t *ioapic_index = (volatile uint32_t *)IO_APIC_ADDR;
+ volatile uint32_t *ioapic_data = (volatile uint32_t *)(IO_APIC_ADDR + 0x10);
/* Set ACPI base address (I/O space). */
pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "i82801cx.h"
#define NMI_OFF 0
static void i82801cx_enable_ioapic( struct device *dev)
{
uint32_t dword;
- volatile uint32_t* ioapic_index = (volatile uint32_t*)0xfec00000;
- volatile uint32_t* ioapic_data = (volatile uint32_t*)0xfec00010;
+ volatile uint32_t* ioapic_index = (volatile uint32_t*)IO_APIC_ADDR;
+ volatile uint32_t* ioapic_data = (volatile uint32_t*)(IO_APIC_ADDR + 0x10);
dword = pci_read_config32(dev, GEN_CNTL);
dword |= (3 << 7); /* enable ioapic & disable SMBus interrupts */
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
extern void i82801dx_enable(device_t dev);
#endif
-#define IO_APIC_ADDR 0xfec00000
-
/*
* HPET Memory Address Range. Possible values:
* 0xfed00000 for FED0_0000h - FED0_03FFh
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "i82801dx.h"
#define NMI_OFF 0
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
#define DEFAULT_GPIOBASE 0x0480
#define DEFAULT_PMBASE 0x0500
-#define IO_APIC_ADDR 0xfec00000
#define HPET_ADDR 0xfed00000
#define DEFAULT_RCBA 0xfed1c000
#include <pc80/isa-dma.h>
#include <pc80/i8259.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "i82801gx.h"
#define NMI_OFF 0
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
-
#include <pc80/mc146818rtc.h>
-
+#include <arch/ioapic.h>
#include "chip.h"
/* PIRQ init
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
-
#include <pc80/mc146818rtc.h>
-
+#include <arch/ioapic.h>
#include "chip.h"
/* The epia-m is really short on interrupts available, so PCI interupts A & D are ganged togther and so are B & C.
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
#define VT8237S_SPI_MEM_BASE 0xfed02000UL
#endif
#define VT8237R_HPET_ADDR 0xfed00000ULL
-#define VT8237R_APIC_BASE 0xfec00000ULL
/* IDE */
#define IDE_CS 0x40
/* Fixed APIC resource */
res = new_resource(dev, 0x44);
- res->base = VT8237R_APIC_BASE;
+ res->base = IO_APIC_ADDR;
res->size = 256;
res->limit = 0xffffffffUL;
res->align = 8;
{
vt8237_common_init(dev);
pci_routing_fixup(dev);
- setup_ioapic(VT8237R_APIC_BASE, VT8237R_APIC_ID);
+ setup_ioapic(IO_APIC_ADDR, VT8237R_APIC_ID);
setup_i8259();
init_keyboard(dev);
}
char *preamble[] = {
"#include <console/console.h>",
"#include <arch/smp/mpspec.h>",
+"#include <arch/ioapic.h>",
"#include <device/pci.h>",
"#include <string.h>",
"#include <stdint.h>",
};
char *ioapic_code[] = {
-" smp_write_ioapic(mc, 2, 0x20, 0xfec00000);",
+" smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);",
" {",
" device_t dev;",
" struct resource *res;",