src/cpu/amd/sc520/sc520.c

   1 /*
   2  * This file needs a major cleanup. Too much #if 0 code
   3  */
   4
   5 #include <console/console.h>
   6 #include <arch/io.h>
   7 #include <arch/ioapic.h>
   8 #include <stdint.h>
   9 #include <device/device.h>
  10 #include <device/pci.h>
  11 #include <device/pci_ids.h>
  12 #include <device/hypertransport.h>
  13 #include <stdlib.h>
  14 #include <string.h>
  15 #include <bitops.h>
  16 #include <delay.h>
  17 #include "chip.h"
  18
  19 /*
  20  * set up basic things ...
  21  * PAR should NOT go here, as it might change with the mainboard.
  22  */
  23 static void cpu_init(device_t dev)
  24 {
  25   unsigned long *l = (unsigned long *) 0xfffef088;
  26   int i;
  27   for(i = 0; i < 16; i++, l++)
  28     printk(BIOS_ERR, "Par%d: 0x%lx\n", i, *l);
  29
  30   printk(BIOS_SPEW, "SC520 random fixup ...\n");
  31 }
  32
  33
  34 /* Ollie says: make a northbridge/amd/sc520. Ron sez:
  35  * there is no real northbridge, keep it here in cpu.
  36  * Ron wins, he's writing the code.
  37  */
  38 static void sc520_enable_resources(struct device *dev) {
  39         unsigned char command;
  40
  41         printk(BIOS_SPEW, "%s\n", __func__);
  42         command = pci_read_config8(dev, PCI_COMMAND);
  43         printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command);
  44         command |= PCI_COMMAND_MEMORY | PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
  45         printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command);
  46         pci_write_config8(dev, PCI_COMMAND, command);
  47         command = pci_read_config8(dev, PCI_COMMAND);
  48         printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command);
  49 /*
  50  */
  51
  52 }
  53
  54 static void sc520_read_resources(device_t dev)
  55 {
  56         struct resource* res;
  57
  58         pci_dev_read_resources(dev);
  59
  60         res = new_resource(dev, 1);
  61         res->base = 0x0UL;
  62         res->size = 0x400UL;
  63         res->limit = 0xffffUL;
  64         res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  65
  66         res = new_resource(dev, 3); /* IOAPIC */
  67         res->base = IO_APIC_ADDR;
  68         res->size = 0x00001000;
  69         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  70 }
  71
  72
  73 static struct device_operations cpu_operations = {
  74         .read_resources   = sc520_read_resources,
  75         .set_resources    = pci_dev_set_resources,
  76         .enable_resources = sc520_enable_resources,
  77         .init             = cpu_init,
  78         .enable           = 0,
  79         .ops_pci          = 0,
  80 };
  81
  82 static const struct pci_driver cpu_driver __pci_driver = {
  83         .ops = &cpu_operations,
  84         .vendor = PCI_VENDOR_ID_AMD,
  85         .device = 0x3000
  86 };
  87
  88 static void pci_domain_set_resources(device_t dev)
  89 {
  90         device_t mc_dev;
  91         uint32_t pci_tolm;
  92   printk(BIOS_SPEW, "%s\n", __func__);
  93         pci_tolm = find_pci_tolm(dev->link_list);
  94         mc_dev = dev->link_list->children;
  95         if (mc_dev) {
  96                 unsigned long tomk, tolmk;
  97                 //              unsigned char rambits;
  98                 // int i;
  99                 int idx;
 100 #if 0
 101                 for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
 102                         unsigned char reg;
 103                         reg = pci_read_config8(mc_dev, ramregs[i]);
 104                         /* these are ENDING addresses, not sizes.
 105                          * if there is memory in this slot, then reg will be > rambits.
 106                          * So we just take the max, that gives us total.
 107                          * We take the highest one to cover for once and future coreboot
 108                          * bugs. We warn about bugs.
 109                          */
 110                         if (reg > rambits)
 111                                 rambits = reg;
 112                         if (reg < rambits)
 113                                 printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
 114                                         ramregs[i]);
 115                 }
 116                 printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
 117                 tomk = rambits*8*1024;
 118 #endif
 119                 tomk = 32 * 1024;
 120                 /* Compute the top of Low memory */
 121                 tolmk = pci_tolm >> 10;
 122                 if (tolmk >= tomk) {
 123                         /* The PCI hole does does not overlap the memory.
 124                          */
 125                         tolmk = tomk;
 126                 }
 127                 /* Report the memory regions */
 128                 idx = 10;
 129                 ram_resource(dev, idx++, 0, tolmk);
 130         }
 131         assign_resources(dev->link_list);
 132 }
 133
 134 #if 0
 135 void sc520_enable_resources(device_t dev) {
 136
 137         printk(BIOS_SPEW, "%s\n", __func__);
 138         printk(BIOS_SPEW, "THIS IS FOR THE SC520 =============================\n");
 139
 140 /*
 141         command = pci_read_config8(dev, PCI_COMMAND);
 142         printk(BIOS_SPEW, "%s, command 0x%x\n", __func__, command);
 143         command |= PCI_COMMAND_MEMORY;
 144         printk(BIOS_SPEW, "%s, command 0x%x\n", __func__, command);
 145         pci_write_config8(dev, PCI_COMMAND, command);
 146         command = pci_read_config8(dev, PCI_COMMAND);
 147         printk(BIOS_SPEW, "%s, command 0x%x\n", __func__, command);
 148  */
 149         enable_childrens_resources(dev);
 150         printk(BIOS_SPEW, "%s\n", __func__);
 151 }
 152 #endif
 153
 154 static struct device_operations pci_domain_ops = {
 155         .read_resources   = pci_domain_read_resources,
 156         .set_resources    = pci_domain_set_resources,
 157         /*
 158          * If enable_resources is set to the generic enable_resources
 159          * function the whole thing will hang in an endless loop on
 160          * the ts5300. If this is really needed on another platform,
 161          * something is conceptually wrong.
 162          */
 163         .enable_resources = 0, //enable_resources,
 164         .init             = 0,
 165         .scan_bus         = pci_domain_scan_bus,
 166 };
 167
 168 #if 0
 169 static void cpu_bus_init(device_t dev)
 170 {
 171   printk(BIOS_SPEW, "cpu_bus_init\n");
 172 }
 173
 174 static void cpu_bus_noop(device_t dev)
 175 {
 176 }
 177
 178 static struct device_operations cpu_bus_ops = {
 179         .read_resources   = cpu_bus_noop,
 180         .set_resources    = cpu_bus_noop,
 181         .enable_resources = cpu_bus_noop,
 182         .init             = cpu_bus_init,
 183         .scan_bus         = 0,
 184 };
 185 #endif
 186
 187 static void enable_dev(struct device *dev)
 188 {
 189   printk(BIOS_SPEW, "%s\n", __func__);
 190         /* Set the operations if it is a special bus type */
 191         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 192                 dev->ops = &pci_domain_ops;
 193                 pci_set_method(dev);
 194         }
 195 #if 0
 196         /* This is never hit as none of the sc520 boards have
 197          * an APIC cluster defined
 198          */
 199         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 200                 dev->ops = &cpu_bus_ops;
 201         }
 202 #endif
 203 }
 204
 205
 206 struct chip_operations cpu_amd_sc520_ops = {
 207         CHIP_NAME("AMD Elan SC520 CPU")
 208         .enable_dev = enable_dev,
 209 };