1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
6 #if CONFIG_LOGICAL_CPUS==1
7 #include <cpu/amd/multicore.h>
11 static unsigned node_link_to_bus(unsigned node, unsigned link)
16 dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
20 for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
25 config_map = pci_read_config32(dev, reg);
26 if ((config_map & 3) != 3) {
29 dst_node = (config_map >> 4) & 7;
30 dst_link = (config_map >> 8) & 3;
31 bus_base = (config_map >> 16) & 0xff;
33 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
34 dst_node, dst_link, bus_base,
37 if ((dst_node == node) && (dst_link == link))
46 static void *smp_write_config_table(void *v)
48 static const char sig[4] = "PCMP";
49 static const char oem[8] = "COREBOOT";
50 static const char productid[12] = "S2880 ";
51 struct mp_config_table *mc;
54 unsigned char bus_chain_0;
55 unsigned char bus_8131_1;
56 unsigned char bus_8131_2;
57 unsigned char bus_8111_1;
60 unsigned apicid_8131_1;
61 unsigned apicid_8131_2;
63 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
64 memset(mc, 0, sizeof(*mc));
66 memcpy(mc->mpc_signature, sig, sizeof(sig));
67 mc->mpc_length = sizeof(*mc); /* initially just the header */
69 mc->mpc_checksum = 0; /* not yet computed */
70 memcpy(mc->mpc_oem, oem, sizeof(oem));
71 memcpy(mc->mpc_productid, productid, sizeof(productid));
74 mc->mpc_entry_count = 0; /* No entries yet... */
75 mc->mpc_lapic = LAPIC_ADDR;
80 smp_write_processors(mc);
86 bus_chain_0 = node_link_to_bus(0, 0);
87 if (bus_chain_0 == 0) {
88 printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n");
93 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
95 bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
98 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
103 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
105 bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
109 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
114 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
116 bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
120 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
127 mptable_write_buses(mc, NULL, &bus_isa);
129 /*I/O APICs: APIC ID Version State Address*/
130 #if CONFIG_LOGICAL_CPUS==1
131 apicid_base = get_apicid_base(3);
133 apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
135 apicid_8111 = apicid_base+0;
136 apicid_8131_1 = apicid_base+1;
137 apicid_8131_2 = apicid_base+2;
138 smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000);
142 struct resource *res;
143 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1));
145 res = find_resource(dev, PCI_BASE_ADDRESS_0);
147 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
150 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1));
152 res = find_resource(dev, PCI_BASE_ADDRESS_0);
154 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
160 mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
162 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
163 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|0, apicid_8111, 0x13);
167 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
169 //On Board ATI Display Adapter
170 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12);
173 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, apicid_8111, 0x10);
174 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, apicid_8111, 0x11);
175 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, apicid_8111, 0x12); //
176 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, apicid_8111, 0x13); //
178 //On Board Promise Serial ATA
179 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x11);
182 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|0, apicid_8131_1, 0x3);
183 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|1, apicid_8131_1, 0x0);
184 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|2, apicid_8131_1, 0x1);//
185 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|3, apicid_8131_1, 0x2);//
188 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|0, apicid_8131_1, 0x2);
189 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|1, apicid_8131_1, 0x3);//
190 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|2, apicid_8131_1, 0x0);//
191 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|3, apicid_8131_1, 0x1);//
193 //On Board NIC and LSI scsi
194 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0);
195 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, apicid_8131_1, 0x1);
196 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|0, apicid_8131_1, 0x0);
197 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|1, apicid_8131_1, 0x1);
199 //Slot 1 PCI-X 133/100/66
200 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0);
201 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x1);
202 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); //
203 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); //
205 //Slot 2 PCI-X 133/100/66
206 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|0, apicid_8131_2, 0x1);
207 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|1, apicid_8131_2, 0x2);
208 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|2, apicid_8131_2, 0x3);//
209 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|3, apicid_8131_2, 0x0);//
211 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
212 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
213 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
214 /* There is no extension information... */
216 /* Compute the checksums */
217 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
218 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
219 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
220 mc, smp_next_mpe_entry(mc));
221 return smp_next_mpe_entry(mc);
224 unsigned long write_smp_table(unsigned long addr)
227 v = smp_write_floating_table(addr);
228 return (unsigned long)smp_write_config_table(v);