src/southbridge/broadcom/bcm5785/bcm5785_lpc.c

   1 /*
   2  * Copyright  2005 AMD
   3  *  by yinghai.lu@amd.com
   4  */
   5
   6 #include <console/console.h>
   7 #include <device/device.h>
   8 #include <device/pci.h>
   9 #include <device/pnp.h>
  10 #include <device/pci_ids.h>
  11 #include <device/pci_ops.h>
  12 #include <pc80/mc146818rtc.h>
  13 #include <pc80/isa-dma.h>
  14 #include <bitops.h>
  15 #include <arch/io.h>
  16 #include <arch/ioapic.h>
  17 #include "bcm5785.h"
  18
  19 static void lpc_init(device_t dev)
  20 {
  21
  22         /* Initialize the real time clock */
  23         rtc_init(0);
  24
  25         /* Initialize isa dma */
  26         isa_dma_init();
  27
  28 }
  29
  30 static void bcm5785_lpc_read_resources(device_t dev)
  31 {
  32         struct resource *res;
  33
  34         /* Get the normal pci resources of this device */
  35         pci_dev_read_resources(dev);
  36
  37         /* Add an extra subtractive resource for both memory and I/O. */
  38         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
  39         res->base = 0;
  40         res->size = 0x1000;
  41         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
  42                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  43
  44         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
  45         res->base = 0xff800000;
  46         res->size = 0x00800000; /* 8 MB for flash */
  47         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
  48                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  49
  50         res = new_resource(dev, 3); /* IOAPIC */
  51         res->base = IO_APIC_ADDR;
  52         res->size = 0x00001000;
  53         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  54 }
  55
  56 /**
  57  * @brief Enable resources for children devices
  58  *
  59  * @param dev the device whos children's resources are to be enabled
  60  *
  61  */
  62 static void bcm5785_lpc_enable_childrens_resources(device_t dev)
  63 {
  64         struct bus *link;
  65         uint32_t reg;
  66
  67         reg = pci_read_config8(dev, 0x44);
  68
  69         for (link = dev->link_list; link; link = link->next) {
  70                 device_t child;
  71                 for (child = link->children; child; child = child->sibling) {
  72                         if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
  73                                 struct resource *res;
  74                                 for(res = child->resource_list; res; res = res->next) {
  75                                         unsigned long base, end; // don't need long long
  76                                         if(!(res->flags & IORESOURCE_IO)) continue;
  77                                         base = res->base;
  78                                         end = resource_end(res);
  79                                         printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
  80                                         switch(base) {
  81                                         case 0x60: //KBC
  82                                         case 0x64:
  83                                                 reg |= (1<<29);
  84                                         case 0x3f8: // COM1
  85                                                 reg |= (1<<6);  break;
  86                                         case 0x2f8: // COM2
  87                                                 reg |= (1<<7);  break;
  88                                         case 0x378: // Parallal 1
  89                                                 reg |= (1<<0); break;
  90                                         case 0x3f0: // FD0
  91                                                 reg |= (1<<26); break;
  92                                         case 0x220:  // Aduio 0
  93                                                 reg |= (1<<14); break;
  94                                         case 0x300:  // Midi 0
  95                                                 reg |= (1<<18); break;
  96                                         }
  97                                 }
  98                         }
  99                 }
 100         }
 101         pci_write_config32(dev, 0x44, reg);
 102
 103
 104 }
 105
 106 static void bcm5785_lpc_enable_resources(device_t dev)
 107 {
 108         pci_dev_enable_resources(dev);
 109         bcm5785_lpc_enable_childrens_resources(dev);
 110 }
 111
 112 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 113 {
 114         pci_write_config32(dev, 0x40,
 115                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 116 }
 117
 118 static struct pci_operations lops_pci = {
 119         .set_subsystem = lpci_set_subsystem,
 120 };
 121
 122 static struct device_operations lpc_ops  = {
 123         .read_resources   = bcm5785_lpc_read_resources,
 124         .set_resources    = pci_dev_set_resources,
 125         .enable_resources = bcm5785_lpc_enable_resources,
 126         .init             = lpc_init,
 127         .scan_bus         = scan_static_bus,
 128 //      .enable           = bcm5785_enable,
 129         .ops_pci          = &lops_pci,
 130 };
 131 static const struct pci_driver lpc_driver __pci_driver = {
 132         .ops    = &lpc_ops,
 133         .vendor = PCI_VENDOR_ID_SERVERWORKS,
 134         .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_LPC,
 135 };
 136