1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
7 static void *smp_write_config_table(void *v)
9 static const char sig[4] = "PCMP";
10 static const char oem[8] = "COREBOOT";
11 static const char productid[12] = "DK8X ";
12 struct mp_config_table *mc;
13 unsigned char bus_num;
14 unsigned char bus_isa;
15 unsigned char bus_8131_1;
16 unsigned char bus_8131_2;
17 unsigned char bus_8111_1;
19 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
20 memset(mc, 0, sizeof(*mc));
22 memcpy(mc->mpc_signature, sig, sizeof(sig));
23 mc->mpc_length = sizeof(*mc); /* initially just the header */
25 mc->mpc_checksum = 0; /* not yet computed */
26 memcpy(mc->mpc_oem, oem, sizeof(oem));
27 memcpy(mc->mpc_productid, productid, sizeof(productid));
30 mc->mpc_entry_count = 0; /* No entries yet... */
31 mc->mpc_lapic = LAPIC_ADDR;
36 smp_write_processors(mc);
42 dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
44 bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
45 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
49 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
55 dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
57 bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
61 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
66 dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
68 bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
72 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
78 /* define bus and isa numbers */
79 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
80 smp_write_bus(mc, bus_num, "PCI ");
82 smp_write_bus(mc, bus_isa, "ISA ");
85 smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
90 dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
92 res = find_resource(dev, PCI_BASE_ADDRESS_0);
94 smp_write_ioapic(mc, 0x03, 0x11, res->base);
98 dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
100 res = find_resource(dev, PCI_BASE_ADDRESS_0);
102 smp_write_ioapic(mc, 0x04, 0x11, res->base);
107 mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
109 /* Standard local interrupt assignments */
110 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
111 bus_isa, 0x00, MP_APIC_ALL, 0x00);
112 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
113 bus_isa, 0x00, MP_APIC_ALL, 0x01);
117 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
118 bus_8131_2, (1<<2)|0, 0x02, 0x11);
119 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
120 bus_8131_2, (1<<2)|1, 0x02, 0x12);
121 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
122 bus_8131_2, (1<<2)|2, 0x02, 0x13);
123 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
124 bus_8131_2, (1<<2)|3, 0x02, 0x10);
127 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
128 bus_8131_2, (2<<2)|0, 0x02, 0x12);
129 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
130 bus_8131_2, (2<<2)|1, 0x02, 0x13);
131 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
132 bus_8131_2, (2<<2)|2, 0x02, 0x10);
133 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
134 bus_8131_2, (2<<2)|3, 0x02, 0x11);
137 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
138 bus_8131_1, (1<<2)|0, 0x02, 0x11);
139 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
140 bus_8131_1, (1<<2)|1, 0x02, 0x12);
141 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
142 bus_8131_1, (1<<2)|2, 0x02, 0x13);
143 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
144 bus_8131_1, (1<<2)|3, 0x02, 0x10);
147 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
148 bus_8131_1, (2<<2)|0, 0x02, 0x12);
149 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
150 bus_8131_1, (2<<2)|1, 0x02, 0x13);
151 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
152 bus_8131_1, (2<<2)|2, 0x02, 0x10);
153 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
154 bus_8131_1, (2<<2)|3, 0x02, 0x11);
157 // FIXME get the irqs right, it's just hacked to work for now
158 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
159 bus_8111_1, (5<<2)|0, 0x02, 0x11);
160 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
161 bus_8111_1, (5<<2)|1, 0x02, 0x12);
162 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
163 bus_8111_1, (5<<2)|2, 0x02, 0x13);
164 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
165 bus_8111_1, (5<<2)|3, 0x02, 0x10);
168 // FIXME get the irqs right, it's just hacked to work for now
169 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
170 bus_8111_1, (4<<2)|0, 0x02, 0x10);
171 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
172 bus_8111_1, (4<<2)|1, 0x02, 0x11);
173 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
174 bus_8111_1, (4<<2)|2, 0x02, 0x12);
175 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
176 bus_8111_1, (4<<2)|3, 0x02, 0x13);
179 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
180 bus_8131_1, (3<<2)|0, 0x02, 0x13);
181 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
182 bus_8131_1, (4<<2)|0, 0x02, 0x13);
184 /* There is no extension information... */
186 /* Compute the checksums */
187 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
188 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
189 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
190 mc, smp_next_mpe_entry(mc));
191 return smp_next_mpe_entry(mc);
194 unsigned long write_smp_table(unsigned long addr)
197 v = smp_write_floating_table(addr);
198 return (unsigned long)smp_write_config_table(v);