1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
6 #if CONFIG_LOGICAL_CPUS==1
7 #include <cpu/amd/multicore.h>
10 static unsigned node_link_to_bus(unsigned node, unsigned link)
15 dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
19 for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
24 config_map = pci_read_config32(dev, reg);
25 if ((config_map & 3) != 3) {
28 dst_node = (config_map >> 4) & 7;
29 dst_link = (config_map >> 8) & 3;
30 bus_base = (config_map >> 16) & 0xff;
32 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
33 dst_node, dst_link, bus_base,
36 if ((dst_node == node) && (dst_link == link))
44 static void *smp_write_config_table(void *v)
46 static const char sig[4] = "PCMP";
47 static const char oem[8] = "COREBOOT";
48 static const char productid[12] = "S4880 ";
49 struct mp_config_table *mc;
52 unsigned char bus_chain_0;
53 unsigned char bus_8131_1;
54 unsigned char bus_8131_2;
55 unsigned char bus_8111_1;
58 unsigned apicid_8131_1;
59 unsigned apicid_8131_2;
61 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
62 memset(mc, 0, sizeof(*mc));
64 memcpy(mc->mpc_signature, sig, sizeof(sig));
65 mc->mpc_length = sizeof(*mc); /* initially just the header */
67 mc->mpc_checksum = 0; /* not yet computed */
68 memcpy(mc->mpc_oem, oem, sizeof(oem));
69 memcpy(mc->mpc_productid, productid, sizeof(productid));
72 mc->mpc_entry_count = 0; /* No entries yet... */
73 mc->mpc_lapic = LAPIC_ADDR;
78 smp_write_processors(mc);
85 bus_chain_0 = node_link_to_bus(0, 2);
86 if (bus_chain_0 == 0) {
87 printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n");
92 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
94 bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
97 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
102 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
104 bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
108 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
113 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
115 bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
119 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
126 mptable_write_buses(mc, NULL, &bus_isa);
128 /*I/O APICs: APIC ID Version State Address*/
129 #if CONFIG_LOGICAL_CPUS==1
130 apicid_base = get_apicid_base(3);
132 apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
134 apicid_8111 = apicid_base+0;
135 apicid_8131_1 = apicid_base+1;
136 apicid_8131_2 = apicid_base+2;
138 smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000);
141 struct resource *res;
142 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1));
144 res = find_resource(dev, PCI_BASE_ADDRESS_0);
146 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
149 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1));
151 res = find_resource(dev, PCI_BASE_ADDRESS_0);
153 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
159 mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
161 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
162 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|0, apicid_8111, 0x13);
166 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
168 //On Board Via USB 1.1 and 2
169 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|0, apicid_8111, 0x11); //1.1
170 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|1, apicid_8111, 0x10); //1.1
171 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|2, apicid_8111, 0x12); //2
174 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, apicid_8111, 0x10);
175 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, apicid_8111, 0x11);
176 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, apicid_8111, 0x12); //
177 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, apicid_8111, 0x13); //
180 //On Board SI Serial ATA
181 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x13);
182 //On Board ATI Display Adapter
183 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12);
187 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, apicid_8131_1, 0x3);
188 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, apicid_8131_1, 0x0);
189 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);//
190 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);//
193 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2);
194 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);//
195 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);//
196 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, apicid_8131_1, 0x1);//
198 //On Board LSI scsi and NIC
199 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|0, apicid_8131_1, 0x0);
200 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|1, apicid_8131_1, 0x1);
201 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0);
202 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, apicid_8131_1, 0x1);
204 //Slot 2 PCI-X 133/100/66
205 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0);
206 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x1);
207 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); //
208 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); //
210 //Slot 1 PCI-X 133/100/66
211 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, apicid_8131_2, 0x1);
212 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, apicid_8131_2, 0x2);
213 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, apicid_8131_2, 0x3);//
214 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);//
216 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
217 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
218 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
219 /* There is no extension information... */
221 /* Compute the checksums */
222 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
223 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
224 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
225 mc, smp_next_mpe_entry(mc));
226 return smp_next_mpe_entry(mc);
229 unsigned long write_smp_table(unsigned long addr)
232 v = smp_write_floating_table(addr);
233 return (unsigned long)smp_write_config_table(v);