1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <arch/ioapic.h>
4 #include <device/pci.h>
8 #include <cpu/amd/amdk8_sysconf.h>
10 extern unsigned char bus_isa;
11 extern unsigned char bus_8131_0;
12 extern unsigned char bus_8131_1;
13 extern unsigned char bus_8131_2;
14 extern unsigned char bus_8111_0;
15 extern unsigned char bus_8111_1;
16 extern unsigned apicid_8111;
17 extern unsigned apicid_8131_1;
18 extern unsigned apicid_8131_2;
20 extern unsigned sbdn3;
24 static void *smp_write_config_table(void *v)
26 static const char sig[4] = "PCMP";
27 static const char oem[8] = "COREBOOT";
28 static const char productid[12] = "S2881 ";
29 struct mp_config_table *mc;
31 unsigned char bus_num;
35 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
36 memset(mc, 0, sizeof(*mc));
38 memcpy(mc->mpc_signature, sig, sizeof(sig));
39 mc->mpc_length = sizeof(*mc); /* initially just the header */
41 mc->mpc_checksum = 0; /* not yet computed */
42 memcpy(mc->mpc_oem, oem, sizeof(oem));
43 memcpy(mc->mpc_productid, productid, sizeof(productid));
46 mc->mpc_entry_count = 0; /* No entries yet... */
47 mc->mpc_lapic = LAPIC_ADDR;
52 smp_write_processors(mc);
58 /* define bus and isa numbers */
59 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
60 smp_write_bus(mc, bus_num, "PCI ");
62 smp_write_bus(mc, bus_isa, "ISA ");
65 /*I/O APICs: APIC ID Version State Address*/
66 smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
70 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
72 res = find_resource(dev, PCI_BASE_ADDRESS_0);
74 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
77 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
79 res = find_resource(dev, PCI_BASE_ADDRESS_0);
81 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
87 mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
89 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
91 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|0, apicid_8111, 0x13);
93 //On Board AMD USB ???
94 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
96 //On Board ATI Display Adapter
97 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12);
99 //On Board SI Serial ATA
100 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x11);
104 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (3+i)%4); //27
107 //On Board NIC and adaptec scsi
109 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|i, apicid_8131_1, (0+i)%4); //24
110 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (0+i)%4); //24
113 //Slot 1 PCI-X 133/100/66 or Side 1 on raiser card
115 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|i, apicid_8131_2, (0+i)%4); //28
118 //Slot 1 PCI-X 133/100/66, Side 2 on raiser card
121 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (1+i)%4); //28
126 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
127 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
128 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
129 /* There is no extension information... */
131 /* Compute the checksums */
132 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
133 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
134 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
135 mc, smp_next_mpe_entry(mc));
136 return smp_next_mpe_entry(mc);
139 unsigned long write_smp_table(unsigned long addr)
142 v = smp_write_floating_table(addr);
143 return (unsigned long)smp_write_config_table(v);