2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
7 * (Thanks to LSRA University of Mannheim for their support)
8 * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 #include <console/console.h>
26 #include <arch/smp/mpspec.h>
27 #include <device/pci.h>
30 #include "southbridge/via/vt8237r/vt8237r.h"
32 static void *smp_write_config_table(void *v)
34 static const char sig[4] = "PCMP";
35 static const char oem[8] = "COREBOOT";
36 static const char productid[12] = "PC2500 ";
37 struct mp_config_table *mc;
41 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
42 memset(mc, 0, sizeof(*mc));
44 memcpy(mc->mpc_signature, sig, sizeof(sig));
45 mc->mpc_length = sizeof(*mc); /* initially just the header */
47 mc->mpc_checksum = 0; /* not yet computed */
48 memcpy(mc->mpc_oem, oem, sizeof(oem));
49 memcpy(mc->mpc_productid, productid, sizeof(productid));
52 mc->mpc_entry_count = 0; /* No entries yet... */
53 mc->mpc_lapic = LAPIC_ADDR;
58 smp_write_processors(mc);
59 mptable_write_buses(mc, NULL, &isa_bus);
61 /* I/O APICs: APIC ID Version State Address*/
62 smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VT8237R_APIC_BASE);
64 /* Now, assemble the table. */
65 mptable_add_isa_interrupts(mc, isa_bus, VT8237R_APIC_ID, 0);
67 #define PCI_INT(bus, dev, fn, pin) \
68 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, \
69 bus, (((dev)<<2)|(fn)), VT8237R_APIC_ID, (pin))
84 PCI_INT(0, 15, 1, 20);
87 PCI_INT(0, 16, 0, 21);
88 PCI_INT(0, 16, 1, 21);
89 PCI_INT(0, 16, 2, 21);
90 PCI_INT(0, 16, 3, 21);
93 PCI_INT(0, 17, 2, 22);
96 PCI_INT(0, 18, 0, 23);
101 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
102 smp_write_lintsrc(mc, mp_ExtINT,
103 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
104 0, 0x0, MP_APIC_ALL, 0x0);
105 smp_write_lintsrc(mc, mp_NMI,
106 MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
107 0, 0x0, MP_APIC_ALL, 0x1);
109 /* There is no extension information... */
111 /* Compute the checksums */
113 smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
114 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
115 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
116 mc, smp_next_mpe_entry(mc));
117 return smp_next_mpe_entry(mc);
120 unsigned long write_smp_table(unsigned long addr)
123 v = smp_write_floating_table(addr);
124 return (unsigned long)smp_write_config_table(v);