src/mainboard/amd/serengeti_cheetah_fam10/mptable.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <console/console.h>
  21 #include <arch/smp/mpspec.h>
  22 #include <device/pci.h>
  23 #include <string.h>
  24 #include <stdint.h>
  25 #if CONFIG_LOGICAL_CPUS==1
  26 #include <cpu/amd/multicore.h>
  27 #endif
  28
  29 #include <cpu/amd/amdfam10_sysconf.h>
  30 #include "mb_sysconf.h"
  31
  32
  33
  34 static void *smp_write_config_table(void *v)
  35 {
  36         static const char sig[4] = "PCMP";
  37         static const char oem[8] = "COREBOOT";
  38         static const char productid[12] = "SERENGETI    ";
  39         struct mp_config_table *mc;
  40
  41         int i;
  42         int j;
  43         struct mb_sysconf_t *m;
  44
  45         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  46         memset(mc, 0, sizeof(*mc));
  47
  48         memcpy(mc->mpc_signature, sig, sizeof(sig));
  49         mc->mpc_length = sizeof(*mc); /* initially just the header */
  50         mc->mpc_spec = 0x04;
  51         mc->mpc_checksum = 0; /* not yet computed */
  52         memcpy(mc->mpc_oem, oem, sizeof(oem));
  53         memcpy(mc->mpc_productid, productid, sizeof(productid));
  54         mc->mpc_oemptr = 0;
  55         mc->mpc_oemsize = 0;
  56         mc->mpc_entry_count = 0; /* No entries yet... */
  57         mc->mpc_lapic = LAPIC_ADDR;
  58         mc->mpe_length = 0;
  59         mc->mpe_checksum = 0;
  60         mc->reserved = 0;
  61
  62         smp_write_processors(mc);
  63
  64         get_bus_conf();
  65
  66         m = sysconf.mb;
  67
  68         /*Bus:  Bus ID  Type*/
  69         /* define bus and isa numbers */
  70         for(j= 0; j < 256 ; j++) {
  71                 if(m->bus_type[j])
  72                         smp_write_bus(mc, j, "PCI   ");
  73         }
  74         smp_write_bus(mc, m->bus_isa, "ISA   ");
  75
  76         /*I/O APICs:    APIC ID Version State   Address*/
  77         smp_write_ioapic(mc, m->apicid_8111, 0x11, 0xfec00000); //8111
  78         {
  79                 device_t dev;
  80                 struct resource *res;
  81                 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
  82                 if (dev) {
  83                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  84                         if (res) {
  85                                 smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
  86                         }
  87                 }
  88                 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
  89                 if (dev) {
  90                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  91                         if (res) {
  92                                 smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
  93                         }
  94                 }
  95
  96                 j = 0;
  97
  98                 for(i=1; i< sysconf.hc_possible_num; i++) {
  99                         if(!(sysconf.pci1234[i] & 0x1) ) continue;
 100
 101                         switch(sysconf.hcid[i]) {
 102                         case 1:
 103                         case 3:
 104                                 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
 105                                 if (dev) {
 106                                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
 107                                         if (res) {
 108                                                 smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
 109                                         }
 110                                 }
 111                                 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
 112                                 if (dev) {
 113                                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
 114                                         if (res) {
 115                                                 smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
 116                                         }
 117                                 }
 118                                 break;
 119                         }
 120                         j++;
 121                 }
 122
 123         }
 124
 125         mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_8111, 0);
 126
 127         /* I/O Ints:    Type    Polarity        Trigger         Bus ID          IRQ     APIC ID PIN#*/
 128 //??? What
 129         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
 130
 131         // Onboard AMD USB
 132          smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
 133
 134         //Slot 3  PCI 32
 135         for(i=0;i<4;i++) {
 136                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
 137         }
 138
 139
 140         // Slot 4 PCI 32
 141         for(i=0;i<4;i++) {
 142                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
 143         }
 144
 145
 146         // Slot 1 PCI-X 133/100/66
 147         for(i=0;i<4;i++) {
 148                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); //
 149         }
 150
 151
 152         //Slot 2 PCI-X 133/100/66
 153         for(i=0;i<4;i++) {
 154                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
 155         }
 156
 157         j = 0;
 158
 159         for(i=1; i< sysconf.hc_possible_num; i++) {
 160                 if(!(sysconf.pci1234[i] & 0x1) ) continue;
 161                 int ii;
 162                 int jj;
 163                 device_t dev;
 164                 struct resource *res;
 165                 switch(sysconf.hcid[i]) {
 166                 case 1:
 167                 case 3:
 168                         dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
 169                         if (dev) {
 170                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
 171                                 if (res) {
 172                                         for(jj=0; jj<4; jj++) {
 173                                                 //Slot 1 PCI-X 133/100/66
 174                                                 for(ii=0;ii<4;ii++) {
 175                                                         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj<<2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); //
 176                                                 }
 177                                         }
 178                                 }
 179                         }
 180
 181                         dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
 182                         if (dev) {
 183                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
 184                                 if (res) {
 185                                         for(jj=0; jj<4; jj++) {
 186                                                 //Slot 2 PCI-X 133/100/66
 187                                                 for(ii=0;ii<4;ii++) {
 188                                                         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj<<2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); //25
 189                                                 }
 190                                         }
 191                                 }
 192                         }
 193
 194                         break;
 195                 case 2:
 196
 197                 //  Slot AGP
 198                         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
 199                         break;
 200                 }
 201
 202                 j++;
 203          }
 204
 205
 206
 207         /* Local Ints:  Type    Polarity        Trigger         Bus ID          IRQ     APIC ID PIN#*/
 208         smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
 209         smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
 210         /* There is no extension information... */
 211
 212         /* Compute the checksums */
 213         mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 214         mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 215         printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 216                 mc, smp_next_mpe_entry(mc));
 217         return smp_next_mpe_entry(mc);
 218 }
 219
 220 unsigned long write_smp_table(unsigned long addr)
 221 {
 222         void *v;
 223         v = smp_write_floating_table(addr);
 224         return (unsigned long)smp_write_config_table(v);
 225 }