1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
7 static void *smp_write_config_table(void *v)
9 static const char sig[4] = "PCMP";
10 static const char oem[8] = "COREBOOT";
11 static const char productid[12] = "SE7520JR20 ";
12 struct mp_config_table *mc;
13 unsigned char bus_num;
14 unsigned char bus_isa;
15 unsigned char bus_pxhd_1;
16 unsigned char bus_pxhd_2;
17 unsigned char bus_pxhd_3 = 0;
18 unsigned char bus_pxhd_4 = 0;
19 unsigned char bus_pxhd_x = 0;
20 unsigned char bus_ich5r_1;
21 unsigned int bus_pxhd_id;
23 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
24 memset(mc, 0, sizeof(*mc));
26 memcpy(mc->mpc_signature, sig, sizeof(sig));
27 mc->mpc_length = sizeof(*mc); /* initially just the header */
29 mc->mpc_checksum = 0; /* not yet computed */
30 memcpy(mc->mpc_oem, oem, sizeof(oem));
31 memcpy(mc->mpc_productid, productid, sizeof(productid));
34 mc->mpc_entry_count = 0; /* No entries yet... */
35 mc->mpc_lapic = LAPIC_ADDR;
40 smp_write_processors(mc);
46 dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
48 bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
49 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
53 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1f.0, using defaults\n");
59 dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
61 bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
65 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
70 dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
72 bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
76 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
80 /* test for active riser with 2nd pxh device */
81 dev = dev_find_slot(0, PCI_DEVFN(0x06,0));
83 bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
84 if(bus_pxhd_id == 0x35998086) {
85 bus_pxhd_x = pci_read_config8(dev, PCI_SECONDARY_BUS);
87 dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x0,0));
89 bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
90 if(bus_pxhd_id == 0x03298086) {
91 bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
95 dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,2));
97 bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
98 if(bus_pxhd_id == 0x032a8086) {
99 bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
106 /* define bus and isa numbers */
107 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
108 smp_write_bus(mc, bus_num, "PCI ");
110 smp_write_bus(mc, bus_isa, "ISA ");
112 /* IOAPIC handling */
114 smp_write_ioapic(mc, 8, 0x20, 0xfec00000);
116 struct resource *res;
119 dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
121 res = find_resource(dev, PCI_BASE_ADDRESS_0);
123 smp_write_ioapic(mc, 0x09, 0x20, res->base);
127 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
130 dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
132 res = find_resource(dev, PCI_BASE_ADDRESS_0);
134 smp_write_ioapic(mc, 0x0a, 0x20, res->base);
138 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
142 if(bus_pxhd_3) { /* Active riser pxhd */
143 dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,1));
145 res = find_resource(dev, PCI_BASE_ADDRESS_0);
147 smp_write_ioapic(mc, 0x0b, 0x20, res->base);
151 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI %d:00.1\n",bus_pxhd_x);
155 if(bus_pxhd_4) { /* active riser pxhd */
156 dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,3));
158 res = find_resource(dev, PCI_BASE_ADDRESS_0);
160 smp_write_ioapic(mc, 0x0c, 0x20, res->base);
164 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI %d:00.3\n",bus_pxhd_x);
169 mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
171 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
172 bus_isa, 0x0a, 0x08, 0x10);
173 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
174 bus_isa, 0x0b, 0x08, 0x11);
175 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
176 bus_isa, 0x0a, 0x08, 0x10);
177 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
178 bus_isa, 0x07, 0x08, 0x13);
179 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
180 bus_isa, 0x0b, 0x08, 0x12);
181 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
182 bus_isa, 0x05, 0x08, 0x17);
183 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
184 bus_isa, 0x0b, 0x08, 0x12);
185 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
186 bus_isa, 0x07, 0x08, 0x13);
187 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
188 bus_isa, 0x0b, 0x08, 0x11);
189 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
190 bus_isa, 0x0a, 0x08, 0x10);
192 /* Standard local interrupt assignments */
193 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
194 bus_isa, 0x00, MP_APIC_ALL, 0x00);
195 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
196 bus_isa, 0x00, MP_APIC_ALL, 0x01);
198 /* FIXME verify I have the irqs handled for all of the risers */
200 /* 2:3.0 PCI Slot 1 */
201 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
202 bus_pxhd_1, (3<<2)|0, 0x9, 0x0);
203 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
204 bus_pxhd_1, (3<<2)|1, 0x9, 0x3);
205 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
206 bus_pxhd_1, (3<<2)|2, 0x9, 0x5);
207 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
208 bus_pxhd_1, (3<<2)|3, 0x9, 0x4);
211 /* 3:7.0 PCI Slot 2 */
212 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
213 bus_pxhd_2, (7<<2)|0, 0xa, 0x4);
214 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
215 bus_pxhd_2, (7<<2)|1, 0xa, 0x3);
216 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
217 bus_pxhd_2, (7<<2)|2, 0xa, 0x2);
218 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
219 bus_pxhd_2, (7<<2)|3, 0xa, 0x1);
221 /* PCI Slot 3 (if active riser) */
223 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
224 bus_pxhd_3, (1<<2)|0, 0xb, 0x0);
227 /* PCI Slot 4 (if active riser) */
229 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
230 bus_pxhd_4, (1<<2)|0, 0xc, 0x0);
234 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
235 bus_pxhd_1, (5<<2)|0, 0x9, 0x2);
238 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
239 bus_pxhd_1, (5<<2)|1, 0x9, 0x1);
242 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
243 bus_pxhd_2, (4<<2)|0, 0xa, 0x6);
246 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
247 bus_pxhd_2, (4<<2)|1, 0xa, 0x7);
250 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
251 bus_ich5r_1, (12<<2)|0, 0x8, 0x11);
253 /* There is no extension information... */
255 /* Compute the checksums */
256 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
258 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
259 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
260 mc, smp_next_mpe_entry(mc));
261 return smp_next_mpe_entry(mc);
264 unsigned long write_smp_table(unsigned long addr)
267 v = smp_write_floating_table(addr);
268 return (unsigned long)smp_write_config_table(v);