2 * (C) 2003 Linux Networx, SuSE Linux AG
3 * (C) 2004 Tyan Computer
4 * (c) 2005 Digital Design Corporation
6 #include <console/console.h>
7 #include <device/device.h>
8 #include <device/pci.h>
9 #include <device/pci_ids.h>
10 #include <device/pci_ops.h>
11 #include <pc80/mc146818rtc.h>
12 #include <pc80/isa-dma.h>
14 #include <arch/ioapic.h>
19 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
20 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
23 #define MAINBOARD_POWER_OFF 0
24 #define MAINBOARD_POWER_ON 1
27 static void i82801cx_enable_ioapic( struct device *dev)
30 volatile uint32_t* ioapic_index = (volatile uint32_t*)IO_APIC_ADDR;
31 volatile uint32_t* ioapic_data = (volatile uint32_t*)(IO_APIC_ADDR + 0x10);
33 dword = pci_read_config32(dev, GEN_CNTL);
34 dword |= (3 << 7); /* enable ioapic & disable SMBus interrupts */
35 dword |= (1 <<13); /* coprocessor error enable */
36 dword |= (1 << 1); /* delay transaction enable */
37 dword |= (1 << 2); /* DMA collection buf enable */
38 pci_write_config32(dev, GEN_CNTL, dword);
39 printk(BIOS_DEBUG, "ioapic southbridge enabled %x\n",dword);
41 // Must program the APIC's ID before using it
43 *ioapic_index = 0; // Select APIC ID register
44 *ioapic_data = (2<<24);
46 // Hang if the ID didn't take (chip not present?)
49 printk(BIOS_DEBUG, "Southbridge apic id = %x\n", (dword>>24) & 0xF);
53 *ioapic_index = 3; // Select Boot Configuration register
54 *ioapic_data = 1; // Use Processor System Bus to deliver interrupts
57 // This is how interrupts are received from the Super I/O chip
58 static void i82801cx_enable_serial_irqs( struct device *dev)
60 // Recognize serial IRQs, continuous mode, frame size 21, 4 clock start frame pulse width
61 pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0));
64 //----------------------------------------------------------------------------------
65 // Function: i82801cx_lpc_route_dma
67 // mask - identifies whether each channel should be used for PCI DMA
68 // (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0.
69 // Channel 4 is not used (reserved).
71 // Description: Route all DMA channels to either PCI or LPC.
73 static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask)
78 dmaConfig = pci_read_config16(dev, PCI_DMA_CFG);
79 dmaConfig &= 0x300; // Preserve reserved bits
80 for(channelIndex = 0; channelIndex < 8; channelIndex++) {
81 if (channelIndex == 4)
82 continue; // Register doesn't support channel 4
83 dmaConfig |= ((mask & (1 << channelIndex))? 3:1) << (channelIndex*2);
85 pci_write_config16(dev, PCI_DMA_CFG, dmaConfig);
88 static void i82801cx_rtc_init(struct device *dev)
92 int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
93 uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3);
95 rtc_failed = pmcon3 & RTC_BATTERY_DEAD;
97 // Clear the RTC_BATTERY_DEAD bit, but preserve
98 // the RTC_POWER_FAILED, G3 state, and reserved bits
99 // NOTE: RTC_BATTERY_DEAD and RTC_POWER_FAILED are "write-1-clear" bits
100 pmcon3 &= ~RTC_POWER_FAILED;
103 get_option(&pwr_on, "power_on_after_fail");
104 pmcon3 &= ~SLEEP_AFTER_POWER_FAIL;
106 pmcon3 |= SLEEP_AFTER_POWER_FAIL;
108 pci_write_config8(dev, GEN_PMCON_3, pmcon3);
109 printk(BIOS_INFO, "set power %s after power fail\n",
110 pwr_on ? "on" : "off");
112 // See if the Safe Mode jumper is set
113 dword = pci_read_config32(dev, GEN_STS);
114 rtc_failed |= dword & (1 << 2);
116 rtc_init(rtc_failed);
120 static void i82801cx_1f0_misc(struct device *dev)
122 // Prevent LPC disabling, enable parity errors, and SERR# (System Error)
123 pci_write_config16(dev, PCI_COMMAND, 0x014f);
125 // Set ACPI base address to 0x1100 (I/O space)
126 pci_write_config32(dev, PMBASE, 0x00001101);
128 // Enable ACPI I/O and power management
129 pci_write_config8(dev, ACPI_CNTL, 0x10);
131 // Set GPIO base address to 0x1180 (I/O space)
132 pci_write_config32(dev, GPIO_BASE, 0x00001181);
135 pci_write_config8(dev, GPIO_CNTL, 0x10);
137 // Route PIRQA to IRQ11, PIRQB to IRQ3, PIRQC to IRQ5, PIRQD to IRQ10
138 pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B);
140 // Route PIRQE to IRQ7. Leave PIRQF - PIRQH unrouted.
141 pci_write_config8(dev, PIRQE_ROUT, 0x07);
143 // Enable access to the upper 128 byte bank of CMOS RAM
144 pci_write_config8(dev, RTC_CONF, 0x04);
146 // Decode 0x3F8-0x3FF (COM1) for COMA port,
147 // 0x2F8-0x2FF (COM2) for COMB
148 pci_write_config8(dev, COM_DEC, 0x10);
150 // LPT decode defaults to 0x378-0x37F and 0x778-0x77F
151 // Floppy decode defaults to 0x3F0-0x3F5, 0x3F7
153 // Enable COMA, COMB, LPT, floppy;
154 // disable microcontroller, Super I/O, sound, gameport
155 pci_write_config16(dev, LPC_EN, 0x000F);
158 static void lpc_init(struct device *dev)
164 /* IO APIC initialization */
165 i82801cx_enable_ioapic(dev);
167 i82801cx_enable_serial_irqs(dev);
169 /* power after power fail */
170 /* FIXME this doesn't work! */
171 /* Which state do we want to goto after g3 (power restored)?
175 byte = pci_read_config8(dev, GEN_PMCON_3);
177 byte &= ~1; // Return to S0 (boot) after power is re-applied
179 byte |= 1; // Return to S5
180 pci_write_config8(dev, GEN_PMCON_3, byte);
181 printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off");
183 /* Set up NMI on errors */
185 byte &= ~(1 << 3); /* IOCHK# NMI Enable */
186 byte &= ~(1 << 2); /* PCI SERR# Enable */
189 nmi_option = NMI_OFF;
190 get_option(&nmi_option, "nmi");
192 byte &= ~(1 << 7); /* set NMI */
196 /* Initialize the real time clock */
197 i82801cx_rtc_init(dev);
199 i82801cx_lpc_route_dma(dev, 0xff);
201 /* Initialize isa dma */
204 i82801cx_1f0_misc(dev);
207 static void i82801cx_lpc_read_resources(device_t dev)
209 struct resource *res;
211 /* Get the normal PCI resources of this device. */
212 pci_dev_read_resources(dev);
214 /* Add an extra subtractive resource for both memory and I/O. */
215 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
218 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
219 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
221 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
222 res->base = 0xff800000;
223 res->size = 0x00800000; /* 8 MB for flash */
224 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
225 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
227 res = new_resource(dev, 3); /* IOAPIC */
228 res->base = IO_APIC_ADDR;
229 res->size = 0x00001000;
230 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
233 static struct device_operations lpc_ops = {
234 .read_resources = i82801cx_lpc_read_resources,
235 .set_resources = pci_dev_set_resources,
236 .enable_resources = pci_dev_enable_resources,
238 .scan_bus = scan_static_bus,
242 static const struct pci_driver lpc_driver __pci_driver = {
244 .vendor = PCI_VENDOR_ID_INTEL,
245 .device = PCI_DEVICE_ID_INTEL_82801CA_LPC,