2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Arastra, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 /* This code is based on src/mainboard/intel/jarrell/mptable.c */
23 #include <console/console.h>
24 #include <arch/smp/mpspec.h>
25 #include <device/pci.h>
29 static void *smp_write_config_table(void *v)
31 static const char sig[4] = "PCMP";
32 static const char oem[8] = "COREBOOT";
33 static const char productid[12] = "Mt. Arvon ";
34 struct mp_config_table *mc;
39 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
40 memset(mc, 0, sizeof(*mc));
42 memcpy(mc->mpc_signature, sig, sizeof(sig));
43 mc->mpc_length = sizeof(*mc); /* initially just the header */
45 mc->mpc_checksum = 0; /* not yet computed */
46 memcpy(mc->mpc_oem, oem, sizeof(oem));
47 memcpy(mc->mpc_productid, productid, sizeof(productid));
50 mc->mpc_entry_count = 0; /* No entries yet... */
51 mc->mpc_lapic = LAPIC_ADDR;
56 smp_write_processors(mc);
58 /* Define bus numbers */
59 smp_write_bus(mc, 0, "PCI ");
60 smp_write_bus(mc, bus_pci, "PCI ");
61 smp_write_bus(mc, bus_pcie_a, "PCI ");
62 smp_write_bus(mc, bus_isa, "ISA ");
65 smp_write_ioapic(mc, 0x01, 0x20, 0xfec00000);
67 mptable_add_isa_interrupts(mc, bus_isa, 0x1, 0);
69 /* Standard local interrupt assignments */
70 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
71 bus_isa, 0x00, MP_APIC_ALL, 0x00);
72 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
73 bus_isa, 0x00, MP_APIC_ALL, 0x01);
75 /* Internal PCI devices */
76 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
77 0, (0x01<<2)|0, 0x01, 0x10); /* DMA controller */
78 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
79 0, (0x02<<2)|0, 0x01, 0x10); /* PCIe port A */
80 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
81 0, (0x03<<2)|0, 0x01, 0x10); /* PCIe port A1 */
82 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
83 0, (0x1c<<2)|0, 0x01, 0x10); /* PCIe port B0 */
84 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
85 0, (0x1c<<2)|1, 0x01, 0x11); /* PCIe port B1 */
86 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
87 0, (0x1c<<2)|2, 0x01, 0x12); /* PCIe port B2 */
88 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
89 0, (0x1c<<2)|3, 0x01, 0x13); /* PCIe port B3 */
90 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
91 0, (0x1d<<2)|0, 0x01, 0x10); /* UHCI0/EHCI */
92 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
93 0, (0x1d<<2)|1, 0x01, 0x11); /* UHCI1 */
94 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
95 0, (0x1e<<2)|0, 0x01, 0x10); /* Audio */
96 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
97 0, (0x1e<<2)|1, 0x01, 0x11); /* Modem */
98 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
99 0, (0x1f<<2)|1, 0x01, 0x11); /* SATA/SMBus */
100 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
101 0, (0x1f<<2)|3, 0x01, 0x13); /* ? */
104 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
105 bus_pci, 0x00, 0x01, 0x10);
106 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
107 bus_pci, 0x01, 0x01, 0x11);
108 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
109 bus_pci, 0x02, 0x01, 0x12);
110 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
111 bus_pci, 0x03, 0x01, 0x13);
113 /* PCIe port A slot */
114 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
115 bus_pcie_a, 0x00, 0x01, 0x10);
116 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
117 bus_pcie_a, 0x01, 0x01, 0x11);
118 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
119 bus_pcie_a, 0x02, 0x01, 0x12);
120 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
121 bus_pcie_a, 0x03, 0x01, 0x13);
123 /* There is no extension information... */
125 /* Compute the checksums */
126 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
128 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
129 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
130 mc, smp_next_mpe_entry(mc));
131 return smp_next_mpe_entry(mc);
134 unsigned long write_smp_table(unsigned long addr)
137 v = smp_write_floating_table(addr);
138 return (unsigned long)smp_write_config_table(v);