1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <arch/ioapic.h>
4 #include <device/pci.h>
8 static void *smp_write_config_table(void *v)
10 static const char sig[4] = "PCMP";
11 static const char oem[8] = "COREBOOT";
12 static const char productid[12] = "KHEPRI ";
13 struct mp_config_table *mc;
14 unsigned char bus_num;
15 unsigned char bus_isa;
16 unsigned char bus_8131_1;
17 unsigned char bus_8131_2;
18 unsigned char bus_8111_1;
20 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
21 memset(mc, 0, sizeof(*mc));
23 memcpy(mc->mpc_signature, sig, sizeof(sig));
24 mc->mpc_length = sizeof(*mc); /* initially just the header */
26 mc->mpc_checksum = 0; /* not yet computed */
27 memcpy(mc->mpc_oem, oem, sizeof(oem));
28 memcpy(mc->mpc_productid, productid, sizeof(productid));
31 mc->mpc_entry_count = 0; /* No entries yet... */
32 mc->mpc_lapic = LAPIC_ADDR;
37 smp_write_processors(mc);
43 dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
45 bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
46 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
50 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
56 dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
58 bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
62 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
67 dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
69 bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
73 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
79 /* define bus and isa numbers */
80 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
81 smp_write_bus(mc, bus_num, "PCI ");
83 smp_write_bus(mc, bus_isa, "ISA ");
87 smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
92 dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
94 res = find_resource(dev, PCI_BASE_ADDRESS_0);
96 smp_write_ioapic(mc, 0x03, 0x11, res->base);
100 dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
102 res = find_resource(dev, PCI_BASE_ADDRESS_0);
104 smp_write_ioapic(mc, 0x04, 0x11, res->base);
109 mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
111 /* Standard local interrupt assignments */
112 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
113 bus_isa, 0x00, MP_APIC_ALL, 0x00);
114 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
115 bus_isa, 0x00, MP_APIC_ALL, 0x01);
119 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
120 bus_8131_2, (1<<2)|0, 0x02, 0x11);
121 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
122 bus_8131_2, (1<<2)|1, 0x02, 0x12);
123 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
124 bus_8131_2, (1<<2)|2, 0x02, 0x13);
125 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
126 bus_8131_2, (1<<2)|3, 0x02, 0x10);
129 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
130 bus_8131_2, (2<<2)|0, 0x02, 0x12);
131 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
132 bus_8131_2, (2<<2)|1, 0x02, 0x13);
133 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
134 bus_8131_2, (2<<2)|2, 0x02, 0x10);
135 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
136 bus_8131_2, (2<<2)|3, 0x02, 0x11);
139 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
140 bus_8131_1, (1<<2)|0, 0x02, 0x11);
141 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
142 bus_8131_1, (1<<2)|1, 0x02, 0x12);
143 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
144 bus_8131_1, (1<<2)|2, 0x02, 0x13);
145 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
146 bus_8131_1, (1<<2)|3, 0x02, 0x10);
149 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
150 bus_8131_1, (2<<2)|0, 0x02, 0x12);
151 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
152 bus_8131_1, (2<<2)|1, 0x02, 0x13);
153 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
154 bus_8131_1, (2<<2)|2, 0x02, 0x10);
155 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
156 bus_8131_1, (2<<2)|3, 0x02, 0x11);
159 // FIXME get the irqs right, it's just hacked to work for now
160 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
161 bus_8111_1, (5<<2)|0, 0x02, 0x11);
162 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
163 bus_8111_1, (5<<2)|1, 0x02, 0x12);
164 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
165 bus_8111_1, (5<<2)|2, 0x02, 0x13);
166 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
167 bus_8111_1, (5<<2)|3, 0x02, 0x10);
170 // FIXME get the irqs right, it's just hacked to work for now
171 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
172 bus_8111_1, (4<<2)|0, 0x02, 0x10);
173 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
174 bus_8111_1, (4<<2)|1, 0x02, 0x11);
175 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
176 bus_8111_1, (4<<2)|2, 0x02, 0x12);
177 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
178 bus_8111_1, (4<<2)|3, 0x02, 0x13);
181 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
182 bus_8131_1, (3<<2)|0, 0x02, 0x13);
183 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
184 bus_8131_1, (4<<2)|0, 0x02, 0x13);
186 /* There is no extension information... */
188 /* Compute the checksums */
189 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
190 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
191 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
192 mc, smp_next_mpe_entry(mc));
193 return smp_next_mpe_entry(mc);
196 unsigned long write_smp_table(unsigned long addr)
199 v = smp_write_floating_table(addr);
200 return (unsigned long)smp_write_config_table(v);