2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
23 #include <device/pnp.h>
24 #include <device/pci_ids.h>
25 #include <device/pci_ops.h>
26 #include <pc80/mc146818rtc.h>
27 #include <pc80/isa-dma.h>
30 #include <arch/ioapic.h>
33 static void lpc_init(device_t dev)
39 /* Enable the LPC Controller */
40 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
41 dword = pci_read_config32(sm_dev, 0x64);
43 pci_write_config32(sm_dev, 0x64, dword);
45 /* Initialize isa dma */
48 /* RPR 7.2 Enable DMA transaction on the LPC bus */
49 byte = pci_read_config8(dev, 0x40);
51 pci_write_config8(dev, 0x40, byte);
53 /* RPR 7.3 Disable the timeout mechanism on LPC */
54 byte = pci_read_config8(dev, 0x48);
56 pci_write_config8(dev, 0x48, byte);
58 /* RPR 7.5 Disable LPC MSI Capability */
59 byte = pci_read_config8(dev, 0x78);
61 pci_write_config8(dev, 0x78, byte);
65 static void sb600_lpc_read_resources(device_t dev)
69 /* Get the normal pci resources of this device */
70 pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
72 pci_get_resource(dev, 0xA0); /* SPI ROM base address */
74 /* Add an extra subtractive resource for both memory and I/O. */
75 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
78 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
79 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
81 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
82 res->base = 0xff800000;
83 res->size = 0x00800000; /* 8 MB for flash */
84 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
85 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
87 res = new_resource(dev, 3); /* IOAPIC */
88 res->base = IO_APIC_ADDR;
89 res->size = 0x00001000;
90 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
92 compact_resources(dev);
96 * @brief Enable resources for children devices
98 * @param dev the device whos children's resources are to be enabled
101 static void sb600_lpc_enable_childrens_resources(device_t dev)
108 reg = pci_read_config32(dev, 0x44);
109 reg_x = pci_read_config32(dev, 0x48);
111 for (link = dev->link_list; link; link = link->next) {
113 for (child = link->children; child;
114 child = child->sibling) {
116 && (child->path.type == DEVICE_PATH_PNP)) {
117 struct resource *res;
118 for (res = child->resource_list; res; res = res->next) {
119 u32 base, end; /* don't need long long */
120 if (!(res->flags & IORESOURCE_IO))
123 end = resource_end(res);
124 printk(BIOS_DEBUG, "sb600 lpc decode:%s, base=0x%08x, end=0x%08x\n",
125 dev_path(child), base, end);
131 case 0x3f8: /* COM1 */
134 case 0x2f8: /* COM2 */
137 case 0x378: /* Parallal 1 */
140 case 0x3f0: /* FD0 */
143 case 0x220: /* Aduio 0 */
146 case 0x300: /* Midi 0 */
169 continue; /* only 3 var ; compact them ? */
188 pci_write_config32(dev, 0x44, reg);
189 pci_write_config32(dev, 0x48, reg_x);
190 /* Set WideIO for as many IOs found (fall through is on purpose) */
193 pci_write_config16(dev, 0x90, reg_var[2]);
195 pci_write_config16(dev, 0x66, reg_var[1]);
197 pci_write_config16(dev, 0x64, reg_var[0]);
202 static void sb600_lpc_enable_resources(device_t dev)
204 pci_dev_enable_resources(dev);
205 sb600_lpc_enable_childrens_resources(dev);
208 static struct pci_operations lops_pci = {
209 .set_subsystem = pci_dev_set_subsystem,
212 static struct device_operations lpc_ops = {
213 .read_resources = sb600_lpc_read_resources,
214 .set_resources = pci_dev_set_resources,
215 .enable_resources = sb600_lpc_enable_resources,
217 .scan_bus = scan_static_bus,
218 /* .enable = sb600_enable, */
219 .ops_pci = &lops_pci,
221 static const struct pci_driver lpc_driver __pci_driver = {
223 .vendor = PCI_VENDOR_ID_ATI,
224 .device = PCI_DEVICE_ID_ATI_SB600_LPC,