1 /* generated by MPTable, version 2.0.15*/
2 /* as modified by RGM for coreboot */
3 #include <console/console.h>
4 #include <arch/smp/mpspec.h>
5 #include <arch/ioapic.h>
6 #include <device/pci.h>
10 static void *smp_write_config_table(void *v)
12 static const char sig[4] = "PCMP";
13 static const char oem[8] = "COREBOOT";
14 static const char productid[12] = "P4DPE ";
15 struct mp_config_table *mc;
18 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
19 memset(mc, 0, sizeof(*mc));
21 memcpy(mc->mpc_signature, sig, sizeof(sig));
22 mc->mpc_length = sizeof(*mc); /* initially just the header */
24 mc->mpc_checksum = 0; /* not yet computed */
25 memcpy(mc->mpc_oem, oem, sizeof(oem));
26 memcpy(mc->mpc_productid, productid, sizeof(productid));
29 mc->mpc_entry_count = 0; /* No entries yet... */
30 mc->mpc_lapic = LAPIC_ADDR;
35 smp_write_processors(mc);
36 mptable_write_buses(mc, NULL, &isa_bus);
38 /*I/O APICs: APIC ID Version State Address*/
39 smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
43 dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
45 res = find_resource(dev, PCI_BASE_ADDRESS_0);
47 smp_write_ioapic(mc, 3, 0x20, res->base);
50 dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
52 res = find_resource(dev, PCI_BASE_ADDRESS_0);
54 smp_write_ioapic(mc, 4, 0x20, res->base);
57 dev = dev_find_slot(4, PCI_DEVFN(0x1e,0));
59 res = find_resource(dev, PCI_BASE_ADDRESS_0);
61 smp_write_ioapic(mc, 5, 0x20, res->base);
64 dev = dev_find_slot(4, PCI_DEVFN(0x1c,0));
66 res = find_resource(dev, PCI_BASE_ADDRESS_0);
68 smp_write_ioapic(mc, 8, 0x20, res->base);
72 mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
74 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
75 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x15);
76 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x15);
77 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x2, 0x15);
78 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x2, 0x15);
79 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x42, 0x2, 0x15);
80 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x46, 0x2, 0x16);
81 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
82 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x48, 0x2, 0x17);
83 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x3d, 0x2, 0x14);
84 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
85 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0);
86 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1);
87 /* There is no extension information... */
89 /* Compute the checksums */
90 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
91 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
92 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
93 mc, smp_next_mpe_entry(mc));
94 return smp_next_mpe_entry(mc);
97 unsigned long write_smp_table(unsigned long addr)
100 v = smp_write_floating_table(addr);
101 return (unsigned long)smp_write_config_table(v);