2 * This file is part of the coreboot project.
4 * Copyright (C) 2003 Linux Networx
5 * Copyright (C) 2003 SuSE Linux AG
6 * Copyright (C) 2004 Tyan Computer
7 * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
8 * Copyright (C) 2006,2007 AMD
9 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
10 * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
11 * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 #include <console/console.h>
29 #include <device/device.h>
30 #include <device/pci.h>
31 #include <device/pnp.h>
32 #include <device/pci_ids.h>
33 #include <device/pci_ops.h>
34 #include <pc80/mc146818rtc.h>
35 #include <pc80/isa-dma.h>
38 #include <arch/ioapic.h>
39 #include <cpu/x86/lapic.h>
42 #include <pc80/keyboard.h>
47 #define PREVIOUS_POWER_STATE 0x7A
49 #define MAINBOARD_POWER_OFF 0
50 #define MAINBOARD_POWER_ON 1
51 #define SLOW_CPU_OFF 0
52 #define SLOW_CPU__ON 1
54 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
55 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
60 static void lpc_common_init(device_t dev)
65 /* IO APIC initialization */
66 byte = pci_read_config8(dev, 0x74);
67 byte |= (1<<0); // enable APIC
68 pci_write_config8(dev, 0x74, byte);
69 ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
71 setup_ioapic(ioapic_base, 0); // Don't rename IO APIC ID
75 static void lpc_slave_init(device_t dev)
81 static void lpc_usb_legacy_init(device_t dev)
85 acpi_base = (pci_read_config8(dev,0x75) << 8);
87 outb(inb(acpi_base + 0xbb) |0x80, acpi_base + 0xbb);
88 outb(inb(acpi_base + 0xba) |0x80, acpi_base + 0xba);
91 static void lpc_init(device_t dev)
98 printk(BIOS_DEBUG, "LPC_INIT -------->\n");
101 lpc_usb_legacy_init(dev);
102 lpc_common_init(dev);
104 /* power after power fail */
107 on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
108 get_option(&on, "power_on_after_fail");
109 byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
114 pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
115 printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
117 /* Throttle the CPU speed down for testing */
119 get_option(&on, "slow_cpu");
123 pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
124 outl(((on<<1)+0x10) ,(pm10_bar + 0x10));
125 dword = inl(pm10_bar + 0x10);
127 printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
128 (on*12)+(on>>1),(on&1)*5);
131 /* Enable Error reporting */
132 /* Set up sync flood detected */
133 byte = pci_read_config8(dev, 0x47);
135 pci_write_config8(dev, 0x47, byte);
137 /* Set up NMI on errors */
138 byte = inb(0x70); // RTC70
140 nmi_option = NMI_OFF;
141 get_option(&nmi_option, "nmi");
143 byte &= ~(1 << 7); /* set NMI */
145 byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
147 if( byte != byte_old) {
151 /* Initialize the real time clock */
154 /* Initialize isa dma */
157 printk(BIOS_DEBUG, "LPC_INIT <--------\n");
160 static void sis966_lpc_read_resources(device_t dev)
162 struct resource *res;
164 /* Get the normal pci resources of this device */
165 pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP
167 /* Add an extra subtractive resource for both memory and I/O. */
168 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
171 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
172 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
174 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
175 res->base = 0xff800000;
176 res->size = 0x00800000; /* 8 MB for flash */
177 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
178 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
180 res = new_resource(dev, 3); /* IOAPIC */
181 res->base = 0xfec00000;
182 res->size = 0x00001000;
183 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
187 * @brief Enable resources for children devices
189 * @param dev the device whos children's resources are to be enabled
192 static void sis966_lpc_enable_childrens_resources(device_t dev)
195 uint32_t reg, reg_var[4];
199 reg = pci_read_config32(dev, 0xa0);
201 for (link = dev->link_list; link; link = link->next) {
203 for (child = link->children; child; child = child->sibling) {
204 if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
205 struct resource *res;
206 for(res = child->resource_list; res; res = res->next) {
207 unsigned long base, end; // don't need long long
208 if(!(res->flags & IORESOURCE_IO)) continue;
210 end = resource_end(res);
211 printk(BIOS_DEBUG, "sis966 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
214 reg |= (1<<0); break;
216 reg |= (1<<1); break;
217 case 0x378: // Parallal 1
218 reg |= (1<<24); break;
220 reg |= (1<<20); break;
221 case 0x220: // Aduio 0
222 reg |= (1<<8); break;
223 case 0x300: // Midi 0
224 reg |= (1<<12); break;
226 if( (base == 0x290) || (base >= 0x400)) {
227 if(var_num>=4) continue; // only 4 var ; compact them ?
228 reg |= (1<<(28+var_num));
229 reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16);
235 pci_write_config32(dev, 0xa0, reg);
236 for(i=0;i<var_num;i++) {
237 pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
243 static void sis966_lpc_enable_resources(device_t dev)
245 pci_dev_enable_resources(dev);
246 sis966_lpc_enable_childrens_resources(dev);
249 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
251 pci_write_config32(dev, 0x40,
252 ((device & 0xffff) << 16) | (vendor & 0xffff));
255 static struct pci_operations lops_pci = {
256 .set_subsystem = lpci_set_subsystem,
259 static struct device_operations lpc_ops = {
260 .read_resources = sis966_lpc_read_resources,
261 .set_resources = pci_dev_set_resources,
262 .enable_resources = sis966_lpc_enable_resources,
264 .scan_bus = scan_static_bus,
265 // .enable = sis966_enable,
266 .ops_pci = &lops_pci,
269 static const struct pci_driver lpc_driver __pci_driver = {
271 .vendor = PCI_VENDOR_ID_SIS,
272 .device = PCI_DEVICE_ID_SIS_SIS966_LPC,
275 #ifdef SLAVE_INIT // No device?
276 static struct device_operations lpc_slave_ops = {
277 .read_resources = sis966_lpc_read_resources,
278 .set_resources = pci_dev_set_resources,
279 .enable_resources = pci_dev_enable_resources,
280 .init = lpc_slave_init,
281 // .enable = sis966_enable,
282 .ops_pci = &lops_pci,