2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <arch/smp/mpspec.h>
22 #include <arch/ioapic.h>
23 #include <device/pci.h>
26 #if CONFIG_LOGICAL_CPUS==1
27 #include <cpu/amd/multicore.h>
30 #include <cpu/amd/amdfam10_sysconf.h>
31 #include "mb_sysconf.h"
35 static void *smp_write_config_table(void *v)
37 static const char sig[4] = "PCMP";
38 static const char oem[8] = "COREBOOT";
39 static const char productid[12] = "SERENGETI ";
40 struct mp_config_table *mc;
44 struct mb_sysconf_t *m;
46 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
47 memset(mc, 0, sizeof(*mc));
49 memcpy(mc->mpc_signature, sig, sizeof(sig));
50 mc->mpc_length = sizeof(*mc); /* initially just the header */
52 mc->mpc_checksum = 0; /* not yet computed */
53 memcpy(mc->mpc_oem, oem, sizeof(oem));
54 memcpy(mc->mpc_productid, productid, sizeof(productid));
57 mc->mpc_entry_count = 0; /* No entries yet... */
58 mc->mpc_lapic = LAPIC_ADDR;
63 smp_write_processors(mc);
70 /* define bus and isa numbers */
71 for(j= 0; j < 256 ; j++) {
73 smp_write_bus(mc, j, "PCI ");
75 smp_write_bus(mc, m->bus_isa, "ISA ");
77 /*I/O APICs: APIC ID Version State Address*/
78 smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
82 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
84 res = find_resource(dev, PCI_BASE_ADDRESS_0);
86 smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
89 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
91 res = find_resource(dev, PCI_BASE_ADDRESS_0);
93 smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
99 for(i=1; i< sysconf.hc_possible_num; i++) {
100 if(!(sysconf.pci1234[i] & 0x1) ) continue;
102 switch(sysconf.hcid[i]) {
105 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
107 res = find_resource(dev, PCI_BASE_ADDRESS_0);
109 smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
112 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
114 res = find_resource(dev, PCI_BASE_ADDRESS_0);
116 smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
126 mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_8111, 0);
128 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
130 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
133 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
137 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
143 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
147 // Slot 1 PCI-X 133/100/66
149 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); //
153 //Slot 2 PCI-X 133/100/66
155 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
160 for(i=1; i< sysconf.hc_possible_num; i++) {
161 if(!(sysconf.pci1234[i] & 0x1) ) continue;
165 struct resource *res;
166 switch(sysconf.hcid[i]) {
169 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
171 res = find_resource(dev, PCI_BASE_ADDRESS_0);
173 for(jj=0; jj<4; jj++) {
174 //Slot 1 PCI-X 133/100/66
175 for(ii=0;ii<4;ii++) {
176 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj<<2)|ii, m->apicid_8132a[j][0], (jj+ii)%4); //
182 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
184 res = find_resource(dev, PCI_BASE_ADDRESS_0);
186 for(jj=0; jj<4; jj++) {
187 //Slot 2 PCI-X 133/100/66
188 for(ii=0;ii<4;ii++) {
189 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj<<2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); //25
199 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
208 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
209 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
210 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
211 /* There is no extension information... */
213 /* Compute the checksums */
214 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
215 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
216 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
217 mc, smp_next_mpe_entry(mc));
218 return smp_next_mpe_entry(mc);
221 unsigned long write_smp_table(unsigned long addr)
224 v = smp_write_floating_table(addr);
225 return (unsigned long)smp_write_config_table(v);