src/mainboard/supermicro/x6dhe_g2/mptable.c

   1 #include <console/console.h>
   2 #include <arch/smp/mpspec.h>
   3 #include <arch/ioapic.h>
   4 #include <device/pci.h>
   5 #include <string.h>
   6 #include <stdint.h>
   7
   8 static void *smp_write_config_table(void *v)
   9 {
  10         static const char sig[4] = "PCMP";
  11         static const char oem[8] = "COREBOOT";
  12         static const char productid[12] = "X6DHE       ";
  13         struct mp_config_table *mc;
  14         unsigned char bus_num;
  15         unsigned char bus_isa;
  16         unsigned char bus_pxhd_1;
  17         unsigned char bus_pxhd_2;
  18         unsigned char bus_esb6300_1;
  19         unsigned char bus_esb6300_2;
  20
  21         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  22         memset(mc, 0, sizeof(*mc));
  23
  24         memcpy(mc->mpc_signature, sig, sizeof(sig));
  25         mc->mpc_length = sizeof(*mc); /* initially just the header */
  26         mc->mpc_spec = 0x04;
  27         mc->mpc_checksum = 0; /* not yet computed */
  28         memcpy(mc->mpc_oem, oem, sizeof(oem));
  29         memcpy(mc->mpc_productid, productid, sizeof(productid));
  30         mc->mpc_oemptr = 0;
  31         mc->mpc_oemsize = 0;
  32         mc->mpc_entry_count = 0; /* No entries yet... */
  33         mc->mpc_lapic = LAPIC_ADDR;
  34         mc->mpe_length = 0;
  35         mc->mpe_checksum = 0;
  36         mc->reserved = 0;
  37
  38         smp_write_processors(mc);
  39
  40         {
  41                 device_t dev;
  42
  43                 /* esb6300_2 */
  44                 dev = dev_find_slot(0, PCI_DEVFN(0x1c,0));
  45                 if (dev) {
  46                         bus_esb6300_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  47                 } else {
  48                         printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1c.0, using defaults\n");
  49                         bus_esb6300_1 = 6;
  50                 }
  51                 /* esb6300_1 */
  52                 dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
  53                 if (dev) {
  54                         bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  55                         bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
  56                         bus_isa++;
  57                 } else {
  58                         printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
  59                         bus_esb6300_2 = 7;
  60                         bus_isa = 8;
  61                 }
  62                 /* pxhd-1 */
  63                 dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
  64                 if (dev) {
  65                         bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  66                 } else {
  67                         printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
  68                         bus_pxhd_1 = 2;
  69                 }
  70                 /* pxhd-2 */
  71                 dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
  72                 if (dev) {
  73                         bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  74                 } else {
  75                         printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
  76                         bus_pxhd_2 = 3;
  77                 }
  78         }
  79
  80         /* define bus and isa numbers */
  81         for(bus_num = 0; bus_num < bus_isa; bus_num++) {
  82                 smp_write_bus(mc, bus_num, "PCI   ");
  83         }
  84         smp_write_bus(mc, bus_isa, "ISA   ");
  85
  86         /* IOAPIC handling */
  87
  88         smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
  89         smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000);
  90         {
  91                 struct resource *res;
  92                 device_t dev;
  93                 /* PXHd apic 4 */
  94                 dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
  95                 if (dev) {
  96                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  97                         if (res) {
  98                                 smp_write_ioapic(mc, 0x04, 0x20, res->base);
  99                         }
 100                 } else {
 101                         printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
 102                         printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
 103                 }
 104                 /* PXHd apic 5 */
 105                 dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
 106                 if (dev) {
 107                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
 108                         if (res) {
 109                                 smp_write_ioapic(mc, 0x05, 0x20, res->base);
 110                         }
 111                 } else {
 112                         printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
 113                         printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
 114                 }
 115         }
 116
 117         mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
 118
 119         /* ISA backward compatibility interrupts  */
 120         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 121                 0x00, 0x74, 0x02, 0x10);
 122         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 123                 0x00, 0x77, 0x02, 0x17);
 124         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 125                 0x00, 0x75, 0x02, 0x13);
 126         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 127                 0x00, 0x7c, 0x02, 0x12);
 128         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 129                 0x00, 0x7d, 0x02, 0x11);
 130         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 131                 0x03, 0x08, 0x05, 0x00);
 132         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 133                 0x03, 0x08, 0x05, 0x04);
 134         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 135                 bus_esb6300_1, 0x04, 0x03, 0x00);
 136         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 137                 bus_esb6300_1, 0x08, 0x03, 0x01);
 138         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 139                 bus_esb6300_2, 0x04, 0x02, 0x10);
 140         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 141                 bus_esb6300_2, 0x08, 0x02, 0x14);
 142
 143         /* Standard local interrupt assignments */
 144         smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 145                 bus_isa, 0x00, MP_APIC_ALL, 0x00);
 146         smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 147                 bus_isa, 0x00, MP_APIC_ALL, 0x01);
 148
 149         /* FIXME verify I have the irqs handled for all of the risers */
 150
 151         /* Compute the checksums */
 152         mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 153
 154         mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 155         printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 156                 mc, smp_next_mpe_entry(mc));
 157         return smp_next_mpe_entry(mc);
 158 }
 159
 160 unsigned long write_smp_table(unsigned long addr)
 161 {
 162         void *v;
 163         v = smp_write_floating_table(addr);
 164         return (unsigned long)smp_write_config_table(v);
 165 }
 166