2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
23 #include <device/device.h>
24 #include <device/pci.h>
25 #include <device/pci_ops.h>
26 #include <device/pci_ids.h>
28 #include <pc80/mc146818rtc.h>
29 #include <pc80/i8259.h>
30 #include <pc80/keyboard.h>
31 #include <pc80/isa-dma.h>
33 #include <cpu/x86/lapic.h>
34 #include <arch/ioapic.h>
37 #define ACPI_IO_BASE 0x400
38 #define HPET_ADDR 0xfe800000UL
40 static const unsigned char pci_irqs[4] = { 11, 11, 10, 10 };
42 static const unsigned char usb_pins[4] = { 'A', 'B', 'C', 'D' };
43 static const unsigned char vga_pins[4] = { 'A', 'B', 'C', 'D' };
44 static const unsigned char slot_pins[4] = { 'B', 'C', 'D', 'A' };
45 static const unsigned char ac97_pins[4] = { 'B', 'C', 'D', 'A' };
47 static unsigned char *pin_to_irq(const unsigned char *pin)
49 static unsigned char irqs[4];
51 for (i = 0; i < 4; i++)
52 irqs[i] = pci_irqs[pin[i] - 'A'];
57 static void pci_routing_fixup(struct device *dev)
59 printk(BIOS_DEBUG, "%s: device is %p\n", __FUNCTION__, dev);
61 /* set up PCI IRQ routing */
62 pci_write_config8(dev, 0x55, pci_irqs[0] << 4);
63 pci_write_config8(dev, 0x56, pci_irqs[1] | (pci_irqs[2] << 4));
64 pci_write_config8(dev, 0x57, pci_irqs[3] << 4);
67 printk(BIOS_DEBUG, "Setting up USB interrupts.\n");
68 pci_assign_irqs(0, 0x10, pin_to_irq(usb_pins));
70 printk(BIOS_DEBUG, "Setting up VGA interrupts.\n");
71 pci_assign_irqs(1, 0x00, pin_to_irq(vga_pins));
73 printk(BIOS_DEBUG, "Setting up PCI slot interrupts.\n");
74 pci_assign_irqs(2, 0x04, pin_to_irq(slot_pins));
77 printk(BIOS_DEBUG, "Setting up AC97 interrupts.\n");
78 pci_assign_irqs(0x80, 0x1, pin_to_irq(ac97_pins));
82 * Set up the power management capabilities directly into ACPI mode. This
83 * avoids having to handle any System Management Interrupts (SMI's) which I
84 * can't figure out how to do !!!!
87 static void setup_pm(device_t dev)
89 /* Debounce LID and PWRBTN# Inputs for 16ms. */
90 pci_write_config8(dev, 0x80, 0x20);
92 /* Set ACPI base address to IO ACPI_IO_BASE */
93 pci_write_config16(dev, 0x88, ACPI_IO_BASE | 1);
95 /* set ACPI irq to 9 */
96 pci_write_config8(dev, 0x82, 0x49);
98 /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
99 pci_write_config16(dev, 0x84, 0x609a);
101 /* SMI output level to low, 7.5us throttle clock */
102 pci_write_config8(dev, 0x8d, 0x18);
104 /* GP Timer Control 1s */
105 pci_write_config8(dev, 0x93, 0x88);
108 pci_write_config8(dev, 0x94, 0x20); // 0x20??
110 /* 7 = stp to sust delay 1msec
111 * 6 = SUSST# Deasserted Before PWRGD for STD
113 pci_write_config8(dev, 0x95, 0xc0); // 0xc1??
115 /* Disable GP2 & GP3 Timer */
116 pci_write_config8(dev, 0x98, 0);
118 /* GP2 Timer Counter */
119 pci_write_config8(dev, 0x99, 0xfb);
120 /* GP3 Timer Counter */
121 //pci_write_config8(dev, 0x9a, 0x20);
123 /* Multi Function Select 1 */
124 pci_write_config8(dev, 0xe4, 0x00);
126 /* Multi Function Select 2 */
127 pci_write_config8(dev, 0xe5, 0x41); //??
129 /* Enable ACPI access (and setup like award) */
130 pci_write_config8(dev, 0x81, 0x84);
132 /* Clear status events. */
133 outw(0xffff, ACPI_IO_BASE + 0x00);
134 outw(0xffff, ACPI_IO_BASE + 0x20);
135 outw(0xffff, ACPI_IO_BASE + 0x28);
136 outl(0xffffffff, ACPI_IO_BASE + 0x30);
138 /* Disable SCI on GPIO. */
139 outw(0x0, ACPI_IO_BASE + 0x22);
141 /* Disable SMI on GPIO. */
142 outw(0x0, ACPI_IO_BASE + 0x24);
144 /* Disable all global enable SMIs. */
145 outw(0x0, ACPI_IO_BASE + 0x2a);
147 /* All SMI off, both IDE buses ON, PSON rising edge. */
148 outw(0x0, ACPI_IO_BASE + 0x2c);
150 /* Primary activity SMI disable. */
151 outl(0x0, ACPI_IO_BASE + 0x34);
153 /* GP timer reload on none. */
154 outl(0x0, ACPI_IO_BASE + 0x38);
156 /* Disable extended IO traps. */
157 outb(0x0, ACPI_IO_BASE + 0x42);
159 /* SCI is generated for RTC/pwrBtn/slpBtn. */
160 outw(0x0001, ACPI_IO_BASE + 0x04);
162 /* Allow SLP# signal to assert LDTSTOP_L.
163 * Will work for C3 and for FID/VID change.
165 outb(0x1, ACPI_IO_BASE + 0x11);
168 static void cx700_set_lpc_registers(struct device *dev)
170 unsigned char enables;
172 printk(BIOS_DEBUG, "VIA CX700 LPC bridge init\n");
174 // enable the internal I/O decode
175 enables = pci_read_config8(dev, 0x6C);
177 pci_write_config8(dev, 0x6C, enables);
179 // Map 4MB of FLASH into the address space
180 // pci_write_config8(dev, 0x41, 0x7f);
182 // Set bit 6 of 0x40, because Award does it (IO recovery time)
183 // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
184 // interrupts can be properly marked as level triggered.
185 enables = pci_read_config8(dev, 0x40);
187 pci_write_config8(dev, 0x40, enables);
189 /* DMA Line buffer control */
190 enables = pci_read_config8(dev, 0x42);
192 pci_write_config8(dev, 0x42, enables);
194 /* I/O recovery time */
195 pci_write_config8(dev, 0x4c, 0x44);
197 /* ROM memory cycles go to LPC. */
198 pci_write_config8(dev, 0x59, 0x80);
200 /* Enable SM dynamic clock gating */
201 pci_write_config8(dev, 0x5b, 0x01);
203 /* Set Read Pass Write Control Enable */
204 pci_write_config8(dev, 0x48, 0x0c);
206 /* Set SM Misc Control: Enable Internal APIC . */
207 enables = pci_read_config8(dev, 0x58);
209 pci_write_config8(dev, 0x58, enables);
210 enables = pci_read_config8(dev, 0x4d);
212 pci_write_config8(dev, 0x4d, enables);
214 /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
215 enables = pci_read_config8(dev, 0x4f);
217 pci_write_config8(dev, 0x4f, enables);
219 /* enable KBC configuration */
220 pci_write_config8(dev, 0x51, 0x1f);
222 /* enable serial irq */
223 pci_write_config8(dev, 0x52, 0x9);
226 pci_write_config8(dev, 0x53, 0x00);
228 // Power management setup
231 /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
232 pci_write_config8(dev, 0x40, 0x54);
234 /* Enable HPET timer */
235 pci_write_config32(dev, 0x68, (1 << 31) | (HPET_ADDR >> 8));
239 static void cx700_read_resources(device_t dev)
241 struct resource *res;
243 /* Make sure we call our childrens set/enable functions - these
244 * are not called unless this device has a resource to set.
247 pci_dev_read_resources(dev);
249 res = new_resource(dev, 1);
252 res->limit = 0xffffUL;
253 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
255 res = new_resource(dev, 3); /* IOAPIC */
256 res->base = 0xfec00000;
257 res->size = 0x00001000;
258 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
261 static void cx700_set_resources(device_t dev)
263 struct resource *resource;
264 resource = find_resource(dev, 1);
265 resource->flags |= IORESOURCE_STORED;
266 pci_dev_set_resources(dev);
269 static void cx700_enable_resources(device_t dev)
271 /* Enable SuperIO decoding */
272 pci_dev_enable_resources(dev);
275 static void cx700_lpc_init(struct device *dev)
277 cx700_set_lpc_registers(dev);
281 setup_ioapic(IO_APIC_ADDR, IO_APIC_ID);
284 /* Initialize interrupts */
285 pci_routing_fixup(dev);
286 /* make sure interupt controller is configured before keyboard init */
289 /* Start the Real Time Clock */
292 /* Initialize isa dma */
295 /* Initialize keyboard controller */
299 static struct device_operations cx700_lpc_ops = {
300 .read_resources = cx700_read_resources,
301 .set_resources = cx700_set_resources,
302 .enable_resources = cx700_enable_resources,
303 .init = &cx700_lpc_init,
304 .scan_bus = scan_static_bus,
307 static const struct pci_driver lpc_driver __pci_driver = {
308 .ops = &cx700_lpc_ops,
309 .vendor = PCI_VENDOR_ID_VIA,