Reduce duplicate definition in CAR code.

Macros for the register addresses for the MTRR MSRs are already defined
in include/cpu/x86/car.h. This patch uses those macros instead of
creating a second instance of that same data.

I also added a few macros to the amd mtrr.h to make the MSR naming more
consistent.

Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5942 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 53182726f184d92ff88611a47dceb588efb6d22e..5a19a0c0b0f9cc3a3dfd493c9c4bd3cd7c4f620a 100644 (file)
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -155,7 +155,7 @@ enable_fixed_mtrr_dram_modify:
 
        /* Clear all MTRRs. */
        xorl    %edx, %edx
-       movl    $fixed_mtrr_msr, %esi
+       movl    $all_mtrr_msrs, %esi
 
 clear_fixed_var_mtrr:
        lodsl   (%esi), %eax
@@ -396,23 +396,48 @@ CAR_FAM10_ap_out:
 
        post_code(0xaf)         /* Should never see this POST code. */
 
-fixed_mtrr_msr:
-       .long   0x250, 0x258, 0x259
-       .long   0x268, 0x269, 0x26A
-       .long   0x26B, 0x26C, 0x26D
-       .long   0x26E, 0x26F
+all_mtrr_msrs:
+       /* fixed MTRR MSRs */
+       .long   MTRRfix64K_00000_MSR
+       .long   MTRRfix16K_80000_MSR
+       .long   MTRRfix16K_A0000_MSR
+       .long   MTRRfix4K_C0000_MSR
+       .long   MTRRfix4K_C8000_MSR
+       .long   MTRRfix4K_D0000_MSR
+       .long   MTRRfix4K_D8000_MSR
+       .long   MTRRfix4K_E0000_MSR
+       .long   MTRRfix4K_E8000_MSR
+       .long   MTRRfix4K_F0000_MSR
+       .long   MTRRfix4K_F8000_MSR
+
+       /* var MTRR MSRs */
+       .long   MTRRphysBase_MSR(0)
+       .long   MTRRphysMask_MSR(0)
+       .long   MTRRphysBase_MSR(1)
+       .long   MTRRphysMask_MSR(1)
+       .long   MTRRphysBase_MSR(2)
+       .long   MTRRphysMask_MSR(2)
+       .long   MTRRphysBase_MSR(3)
+       .long   MTRRphysMask_MSR(3)
+       .long   MTRRphysBase_MSR(4)
+       .long   MTRRphysMask_MSR(4)
+       .long   MTRRphysBase_MSR(5)
+       .long   MTRRphysMask_MSR(5)
+       .long   MTRRphysBase_MSR(6)
+       .long   MTRRphysMask_MSR(6)
+       .long   MTRRphysBase_MSR(7)
+       .long   MTRRphysMask_MSR(7)
+
+       /* Variable IORR MTRR MSRs */
+       .long   IORRBase_MSR(0)
+       .long   IORRMask_MSR(0)
+       .long   IORRBase_MSR(1)
+       .long   IORRMask_MSR(1)
+
+       /* Top of memory MTRR MSRs */
+       .long   TOP_MEM_MSR
+       .long   TOP_MEM2_MSR
 
-var_mtrr_msr:
-       .long   0x200, 0x201, 0x202, 0x203
-       .long   0x204, 0x205, 0x206, 0x207
-       .long   0x208, 0x209, 0x20A, 0x20B
-       .long   0x20C, 0x20D, 0x20E, 0x20F
-
-var_iorr_msr:
-       .long   0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019
-
-mem_top:
-       .long   0xC001001A, 0xC001001D
        .long   0x000 /* NULL, end of table */
 
 cache_as_ram_setup_out:

diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index d8465f4b2f1b9307f2d4e802b147cf383f673fff..e228f4c4a07004125f2bc88b7c49dda0d5c54345 100644 (file)
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -115,7 +115,7 @@ NotHtProcessor:
 
        /* Clear all MTRRs. */
        xorl    %edx, %edx
-       movl    $fixed_mtrr_msr, %esi
+       movl    $all_mtrr_msrs, %esi
 
 clear_fixed_var_mtrr:
        lodsl   (%esi), %eax
@@ -128,17 +128,38 @@ clear_fixed_var_mtrr:
 
        jmp     clear_fixed_var_mtrr
 
-fixed_mtrr_msr:
-       .long   0x250, 0x258, 0x259
-       .long   0x268, 0x269, 0x26A
-       .long   0x26B, 0x26C, 0x26D
-       .long   0x26E, 0x26F
-
-var_mtrr_msr:
-       .long   0x200, 0x201, 0x202, 0x203
-       .long   0x204, 0x205, 0x206, 0x207
-       .long   0x208, 0x209, 0x20A, 0x20B
-       .long   0x20C, 0x20D, 0x20E, 0x20F
+all_mtrr_msrs:
+       /* fixed MTRR MSRs */
+       .long   MTRRfix64K_00000_MSR
+       .long   MTRRfix16K_80000_MSR
+       .long   MTRRfix16K_A0000_MSR
+       .long   MTRRfix4K_C0000_MSR
+       .long   MTRRfix4K_C8000_MSR
+       .long   MTRRfix4K_D0000_MSR
+       .long   MTRRfix4K_D8000_MSR
+       .long   MTRRfix4K_E0000_MSR
+       .long   MTRRfix4K_E8000_MSR
+       .long   MTRRfix4K_F0000_MSR
+       .long   MTRRfix4K_F8000_MSR
+
+       /* var MTRR MSRs */
+       .long   MTRRphysBase_MSR(0)
+       .long   MTRRphysMask_MSR(0)
+       .long   MTRRphysBase_MSR(1)
+       .long   MTRRphysMask_MSR(1)
+       .long   MTRRphysBase_MSR(2)
+       .long   MTRRphysMask_MSR(2)
+       .long   MTRRphysBase_MSR(3)
+       .long   MTRRphysMask_MSR(3)
+       .long   MTRRphysBase_MSR(4)
+       .long   MTRRphysMask_MSR(4)
+       .long   MTRRphysBase_MSR(5)
+       .long   MTRRphysMask_MSR(5)
+       .long   MTRRphysBase_MSR(6)
+       .long   MTRRphysMask_MSR(6)
+       .long   MTRRphysBase_MSR(7)
+       .long   MTRRphysMask_MSR(7)
+
        .long   0x000 /* NULL, end of table */
 
 clear_fixed_var_mtrr_out:

diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index d6df4a90e98de391a432f74f449ab55c909b1696..1f0bed2032cbe09a46aeb944f9010cd64e18fe31 100644 (file)
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -47,7 +47,7 @@ CacheAsRam:
 
        /* Clear all MTRRs. */
        xorl    %edx, %edx
-       movl    $fixed_mtrr_msr, %esi
+       movl    $all_mtrr_msrs, %esi
 
 clear_fixed_var_mtrr:
        lodsl   (%esi), %eax
@@ -60,17 +60,38 @@ clear_fixed_var_mtrr:
 
        jmp     clear_fixed_var_mtrr
 
-fixed_mtrr_msr:
-       .long   0x250, 0x258, 0x259
-       .long   0x268, 0x269, 0x26A
-       .long   0x26B, 0x26C, 0x26D
-       .long   0x26E, 0x26F
-
-var_mtrr_msr:
-       .long   0x200, 0x201, 0x202, 0x203
-       .long   0x204, 0x205, 0x206, 0x207
-       .long   0x208, 0x209, 0x20A, 0x20B
-       .long   0x20C, 0x20D, 0x20E, 0x20F
+all_mtrr_msrs:
+       /* fixed MTRR MSRs */
+       .long   MTRRfix64K_00000_MSR
+       .long   MTRRfix16K_80000_MSR
+       .long   MTRRfix16K_A0000_MSR
+       .long   MTRRfix4K_C0000_MSR
+       .long   MTRRfix4K_C8000_MSR
+       .long   MTRRfix4K_D0000_MSR
+       .long   MTRRfix4K_D8000_MSR
+       .long   MTRRfix4K_E0000_MSR
+       .long   MTRRfix4K_E8000_MSR
+       .long   MTRRfix4K_F0000_MSR
+       .long   MTRRfix4K_F8000_MSR
+
+       /* var MTRR MSRs */
+       .long   MTRRphysBase_MSR(0)
+       .long   MTRRphysMask_MSR(0)
+       .long   MTRRphysBase_MSR(1)
+       .long   MTRRphysMask_MSR(1)
+       .long   MTRRphysBase_MSR(2)
+       .long   MTRRphysMask_MSR(2)
+       .long   MTRRphysBase_MSR(3)
+       .long   MTRRphysMask_MSR(3)
+       .long   MTRRphysBase_MSR(4)
+       .long   MTRRphysMask_MSR(4)
+       .long   MTRRphysBase_MSR(5)
+       .long   MTRRphysMask_MSR(5)
+       .long   MTRRphysBase_MSR(6)
+       .long   MTRRphysMask_MSR(6)
+       .long   MTRRphysBase_MSR(7)
+       .long   MTRRphysMask_MSR(7)
+
        .long   0x000 /* NULL, end of table */
 
 clear_fixed_var_mtrr_out:

diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h
index c7b3fcae7d33b4352e00405c11c1482154df5d15..e866fb95116cadb38dc9669a77edb9db3dd37ae8 100644 (file)
--- a/src/include/cpu/amd/mtrr.h
+++ b/src/include/cpu/amd/mtrr.h
@@ -21,12 +21,13 @@
 #define SYSCFG_MSR_SysVicLimitMask     ((1 << 8) - (1 << 5))
 #define SYSCFG_MSR_SysAckLimitMask     ((1 << 5) - (1 << 0))
 
-#define IORR0_BASE                     0xC0010016
-#define IORR0_MASK                     0xC0010017
-#define IORR1_BASE                     0xC0010018
-#define IORR1_MASK                     0xC0010019
-#define TOP_MEM                                0xC001001A
-#define TOP_MEM2                       0xC001001D
+#define IORRBase_MSR(reg) (0xC0010016 + 2 * (reg))
+#define IORRMask_MSR(reg) (0xC0010016 + 2 * (reg) + 1)
+
+#define TOP_MEM_MSR                    0xC001001A
+#define TOP_MEM2_MSR                   0xC001001D
+#define TOP_MEM                                TOP_MEM_MSR
+#define TOP_MEM2                       TOP_MEM2_MSR
 
 #define TOP_MEM_MASK                   0x007fffff
 #define TOP_MEM_MASK_KB                        (TOP_MEM_MASK >> 10)