2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Arastra, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 /* This code is based on src/mainboard/intel/jarrell/mptable.c */
23 #include <console/console.h>
24 #include <arch/smp/mpspec.h>
25 #include <arch/ioapic.h>
26 #include <device/pci.h>
30 static void *smp_write_config_table(void *v)
32 static const char sig[4] = "PCMP";
33 static const char oem[8] = "COREBOOT";
34 static const char productid[12] = "Mt. Arvon ";
35 struct mp_config_table *mc;
40 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
41 memset(mc, 0, sizeof(*mc));
43 memcpy(mc->mpc_signature, sig, sizeof(sig));
44 mc->mpc_length = sizeof(*mc); /* initially just the header */
46 mc->mpc_checksum = 0; /* not yet computed */
47 memcpy(mc->mpc_oem, oem, sizeof(oem));
48 memcpy(mc->mpc_productid, productid, sizeof(productid));
51 mc->mpc_entry_count = 0; /* No entries yet... */
52 mc->mpc_lapic = LAPIC_ADDR;
57 smp_write_processors(mc);
59 /* Define bus numbers */
60 smp_write_bus(mc, 0, "PCI ");
61 smp_write_bus(mc, bus_pci, "PCI ");
62 smp_write_bus(mc, bus_pcie_a, "PCI ");
63 smp_write_bus(mc, bus_isa, "ISA ");
66 smp_write_ioapic(mc, 0x01, 0x20, IO_APIC_ADDR);
68 mptable_add_isa_interrupts(mc, bus_isa, 0x1, 0);
70 /* Standard local interrupt assignments */
71 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
72 bus_isa, 0x00, MP_APIC_ALL, 0x00);
73 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
74 bus_isa, 0x00, MP_APIC_ALL, 0x01);
76 /* Internal PCI devices */
77 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
78 0, (0x01<<2)|0, 0x01, 0x10); /* DMA controller */
79 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
80 0, (0x02<<2)|0, 0x01, 0x10); /* PCIe port A */
81 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
82 0, (0x03<<2)|0, 0x01, 0x10); /* PCIe port A1 */
83 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
84 0, (0x1c<<2)|0, 0x01, 0x10); /* PCIe port B0 */
85 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
86 0, (0x1c<<2)|1, 0x01, 0x11); /* PCIe port B1 */
87 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
88 0, (0x1c<<2)|2, 0x01, 0x12); /* PCIe port B2 */
89 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
90 0, (0x1c<<2)|3, 0x01, 0x13); /* PCIe port B3 */
91 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
92 0, (0x1d<<2)|0, 0x01, 0x10); /* UHCI0/EHCI */
93 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
94 0, (0x1d<<2)|1, 0x01, 0x11); /* UHCI1 */
95 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
96 0, (0x1e<<2)|0, 0x01, 0x10); /* Audio */
97 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
98 0, (0x1e<<2)|1, 0x01, 0x11); /* Modem */
99 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
100 0, (0x1f<<2)|1, 0x01, 0x11); /* SATA/SMBus */
101 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
102 0, (0x1f<<2)|3, 0x01, 0x13); /* ? */
105 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
106 bus_pci, 0x00, 0x01, 0x10);
107 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
108 bus_pci, 0x01, 0x01, 0x11);
109 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
110 bus_pci, 0x02, 0x01, 0x12);
111 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
112 bus_pci, 0x03, 0x01, 0x13);
114 /* PCIe port A slot */
115 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
116 bus_pcie_a, 0x00, 0x01, 0x10);
117 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
118 bus_pcie_a, 0x01, 0x01, 0x11);
119 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
120 bus_pcie_a, 0x02, 0x01, 0x12);
121 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
122 bus_pcie_a, 0x03, 0x01, 0x13);
124 /* There is no extension information... */
126 /* Compute the checksums */
127 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
129 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
130 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
131 mc, smp_next_mpe_entry(mc));
132 return smp_next_mpe_entry(mc);
135 unsigned long write_smp_table(unsigned long addr)
138 v = smp_write_floating_table(addr);
139 return (unsigned long)smp_write_config_table(v);