2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Arastra, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <arch/smp/mpspec.h>
23 #include <arch/ioapic.h>
24 #include <device/pci.h>
28 static void *smp_write_config_table(void *v)
30 static const char sig[4] = "PCMP";
31 static const char oem[8] = "COREBOOT";
32 static const char productid[12] = "Truxton ";
33 struct mp_config_table *mc;
41 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
42 memset(mc, 0, sizeof(*mc));
44 memcpy(mc->mpc_signature, sig, sizeof(sig));
45 mc->mpc_length = sizeof(*mc); /* initially just the header */
47 mc->mpc_checksum = 0; /* not yet computed */
48 memcpy(mc->mpc_oem, oem, sizeof(oem));
49 memcpy(mc->mpc_productid, productid, sizeof(productid));
52 mc->mpc_entry_count = 0; /* No entries yet... */
53 mc->mpc_lapic = LAPIC_ADDR;
58 smp_write_processors(mc);
62 dev = dev_find_slot(0, PCI_DEVFN(0x04,0));
64 bus_aioc = pci_read_config8(dev, PCI_SECONDARY_BUS);
65 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
69 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0\n");
74 dev = dev_find_slot(0, PCI_DEVFN(0x02,0));
76 bus_pea0 = pci_read_config8(dev, PCI_SECONDARY_BUS);
79 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:02.0\n");
83 dev = dev_find_slot(0, PCI_DEVFN(0x03,0));
85 bus_pea1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
88 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:03.0\n");
92 /* define bus and isa numbers */
93 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
94 smp_write_bus(mc, bus_num, "PCI ");
96 smp_write_bus(mc, bus_isa, "ISA ");
99 smp_write_ioapic(mc, 0x8, 0x20, IO_APIC_ADDR);
101 mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
103 /* Standard local interrupt assignments */
104 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
105 bus_isa, 0x00, MP_APIC_ALL, 0x00);
106 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
107 bus_isa, 0x00, MP_APIC_ALL, 0x01);
109 /* IMCH/IICH PCI devices */
110 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
111 0, (0x01<<2)|0, 0x8, 0x10); /* DMA controller */
112 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
113 0, (0x02<<2)|0, 0x8, 0x10); /* PCIe port A bridge */
114 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
115 0, (0x03<<2)|0, 0x8, 0x10); /* PCIe port A1 bridge */
116 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
117 0, (0x04<<2)|0, 0x8, 0x10); /* AIOC PCI bridge */
118 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
119 0, (0x1d<<2)|0, 0x8, 0x10); /* UHCI/EHCI */
120 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
121 0, (0x1f<<2)|1, 0x8, 0x11); /* SATA/SMBus */
125 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
126 bus_pea0, (0<<2)|0, 0x8, 0x10);
127 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
128 bus_pea0, (0<<2)|1, 0x8, 0x11);
129 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
130 bus_pea0, (0<<2)|2, 0x8, 0x12);
131 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
132 bus_pea0, (0<<2)|3, 0x8, 0x13);
137 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
138 bus_pea1, (0<<2)|0, 0x8, 0x10);
139 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
140 bus_pea1, (0<<2)|1, 0x8, 0x11);
141 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
142 bus_pea1, (0<<2)|2, 0x8, 0x12);
143 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
144 bus_pea1, (0<<2)|3, 0x8, 0x13);
148 /* AIOC PCI devices */
149 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
150 bus_aioc, (0<<2)|0, 0x8, 0x10); /* GbE0 */
151 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
152 bus_aioc, (1<<2)|0, 0x8, 0x11); /* GbE1 */
153 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
154 bus_aioc, (2<<2)|0, 0x8, 0x12); /* GbE2 */
157 /* There is no extension information... */
159 /* Compute the checksums */
160 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
162 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
163 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
164 mc, smp_next_mpe_entry(mc));
165 return smp_next_mpe_entry(mc);
168 unsigned long write_smp_table(unsigned long addr)
171 v = smp_write_floating_table(addr);
172 return (unsigned long)smp_write_config_table(v);