2 * This file is part of the coreboot project.
4 * Copyright (C) 2004 Ron G. Minnich
5 * Copyright (C) 2004 Eric Biederman
6 * Copyright (C) 2008-2009 coresystems GmbH
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; version 2 of
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 /* the problem: we have 82801dbm support in fb1, and 82801er in fb2.
24 * fb1 code is what we want, fb2 structure is needed however.
25 * so we need to get fb1 code for 82801dbm into fb2 structure.
27 /* What I did: took the 80801er stuff from fb2, verify it against the
28 * db stuff in fb1, and made sure it was right.
34 #if !defined(__PRE_RAM__)
36 extern void i82801dx_enable(device_t dev);
39 #define IO_APIC_ADDR 0xfec00000
42 * HPET Memory Address Range. Possible values:
43 * 0xfed00000 for FED0_0000h - FED0_03FFh
44 * 0xfed01000 for FED0_1000h - FED0_13FFh
45 * 0xfed02000 for FED0_2000h - FED0_23FFh
46 * 0xfed03000 for FED0_3000h - FED0_33FFh
48 #define HPET_ADDR 0xfed00000
50 #define DEBUG_PERIODIC_SMIS 0
52 #define MAINBOARD_POWER_OFF 0
53 #define MAINBOARD_POWER_ON 1
54 #define MAINBOARD_POWER_KEEP 2
56 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
57 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
61 * 000 = Non-combined. P0 is primary master. P1 is secondary master.
62 * 001 = Non-combined. P0 is secondary master. P1 is primary master.
63 * 100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary;
64 * Primary IDE channel disabled.
65 * 101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary.
66 * 110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary
67 * slave; Secondary IDE channel disabled.
68 * 111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master.
70 /* PCI Configuration Space (D31:F1) */
71 #define IDE_TIM_PRI 0x40 /* IDE timings, primary */
72 #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
75 #define IDE_DECODE_ENABLE (1 << 15)
79 #define PCI_DMA_CFG 0x90
80 #define SERIRQ_CNTL 0x64
84 #define GEN_PMCON_3 0xa4
88 #define PMBASE_ADDR 0x0400
89 #define DEFAULT_PMBASE PMBASE_ADDR
90 #define ACPI_CNTL 0x44
91 #define BIOS_CNTL 0x4E
92 #define GPIO_BASE 0x58
93 #define GPIO_CNTL 0x5C
94 #define GPIOBASE_ADDR 0x0500
95 #define PIRQA_ROUT 0x60
96 #define PIRQB_ROUT 0x61
97 #define PIRQC_ROUT 0x62
98 #define PIRQD_ROUT 0x63
99 #define PIRQE_ROUT 0x68
100 #define PIRQF_ROUT 0x69
101 #define PIRQG_ROUT 0x6A
102 #define PIRQH_ROUT 0x6B
105 #define FUNC_DIS 0xF2
110 #define SBUS_NUM 0x19
111 #define SUB_BUS_NUM 0x1A
119 #define PCI_MAST_STS 0x82
121 #define RTC_FAILED (1 <<2)
124 #define SMBUS_IO_BASE 0x1000
126 #define SMBHSTSTAT 0x0
127 #define SMBHSTCTL 0x2
128 #define SMBHSTCMD 0x3
129 #define SMBXMITADD 0x4
130 #define SMBHSTDAT0 0x5
131 #define SMBHSTDAT1 0x6
132 #define SMBBLKDAT 0x7
133 #define SMBTRNSADD 0x9
134 #define SMBSLVDATA 0xa
135 #define SMLINK_PIN_CTL 0xe
136 #define SMBUS_PIN_CTL 0xf
138 /* Between 1-10 seconds, We should never timeout normally
139 * Longer than this is just painful when a timeout condition occurs.
141 #define SMBUS_TIMEOUT (100*1000)
144 #define WAK_STS (1 << 15)
145 #define PCIEXPWAK_STS (1 << 14)
146 #define PRBTNOR_STS (1 << 11)
147 #define RTC_STS (1 << 10)
148 #define PWRBTN_STS (1 << 8)
149 #define GBL_STS (1 << 5)
150 #define BM_STS (1 << 4)
151 #define TMROF_STS (1 << 0)
153 #define PCIEXPWAK_DIS (1 << 14)
154 #define RTC_EN (1 << 10)
155 #define PWRBTN_EN (1 << 8)
156 #define GBL_EN (1 << 5)
157 #define TMROF_EN (1 << 0)
159 #define SLP_EN (1 << 13)
160 #define SLP_TYP (7 << 10)
161 #define GBL_RLS (1 << 2)
162 #define BM_RLD (1 << 1)
163 #define SCI_EN (1 << 0)
165 #define PROC_CNT 0x10
169 #define PM2_CNT 0x20 // mobile only
170 #define GPE0_STS 0x28
171 #define PME_B0_STS (1 << 13)
172 #define USB3_STS (1 << 12)
173 #define PME_STS (1 << 11)
174 #define BATLOW_STS (1 << 10)
175 #define GST_STS (1 << 9)
176 #define RI_STS (1 << 8)
177 #define SMB_WAK_STS (1 << 7)
178 #define TCOSCI_STS (1 << 6)
179 #define AC97_STS (1 << 5)
180 #define USB2_STS (1 << 4)
181 #define USB1_STS (1 << 3)
182 #define SWGPE_STS (1 << 2)
183 #define HOT_PLUG_STS (1 << 1)
184 #define THRM_STS (1 << 0)
186 #define PME_B0_EN (1 << 13)
187 #define PME_EN (1 << 11)
189 #define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology
190 #define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
191 #define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
192 #define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS
193 #define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)
194 #define MCSMI_EN (1 << 11) // Trap microcontroller range access
195 #define BIOS_RLS (1 << 7) // asserts SCI on bit set
196 #define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set
197 #define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#
198 #define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#
199 #define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic
200 #define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit
201 #define EOS (1 << 1) // End of SMI (deassert SMI#)
202 #define GBL_SMI_EN (1 << 0) // SMI# generation at all?
204 #define ALT_GP_SMI_EN 0x38
205 #define ALT_GP_SMI_STS 0x3a
206 #define GPE_CNTL 0x42
207 #define DEVACT_STS 0x44
211 #define TCOBASE 0x60 /* TCO Base Address Register */
212 #define TCO1_CNT 0x08 /* TCO1 Control Register */
214 #define GEN_PMCON_1 0xa0
215 #define GEN_PMCON_2 0xa2
216 #define GEN_PMCON_3 0xa4
218 /* GEN_PMCON_3 bits */
219 #define RTC_BATTERY_DEAD (1 << 2)
220 #define RTC_POWER_FAILED (1 << 1)
221 #define SLEEP_AFTER_POWER_FAIL (1 << 0)
223 #endif /* I82801DX_H */