src/mainboard/supermicro/x6dhe_g2/mptable.c

   1 #include <console/console.h>
   2 #include <arch/smp/mpspec.h>
   3 #include <device/pci.h>
   4 #include <string.h>
   5 #include <stdint.h>
   6
   7 static void *smp_write_config_table(void *v)
   8 {
   9         static const char sig[4] = "PCMP";
  10         static const char oem[8] = "COREBOOT";
  11         static const char productid[12] = "X6DHE       ";
  12         struct mp_config_table *mc;
  13         unsigned char bus_num;
  14         unsigned char bus_isa;
  15         unsigned char bus_pxhd_1;
  16         unsigned char bus_pxhd_2;
  17         unsigned char bus_esb6300_1;
  18         unsigned char bus_esb6300_2;
  19
  20         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  21         memset(mc, 0, sizeof(*mc));
  22
  23         memcpy(mc->mpc_signature, sig, sizeof(sig));
  24         mc->mpc_length = sizeof(*mc); /* initially just the header */
  25         mc->mpc_spec = 0x04;
  26         mc->mpc_checksum = 0; /* not yet computed */
  27         memcpy(mc->mpc_oem, oem, sizeof(oem));
  28         memcpy(mc->mpc_productid, productid, sizeof(productid));
  29         mc->mpc_oemptr = 0;
  30         mc->mpc_oemsize = 0;
  31         mc->mpc_entry_count = 0; /* No entries yet... */
  32         mc->mpc_lapic = LAPIC_ADDR;
  33         mc->mpe_length = 0;
  34         mc->mpe_checksum = 0;
  35         mc->reserved = 0;
  36
  37         smp_write_processors(mc);
  38
  39         {
  40                 device_t dev;
  41
  42                 /* esb6300_2 */
  43                 dev = dev_find_slot(0, PCI_DEVFN(0x1c,0));
  44                 if (dev) {
  45                         bus_esb6300_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  46                 } else {
  47                         printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1c.0, using defaults\n");
  48                         bus_esb6300_1 = 6;
  49                 }
  50                 /* esb6300_1 */
  51                 dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
  52                 if (dev) {
  53                         bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  54                         bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
  55                         bus_isa++;
  56                 } else {
  57                         printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
  58                         bus_esb6300_2 = 7;
  59                         bus_isa = 8;
  60                 }
  61                 /* pxhd-1 */
  62                 dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
  63                 if (dev) {
  64                         bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  65                 } else {
  66                         printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
  67                         bus_pxhd_1 = 2;
  68                 }
  69                 /* pxhd-2 */
  70                 dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
  71                 if (dev) {
  72                         bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  73                 } else {
  74                         printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
  75                         bus_pxhd_2 = 3;
  76                 }
  77         }
  78
  79         /* define bus and isa numbers */
  80         for(bus_num = 0; bus_num < bus_isa; bus_num++) {
  81                 smp_write_bus(mc, bus_num, "PCI   ");
  82         }
  83         smp_write_bus(mc, bus_isa, "ISA   ");
  84
  85         /* IOAPIC handling */
  86
  87         smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
  88         smp_write_ioapic(mc, 3, 0x20, 0xfec10000);
  89         {
  90                 struct resource *res;
  91                 device_t dev;
  92                 /* PXHd apic 4 */
  93                 dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
  94                 if (dev) {
  95                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  96                         if (res) {
  97                                 smp_write_ioapic(mc, 0x04, 0x20, res->base);
  98                         }
  99                 } else {
 100                         printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
 101                         printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
 102                 }
 103                 /* PXHd apic 5 */
 104                 dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
 105                 if (dev) {
 106                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
 107                         if (res) {
 108                                 smp_write_ioapic(mc, 0x05, 0x20, res->base);
 109                         }
 110                 } else {
 111                         printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
 112                         printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
 113                 }
 114         }
 115
 116         mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
 117
 118         /* ISA backward compatibility interrupts  */
 119         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 120                 0x00, 0x74, 0x02, 0x10);
 121         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 122                 0x00, 0x77, 0x02, 0x17);
 123         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 124                 0x00, 0x75, 0x02, 0x13);
 125         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 126                 0x00, 0x7c, 0x02, 0x12);
 127         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 128                 0x00, 0x7d, 0x02, 0x11);
 129         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 130                 0x03, 0x08, 0x05, 0x00);
 131         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 132                 0x03, 0x08, 0x05, 0x04);
 133         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 134                 bus_esb6300_1, 0x04, 0x03, 0x00);
 135         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 136                 bus_esb6300_1, 0x08, 0x03, 0x01);
 137         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 138                 bus_esb6300_2, 0x04, 0x02, 0x10);
 139         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
 140                 bus_esb6300_2, 0x08, 0x02, 0x14);
 141
 142         /* Standard local interrupt assignments */
 143         smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 144                 bus_isa, 0x00, MP_APIC_ALL, 0x00);
 145         smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 146                 bus_isa, 0x00, MP_APIC_ALL, 0x01);
 147
 148         /* FIXME verify I have the irqs handled for all of the risers */
 149
 150         /* Compute the checksums */
 151         mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 152
 153         mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 154         printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 155                 mc, smp_next_mpe_entry(mc));
 156         return smp_next_mpe_entry(mc);
 157 }
 158
 159 unsigned long write_smp_table(unsigned long addr)
 160 {
 161         void *v;
 162         v = smp_write_floating_table(addr);
 163         return (unsigned long)smp_write_config_table(v);
 164 }
 165