src/southbridge/amd/cs5535/cs5535.c

   1
   2 #include <arch/io.h>
   3 #include <arch/ioapic.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ops.h>
   7 #include <device/pci_ids.h>
   8 #include <console/console.h>
   9 #include "cs5535.h"
  10
  11 static void nvram_on(struct device *dev)
  12 {
  13 #if 0
  14         volatile char *flash = (volatile unsigned char *)0xFFFc0000;
  15         unsigned char id1, id2;
  16 #endif
  17         unsigned char reg;
  18
  19         /* Enable writes to flash at top of memory */
  20         pci_write_config8(dev, 0x52, 0xee);
  21
  22         /* Set positive decode on ROM */
  23         /* Also, there is no apparent reason to turn off the devoce on the */
  24         /* IDE devices */
  25
  26         reg = pci_read_config8(dev, 0x5b);
  27         reg |= 1 << 5;  /* ROM Decode */
  28         reg |= 1 << 3;  /* Primary IDE decode */
  29         reg |= 1 << 4;  /* Secondary IDE decode */
  30
  31         pci_write_config8(dev, 0x5b, reg);
  32
  33 #if 0           // just to test if the flash is accessible!
  34         *(flash + 0x555) = 0xaa;
  35         *(flash + 0x2aa) = 0x55;
  36         *(flash + 0x555) = 0x90;
  37
  38         id1 = *(volatile unsigned char *) flash;
  39         id2 = *(volatile unsigned char *) (flash + 1);
  40
  41         *flash = 0xf0;
  42
  43         printk(BIOS_DEBUG, "Flash device: MFGID %02x, DEVID %02x\n", id1, id2);
  44 #endif
  45 }
  46
  47
  48 static void southbridge_init(struct device *dev)
  49 {
  50         printk(BIOS_SPEW, "cs5535: %s\n", __func__);
  51         nvram_on(dev);
  52 }
  53
  54 /*
  55 static void dump_south(struct device *dev)
  56 {
  57         int i, j;
  58
  59         for(i=0; i<256; i+=16) {
  60                 printk(BIOS_DEBUG, "0x%02x: ", i);
  61                 for(j=0; j<16; j++)
  62                         printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i+j));
  63                 printk(BIOS_DEBUG, "\n");
  64         }
  65 }
  66 */
  67
  68 static void southbridge_enable(struct device *dev)
  69 {
  70         printk(BIOS_SPEW, "%s: dev is %p\n", __func__, dev);
  71 }
  72
  73 static void cs5535_read_resources(device_t dev)
  74 {
  75         struct resource *res;
  76
  77         pci_dev_read_resources(dev);
  78
  79         res = new_resource(dev, 1);
  80         res->base = 0x0UL;
  81         res->size = 0x1000UL;
  82         res->limit = 0xffffUL;
  83         res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  84
  85         res = new_resource(dev, 3); /* IOAPIC */
  86         res->base = IO_APIC_ADDR;
  87         res->size = 0x00001000;
  88         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  89 }
  90
  91 static struct device_operations southbridge_ops = {
  92         .read_resources   = cs5535_read_resources,
  93         .set_resources    = pci_dev_set_resources,
  94         .enable_resources = pci_dev_enable_resources,
  95         .init             = southbridge_init,
  96         .enable           = southbridge_enable,
  97         .scan_bus         = scan_static_bus,
  98 };
  99
 100 static const struct pci_driver cs5535_pci_driver __pci_driver = {
 101         .ops    = &southbridge_ops,
 102         .vendor = PCI_VENDOR_ID_NS,
 103         .device = PCI_DEVICE_ID_NS_CS5535
 104 };
 105
 106 struct chip_operations southbridge_amd_cs5535_ops = {
 107         CHIP_NAME("AMD Geode CS5535 Southbridge")
 108             /* This is only called when this device is listed in the
 109              * static device tree.
 110              */
 111             .enable_dev = southbridge_enable,
 112 };