2 * This file is part of the coreboot project.
4 * Copyright (C) 2003 Linux Networx
5 * Copyright (C) 2003 SuSE Linux AG
6 * Copyright (C) 2005 Tyan Computer
7 * (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer)
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <console/console.h>
25 #include <device/device.h>
26 #include <device/pci.h>
27 #include <device/pci_ids.h>
28 #include <pc80/mc146818rtc.h>
29 #include <pc80/isa-dma.h>
33 #define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */
37 typedef struct southbridge_intel_i82801ax_config config_t;
39 /* PIRQ[n]_ROUT[3:0] - IRQ Routing (ISA compatible)
40 * 0x00 - 0000 = Reserved
41 * 0x01 - 0001 = Reserved
42 * 0x02 - 0010 = Reserved
48 * 0x08 - 1000 = Reserved
53 * 0x0D - 1101 = Reserved
57 * PIRQ[n]_ROUT[7] - Interrupt Routing Enable (IRQEN)
58 * 0 - The PIRQ is routed to the ISA-compatible interrupt specified above.
59 * 1 - The PIRQ is not routed to the 8259.
68 * Use 0x0ef8 for a bitmap to cover all these IRQ's.
69 * Use the defined IRQ values above or set mainboard
70 * specific IRQ values in your mainboards Config.lb.
72 static void i82801ax_enable_apic(struct device *dev)
75 volatile u32 *ioapic_index = (volatile u32 *)0xfec00000;
76 volatile u32 *ioapic_data = (volatile u32 *)0xfec00010;
78 /* Set ACPI base address (I/O space). */
79 pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
81 /* Enable ACPI I/O range decode and ACPI power management. */
82 pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
84 reg32 = pci_read_config32(dev, GEN_CNTL);
85 reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */
86 reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */
87 reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */
88 reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */
89 pci_write_config32(dev, GEN_CNTL, reg32);
90 printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
93 *ioapic_data = (1 << 25);
97 printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32);
98 if (reg32 != (1 << 25))
101 /* TODO: From i82801ca, needed/useful on other ICH? */
102 *ioapic_index = 3; /* Select Boot Configuration register. */
103 *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
106 static void i82801ax_enable_serial_irqs(struct device *dev)
108 /* Set packet length and toggle silent mode bit. */
109 pci_write_config8(dev, SERIRQ_CNTL,
110 (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
111 pci_write_config8(dev, SERIRQ_CNTL,
112 (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
113 /* TODO: Explain/#define the real meaning of these magic numbers. */
116 static void i82801ax_pirq_init(device_t dev)
119 config_t *config = dev->chip_info;
121 reg8 = (config->pirqa_routing) ? config->pirqa_routing : PIRQA;
122 pci_write_config8(dev, PIRQA_ROUT, reg8);
124 reg8 = (config->pirqb_routing) ? config->pirqb_routing : PIRQB;
125 pci_write_config8(dev, PIRQB_ROUT, reg8);
127 reg8 = (config->pirqc_routing) ? config->pirqc_routing : PIRQC;
128 pci_write_config8(dev, PIRQC_ROUT, reg8);
130 reg8 = (config->pirqd_routing) ? config->pirqd_routing : PIRQD;
131 pci_write_config8(dev, PIRQD_ROUT, reg8);
134 static void i82801ax_power_options(device_t dev)
140 /* power after power fail */
141 /* FIXME this doesn't work! */
142 /* Which state do we want to goto after g3 (power restored)?
146 pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
147 printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off");
149 /* Set up NMI on errors. */
151 byte &= ~(1 << 3); /* IOCHK# NMI Enable */
152 byte &= ~(1 << 2); /* PCI SERR# Enable */
156 nmi_option = NMI_OFF;
157 get_option(&nmi_option, "nmi");
159 byte &= ~(1 << 7); /* Set NMI. */
164 static void gpio_init(device_t dev)
166 pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1));
167 pci_write_config8(dev, GPIO_CNTL, GPIO_EN);
170 static void i82801ax_rtc_init(struct device *dev)
176 reg8 = pci_read_config8(dev, GEN_PMCON_3);
177 rtc_failed = reg8 & RTC_BATTERY_DEAD;
179 reg8 &= ~(1 << 1); /* Preserve the power fail state. */
180 pci_write_config8(dev, GEN_PMCON_3, reg8);
182 reg32 = pci_read_config32(dev, GEN_STA);
183 rtc_failed |= reg32 & (1 << 2);
184 rtc_init(rtc_failed);
186 /* Enable access to the upper 128 byte bank of CMOS RAM. */
187 pci_write_config8(dev, RTC_CONF, 0x04);
190 static void i82801ax_lpc_route_dma(struct device *dev, uint8_t mask)
195 reg16 = pci_read_config16(dev, PCI_DMA_CFG);
197 for (i = 0; i < 8; i++) {
200 reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
202 pci_write_config16(dev, PCI_DMA_CFG, reg16);
205 static void i82801ax_lpc_decode_en(device_t dev)
207 /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
208 * LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
209 * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7.
210 * We also need to set the value for LPC I/F Enables Register.
212 pci_write_config8(dev, COM_DEC, 0x10);
213 pci_write_config16(dev, LPC_EN, 0x300F);
216 static void lpc_init(struct device *dev)
218 /* Set the value for PCI command register. */
219 pci_write_config16(dev, PCI_COMMAND, 0x000f);
221 /* IO APIC initialization. */
222 i82801ax_enable_apic(dev);
224 i82801ax_enable_serial_irqs(dev);
226 /* Setup the PIRQ. */
227 i82801ax_pirq_init(dev);
229 /* Setup power options. */
230 i82801ax_power_options(dev);
232 /* Set the state of the GPIO lines. */
235 /* Initialize the real time clock. */
236 i82801ax_rtc_init(dev);
239 i82801ax_lpc_route_dma(dev, 0xff);
241 /* Initialize ISA DMA. */
244 /* Setup decode ports and LPC I/F enables. */
245 i82801ax_lpc_decode_en(dev);
248 static void i82801ax_lpc_read_resources(device_t dev)
250 struct resource *res;
252 /* Get the normal PCI resources of this device. */
253 pci_dev_read_resources(dev);
255 /* Add an extra subtractive resource for both memory and I/O. */
256 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
259 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
260 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
262 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
263 res->base = 0xff800000;
264 res->size = 0x00800000; /* 8 MB for flash */
265 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
266 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
268 res = new_resource(dev, 3); /* IOAPIC */
269 res->base = 0xfec00000;
270 res->size = 0x00001000;
271 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
274 static struct device_operations lpc_ops = {
275 .read_resources = i82801ax_lpc_read_resources,
276 .set_resources = pci_dev_set_resources,
277 .enable_resources = pci_dev_enable_resources,
279 .scan_bus = scan_static_bus,
280 .enable = i82801ax_enable,
284 static const struct pci_driver i82801aa_lpc __pci_driver = {
286 .vendor = PCI_VENDOR_ID_INTEL,
291 static const struct pci_driver i82801ab_lpc __pci_driver = {
293 .vendor = PCI_VENDOR_ID_INTEL,