src/mainboard/amd/serengeti_cheetah/mptable.c

   1 #include <console/console.h>
   2 #include <arch/smp/mpspec.h>
   3 #include <device/pci.h>
   4 #include <string.h>
   5 #include <stdint.h>
   6 #if CONFIG_LOGICAL_CPUS==1
   7 #include <cpu/amd/multicore.h>
   8 #endif
   9
  10 #include <cpu/amd/amdk8_sysconf.h>
  11 #include "mb_sysconf.h"
  12
  13
  14
  15 static void *smp_write_config_table(void *v)
  16 {
  17         static const char sig[4] = "PCMP";
  18         static const char oem[8] = "COREBOOT";
  19         static const char productid[12] = "SERENGETI   ";
  20         struct mp_config_table *mc;
  21
  22         unsigned char bus_num;
  23         int i, j;
  24         struct mb_sysconf_t *m;
  25
  26         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  27         memset(mc, 0, sizeof(*mc));
  28
  29         memcpy(mc->mpc_signature, sig, sizeof(sig));
  30         mc->mpc_length = sizeof(*mc); /* initially just the header */
  31         mc->mpc_spec = 0x04;
  32         mc->mpc_checksum = 0; /* not yet computed */
  33         memcpy(mc->mpc_oem, oem, sizeof(oem));
  34         memcpy(mc->mpc_productid, productid, sizeof(productid));
  35         mc->mpc_oemptr = 0;
  36         mc->mpc_oemsize = 0;
  37         mc->mpc_entry_count = 0; /* No entries yet... */
  38         mc->mpc_lapic = LAPIC_ADDR;
  39         mc->mpe_length = 0;
  40         mc->mpe_checksum = 0;
  41         mc->reserved = 0;
  42
  43         smp_write_processors(mc);
  44
  45         get_bus_conf();
  46
  47         m = sysconf.mb;
  48
  49 /*Bus:          Bus ID  Type*/
  50        /* define bus and isa numbers */
  51         for(bus_num = 0; bus_num < m->bus_isa; bus_num++) {
  52                 smp_write_bus(mc, bus_num, "PCI   ");
  53         }
  54         smp_write_bus(mc, m->bus_isa, "ISA   ");
  55
  56 /*I/O APICs:    APIC ID Version State           Address*/
  57         smp_write_ioapic(mc, m->apicid_8111, 0x11, 0xfec00000); //8111
  58         {
  59                 device_t dev;
  60                 struct resource *res;
  61                 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
  62                 if (dev) {
  63                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  64                         if (res) {
  65                                 smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
  66                         }
  67                 }
  68                 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
  69                 if (dev) {
  70                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  71                         if (res) {
  72                                 smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
  73                         }
  74                 }
  75
  76                 j = 0;
  77
  78                 for(i=1; i< sysconf.hc_possible_num; i++) {
  79                         if(!(sysconf.pci1234[i] & 0x1) ) continue;
  80
  81                         switch(sysconf.hcid[i]) {
  82                         case 1: // 8132
  83                         case 3: // 8131
  84                                 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
  85                                 if (dev) {
  86                                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  87                                         if (res) {
  88                                                 smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
  89                                         }
  90                                 }
  91                                 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
  92                                 if (dev) {
  93                                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  94                                         if (res) {
  95                                                 smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
  96                                         }
  97                                 }
  98                                 break;
  99                         }
 100                         j++;
 101                 }
 102
 103         }
 104
 105         mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_8111, 0);
 106
 107 /*I/O Ints:     Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 108 //??? What
 109         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
 110
 111 // Onboard AMD USB
 112         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
 113
 114 //Slot 3  PCI 32
 115         for(i=0;i<4;i++) {
 116                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
 117         }
 118
 119
 120 //Slot 4 PCI 32
 121         for(i=0;i<4;i++) {
 122                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
 123         }
 124
 125
 126 //Slot 1 PCI-X 133/100/66
 127         for(i=0;i<4;i++) {
 128                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); //
 129         }
 130
 131
 132 //Slot 2 PCI-X 133/100/66
 133         for(i=0;i<4;i++) {
 134                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
 135         }
 136
 137         j = 0;
 138
 139         for(i=1; i< sysconf.hc_possible_num; i++) {
 140                 if(!(sysconf.pci1234[i] & 0x1) ) continue;
 141                 int ii;
 142                 device_t dev;
 143                 struct resource *res;
 144                 switch(sysconf.hcid[i]) {
 145                 case 1:
 146                 case 3:
 147                         dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
 148                         if (dev) {
 149                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
 150                                 if (res) {
 151                                         //Slot 1 PCI-X 133/100/66
 152                                         for(ii=0;ii<4;ii++) {
 153                                                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
 154                                         }
 155                                 }
 156                         }
 157
 158                         dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
 159                         if (dev) {
 160                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
 161                                 if (res) {
 162                                         //Slot 2 PCI-X 133/100/66
 163                                         for(ii=0;ii<4;ii++) {
 164                                                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
 165                                         }
 166                                 }
 167                         }
 168
 169                         break;
 170                 case 2:
 171
 172                 //  Slot AGP
 173                         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
 174                         break;
 175                 }
 176
 177                 j++;
 178         }
 179
 180
 181
 182 /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
 183         smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
 184         smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
 185         /* There is no extension information... */
 186
 187         /* Compute the checksums */
 188         mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 189         mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 190         printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 191                 mc, smp_next_mpe_entry(mc));
 192         return smp_next_mpe_entry(mc);
 193 }
 194
 195 unsigned long write_smp_table(unsigned long addr)
 196 {
 197         void *v;
 198         v = smp_write_floating_table(addr);
 199         return (unsigned long)smp_write_config_table(v);
 200 }