2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <device/device.h>
23 #include <device/pci.h>
24 #include <device/pci_ops.h>
25 #include <device/pci_ids.h>
26 #include <pc80/mc146818rtc.h>
27 #include <pc80/i8259.h>
28 #include <pc80/keyboard.h>
29 #include <pc80/isa-dma.h>
30 #include <cpu/x86/lapic.h>
31 #include <arch/ioapic.h>
34 #define ACPI_IO_BASE 0x400
35 #define HPET_ADDR 0xfe800000UL
37 static const unsigned char pci_irqs[4] = { 11, 11, 10, 10 };
39 static const unsigned char usb_pins[4] = { 'A', 'B', 'C', 'D' };
40 static const unsigned char vga_pins[4] = { 'A', 'B', 'C', 'D' };
41 static const unsigned char slot_pins[4] = { 'B', 'C', 'D', 'A' };
42 static const unsigned char ac97_pins[4] = { 'B', 'C', 'D', 'A' };
44 static unsigned char *pin_to_irq(const unsigned char *pin)
46 static unsigned char irqs[4];
48 for (i = 0; i < 4; i++)
49 irqs[i] = pci_irqs[pin[i] - 'A'];
54 static void pci_routing_fixup(struct device *dev)
56 printk(BIOS_DEBUG, "%s: device is %p\n", __FUNCTION__, dev);
58 /* set up PCI IRQ routing */
59 pci_write_config8(dev, 0x55, pci_irqs[0] << 4);
60 pci_write_config8(dev, 0x56, pci_irqs[1] | (pci_irqs[2] << 4));
61 pci_write_config8(dev, 0x57, pci_irqs[3] << 4);
64 printk(BIOS_DEBUG, "Setting up USB interrupts.\n");
65 pci_assign_irqs(0, 0x10, pin_to_irq(usb_pins));
67 printk(BIOS_DEBUG, "Setting up VGA interrupts.\n");
68 pci_assign_irqs(1, 0x00, pin_to_irq(vga_pins));
70 printk(BIOS_DEBUG, "Setting up PCI slot interrupts.\n");
71 pci_assign_irqs(2, 0x04, pin_to_irq(slot_pins));
74 printk(BIOS_DEBUG, "Setting up AC97 interrupts.\n");
75 pci_assign_irqs(0x80, 0x1, pin_to_irq(ac97_pins));
79 * Set up the power management capabilities directly into ACPI mode. This
80 * avoids having to handle any System Management Interrupts (SMI's) which I
81 * can't figure out how to do !!!!
84 static void setup_pm(device_t dev)
86 /* Debounce LID and PWRBTN# Inputs for 16ms. */
87 pci_write_config8(dev, 0x80, 0x20);
89 /* Set ACPI base address to IO ACPI_IO_BASE */
90 pci_write_config16(dev, 0x88, ACPI_IO_BASE | 1);
92 /* set ACPI irq to 9 */
93 pci_write_config8(dev, 0x82, 0x49);
95 /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
96 pci_write_config16(dev, 0x84, 0x609a);
98 /* SMI output level to low, 7.5us throttle clock */
99 pci_write_config8(dev, 0x8d, 0x18);
101 /* GP Timer Control 1s */
102 pci_write_config8(dev, 0x93, 0x88);
105 pci_write_config8(dev, 0x94, 0x20); // 0x20??
107 /* 7 = stp to sust delay 1msec
108 * 6 = SUSST# Deasserted Before PWRGD for STD
110 pci_write_config8(dev, 0x95, 0xc0); // 0xc1??
112 /* Disable GP2 & GP3 Timer */
113 pci_write_config8(dev, 0x98, 0);
115 /* GP2 Timer Counter */
116 pci_write_config8(dev, 0x99, 0xfb);
117 /* GP3 Timer Counter */
118 //pci_write_config8(dev, 0x9a, 0x20);
120 /* Multi Function Select 1 */
121 pci_write_config8(dev, 0xe4, 0x00);
123 /* Multi Function Select 2 */
124 pci_write_config8(dev, 0xe5, 0x41); //??
126 /* Enable ACPI access (and setup like award) */
127 pci_write_config8(dev, 0x81, 0x84);
129 /* Clear status events. */
130 outw(0xffff, ACPI_IO_BASE + 0x00);
131 outw(0xffff, ACPI_IO_BASE + 0x20);
132 outw(0xffff, ACPI_IO_BASE + 0x28);
133 outl(0xffffffff, ACPI_IO_BASE + 0x30);
135 /* Disable SCI on GPIO. */
136 outw(0x0, ACPI_IO_BASE + 0x22);
138 /* Disable SMI on GPIO. */
139 outw(0x0, ACPI_IO_BASE + 0x24);
141 /* Disable all global enable SMIs. */
142 outw(0x0, ACPI_IO_BASE + 0x2a);
144 /* All SMI off, both IDE buses ON, PSON rising edge. */
145 outw(0x0, ACPI_IO_BASE + 0x2c);
147 /* Primary activity SMI disable. */
148 outl(0x0, ACPI_IO_BASE + 0x34);
150 /* GP timer reload on none. */
151 outl(0x0, ACPI_IO_BASE + 0x38);
153 /* Disable extended IO traps. */
154 outb(0x0, ACPI_IO_BASE + 0x42);
156 /* SCI is generated for RTC/pwrBtn/slpBtn. */
157 outw(0x0001, ACPI_IO_BASE + 0x04);
159 /* Allow SLP# signal to assert LDTSTOP_L.
160 * Will work for C3 and for FID/VID change.
162 outb(0x1, ACPI_IO_BASE + 0x11);
165 static void cx700_set_lpc_registers(struct device *dev)
167 unsigned char enables;
169 printk(BIOS_DEBUG, "VIA CX700 LPC bridge init\n");
171 // enable the internal I/O decode
172 enables = pci_read_config8(dev, 0x6C);
174 pci_write_config8(dev, 0x6C, enables);
176 // Map 4MB of FLASH into the address space
177 // pci_write_config8(dev, 0x41, 0x7f);
179 // Set bit 6 of 0x40, because Award does it (IO recovery time)
180 // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
181 // interrupts can be properly marked as level triggered.
182 enables = pci_read_config8(dev, 0x40);
184 pci_write_config8(dev, 0x40, enables);
186 /* DMA Line buffer control */
187 enables = pci_read_config8(dev, 0x42);
189 pci_write_config8(dev, 0x42, enables);
191 /* I/O recovery time */
192 pci_write_config8(dev, 0x4c, 0x44);
194 /* ROM memory cycles go to LPC. */
195 pci_write_config8(dev, 0x59, 0x80);
197 /* Enable SM dynamic clock gating */
198 pci_write_config8(dev, 0x5b, 0x01);
200 /* Set Read Pass Write Control Enable */
201 pci_write_config8(dev, 0x48, 0x0c);
203 /* Set SM Misc Control: Enable Internal APIC . */
204 enables = pci_read_config8(dev, 0x58);
206 pci_write_config8(dev, 0x58, enables);
207 enables = pci_read_config8(dev, 0x4d);
209 pci_write_config8(dev, 0x4d, enables);
211 /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
212 enables = pci_read_config8(dev, 0x4f);
214 pci_write_config8(dev, 0x4f, enables);
216 /* enable KBC configuration */
217 pci_write_config8(dev, 0x51, 0x1f);
219 /* enable serial irq */
220 pci_write_config8(dev, 0x52, 0x9);
223 pci_write_config8(dev, 0x53, 0x00);
225 // Power management setup
228 /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
229 pci_write_config8(dev, 0x40, 0x54);
231 /* Enable HPET timer */
232 pci_write_config32(dev, 0x68, (1 << 31) | (HPET_ADDR >> 8));
236 static void cx700_read_resources(device_t dev)
238 struct resource *res;
240 /* Make sure we call our childrens set/enable functions - these
241 * are not called unless this device has a resource to set.
244 pci_dev_read_resources(dev);
246 res = new_resource(dev, 1);
249 res->limit = 0xffffUL;
250 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
252 res = new_resource(dev, 3); /* IOAPIC */
253 res->base = IO_APIC_ADDR;
254 res->size = 0x00001000;
255 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
258 static void cx700_set_resources(device_t dev)
260 struct resource *resource;
261 resource = find_resource(dev, 1);
262 resource->flags |= IORESOURCE_STORED;
263 pci_dev_set_resources(dev);
266 static void cx700_enable_resources(device_t dev)
268 /* Enable SuperIO decoding */
269 pci_dev_enable_resources(dev);
272 static void cx700_lpc_init(struct device *dev)
274 cx700_set_lpc_registers(dev);
278 setup_ioapic(IO_APIC_ADDR, IO_APIC_ID);
281 /* Initialize interrupts */
282 pci_routing_fixup(dev);
283 /* make sure interupt controller is configured before keyboard init */
286 /* Start the Real Time Clock */
289 /* Initialize isa dma */
292 /* Initialize keyboard controller */
296 static struct device_operations cx700_lpc_ops = {
297 .read_resources = cx700_read_resources,
298 .set_resources = cx700_set_resources,
299 .enable_resources = cx700_enable_resources,
300 .init = &cx700_lpc_init,
301 .scan_bus = scan_static_bus,
304 static const struct pci_driver lpc_driver __pci_driver = {
305 .ops = &cx700_lpc_ops,
306 .vendor = PCI_VENDOR_ID_VIA,