1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
7 #include <cpu/amd/amdk8_sysconf.h>
9 extern unsigned char bus_isa;
10 extern unsigned char bus_8131_0;
11 extern unsigned char bus_8131_1;
12 extern unsigned char bus_8131_2;
13 extern unsigned char bus_8111_0;
14 extern unsigned char bus_8111_1;
15 extern unsigned apicid_8111;
16 extern unsigned apicid_8131_1;
17 extern unsigned apicid_8131_2;
19 extern unsigned sbdn3;
23 static void *smp_write_config_table(void *v)
25 static const char sig[4] = "PCMP";
26 static const char oem[8] = "COREBOOT";
27 static const char productid[12] = "DL145G1 ";
28 struct mp_config_table *mc;
30 unsigned char bus_num;
32 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
33 memset(mc, 0, sizeof(*mc));
35 memcpy(mc->mpc_signature, sig, sizeof(sig));
36 mc->mpc_length = sizeof(*mc); /* initially just the header */
38 mc->mpc_checksum = 0; /* not yet computed */
39 memcpy(mc->mpc_oem, oem, sizeof(oem));
40 memcpy(mc->mpc_productid, productid, sizeof(productid));
43 mc->mpc_entry_count = 0; /* No entries yet... */
44 mc->mpc_lapic = LAPIC_ADDR;
49 smp_write_processors(mc);
55 /* define bus and isa numbers */
56 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
57 smp_write_bus(mc, bus_num, "PCI ");
59 smp_write_bus(mc, bus_isa, "ISA ");
62 /*I/O APICs: APIC ID Version State Address*/
63 smp_write_ioapic(mc, apicid_8111, 0x20, 0xfec00000);
67 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
69 res = find_resource(dev, PCI_BASE_ADDRESS_0);
71 smp_write_ioapic(mc, apicid_8131_1, 0x20, res->base);
74 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
76 res = find_resource(dev, PCI_BASE_ADDRESS_0);
78 smp_write_ioapic(mc, apicid_8131_2, 0x20, res->base);
84 mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
87 // The commented-out lines are auto-detected on my servers.
89 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
90 // Integrated SMBus 2.0
91 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|3, apicid_8111 , 0x15);
92 // Integrated AMD AC97 Audio
93 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11);
94 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12);
96 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x4 <<2)|0, apicid_8111 , 0x10);
97 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x0 <<2)|3, apicid_8111 , 0x13);
98 // On board ATI Rage XL
99 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14);
100 // On board Broadcom nics
101 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|0, apicid_8131_2, 0x03);
102 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|1, apicid_8131_2, 0x00);
104 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02);
107 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|0, apicid_8131_1, 0x01);
108 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02);
109 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03);
110 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04);
112 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
113 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
114 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
115 /* There is no extension information... */
117 /* Compute the checksums */
118 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
119 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
120 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
121 mc, smp_next_mpe_entry(mc));
122 return smp_next_mpe_entry(mc);
125 unsigned long write_smp_table(unsigned long addr)
128 v = smp_write_floating_table(addr);
129 return (unsigned long)smp_write_config_table(v);