1 /* generated by MPTable, version 2.0.15*/
2 /* as modified by RGM for coreboot */
3 #include <console/console.h>
4 #include <arch/smp/mpspec.h>
5 #include <device/pci.h>
9 static void *smp_write_config_table(void *v)
11 static const char sig[4] = "PCMP";
12 static const char oem[8] = "COREBOOT";
13 static const char productid[12] = "P4DPE ";
14 struct mp_config_table *mc;
17 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
18 memset(mc, 0, sizeof(*mc));
20 memcpy(mc->mpc_signature, sig, sizeof(sig));
21 mc->mpc_length = sizeof(*mc); /* initially just the header */
23 mc->mpc_checksum = 0; /* not yet computed */
24 memcpy(mc->mpc_oem, oem, sizeof(oem));
25 memcpy(mc->mpc_productid, productid, sizeof(productid));
28 mc->mpc_entry_count = 0; /* No entries yet... */
29 mc->mpc_lapic = LAPIC_ADDR;
34 smp_write_processors(mc);
35 mptable_write_buses(mc, NULL, &isa_bus);
37 /*I/O APICs: APIC ID Version State Address*/
38 smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
42 dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
44 res = find_resource(dev, PCI_BASE_ADDRESS_0);
46 smp_write_ioapic(mc, 3, 0x20, res->base);
49 dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
51 res = find_resource(dev, PCI_BASE_ADDRESS_0);
53 smp_write_ioapic(mc, 4, 0x20, res->base);
56 dev = dev_find_slot(4, PCI_DEVFN(0x1e,0));
58 res = find_resource(dev, PCI_BASE_ADDRESS_0);
60 smp_write_ioapic(mc, 5, 0x20, res->base);
63 dev = dev_find_slot(4, PCI_DEVFN(0x1c,0));
65 res = find_resource(dev, PCI_BASE_ADDRESS_0);
67 smp_write_ioapic(mc, 8, 0x20, res->base);
71 mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
73 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
74 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x15);
75 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x15);
76 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x2, 0x15);
77 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x2, 0x15);
78 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x42, 0x2, 0x15);
79 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x46, 0x2, 0x16);
80 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
81 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x48, 0x2, 0x17);
82 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x3d, 0x2, 0x14);
83 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
84 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0);
85 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1);
86 /* There is no extension information... */
88 /* Compute the checksums */
89 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
90 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
91 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
92 mc, smp_next_mpe_entry(mc));
93 return smp_next_mpe_entry(mc);
96 unsigned long write_smp_table(unsigned long addr)
99 v = smp_write_floating_table(addr);
100 return (unsigned long)smp_write_config_table(v);