1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <arch/ioapic.h>
4 #include <device/pci.h>
8 static void *smp_write_config_table(void *v)
10 static const char sig[4] = "PCMP";
11 static const char oem[8] = "COREBOOT";
12 static const char productid[12] = "S2735 ";
13 struct mp_config_table *mc;
16 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
17 memset(mc, 0, sizeof(*mc));
19 memcpy(mc->mpc_signature, sig, sizeof(sig));
20 mc->mpc_length = sizeof(*mc); /* initially just the header */
22 mc->mpc_checksum = 0; /* not yet computed */
23 memcpy(mc->mpc_oem, oem, sizeof(oem));
24 memcpy(mc->mpc_productid, productid, sizeof(productid));
27 mc->mpc_entry_count = 0; /* No entries yet... */
28 mc->mpc_lapic = LAPIC_ADDR;
33 smp_write_processors(mc);
34 mptable_write_buses(mc, NULL, &isa_bus);
35 /*I/O APICs: APIC ID Version State Address*/
36 smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR);
40 dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
42 res = find_resource(dev, PCI_BASE_ADDRESS_0);
44 smp_write_ioapic(mc, 0x09, 0x20, res->base);
47 dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
49 res = find_resource(dev, PCI_BASE_ADDRESS_0);
51 smp_write_ioapic(mc, 0x0a, 0x20, res->base);
55 mptable_add_isa_interrupts(mc, isa_bus, 0x8, 0);
57 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
60 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7c, 0x8, 0x12);
61 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x8, 0x11);
62 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x8, 0x10);
63 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x8, 0x13);
64 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x8, 0x17);
67 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x8, 0x8, 0x12);
69 //onboard intel 82551 10/100
70 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x4, 0x8, 0x11);
72 // onboard Intel 82547 1000
73 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x4, 0xa, 0x0);
74 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x5, 0xa, 0x1);
77 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|0, 0x8, 0x12);
78 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|1, 0x8, 0x13);
79 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|2, 0x8, 0x10);
80 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|3, 0x8, 0x11);
82 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|0, 0x8, 0x13);
83 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|1, 0x8, 0x10);
84 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|2, 0x8, 0x11);
85 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|3, 0x8, 0x12);
87 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|0, 0x9, 0x0);
88 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|1, 0x9, 0x1);
89 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|2, 0x9, 0x2);
90 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|3, 0x9, 0x3);
92 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|0, 0x9, 0x4);
93 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|1, 0x9, 0x5);
94 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|2, 0x9, 0x6);
95 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|3, 0x9, 0x7);
97 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
98 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x0);
99 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x1);
101 MP Config Extended Table Entries:
105 bus ID: 0 address type: I/O address
107 address range: 0x6000
110 bus ID: 0 address type: I/O address
115 bus ID: 0 address type: memory address
116 address base: 0xa0000
117 address range: 0x20000
120 bus ID: 0 address type: memory address
121 address base: 0xfc700000
122 address range: 0x2500000
125 bus ID: 0 address type: prefetch address
126 address base: 0xff600000
127 address range: 0x500000
130 bus ID: 5 bus info: 0x01 parent bus ID: 0--
131 Compatibility Bus Address
132 bus ID: 0 address modifier: add
133 predefined range: 0x00000000--
134 Compatibility Bus Address
135 bus ID: 0 address modifier: add
136 predefined range: 0x00000001 // There is no extension information...
138 /* Compute the checksums */
139 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
140 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
141 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
142 mc, smp_next_mpe_entry(mc));
143 return smp_next_mpe_entry(mc);
146 unsigned long write_smp_table(unsigned long addr)
149 v = smp_write_floating_table(addr);
150 return (unsigned long)smp_write_config_table(v);