src/southbridge/amd/cs5535/cs5535.c

   1
   2 #include <arch/io.h>
   3 #include <device/device.h>
   4 #include <device/pci.h>
   5 #include <device/pci_ops.h>
   6 #include <device/pci_ids.h>
   7 #include <console/console.h>
   8 #include "cs5535.h"
   9
  10 static void nvram_on(struct device *dev)
  11 {
  12 #if 0
  13         volatile char *flash = (volatile unsigned char *)0xFFFc0000;
  14         unsigned char id1, id2;
  15 #endif
  16         unsigned char reg;
  17
  18         /* Enable writes to flash at top of memory */
  19         pci_write_config8(dev, 0x52, 0xee);
  20
  21         /* Set positive decode on ROM */
  22         /* Also, there is no apparent reason to turn off the devoce on the */
  23         /* IDE devices */
  24
  25         reg = pci_read_config8(dev, 0x5b);
  26         reg |= 1 << 5;  /* ROM Decode */
  27         reg |= 1 << 3;  /* Primary IDE decode */
  28         reg |= 1 << 4;  /* Secondary IDE decode */
  29
  30         pci_write_config8(dev, 0x5b, reg);
  31
  32 #if 0           // just to test if the flash is accessible!
  33         *(flash + 0x555) = 0xaa;
  34         *(flash + 0x2aa) = 0x55;
  35         *(flash + 0x555) = 0x90;
  36
  37         id1 = *(volatile unsigned char *) flash;
  38         id2 = *(volatile unsigned char *) (flash + 1);
  39
  40         *flash = 0xf0;
  41
  42         printk(BIOS_DEBUG, "Flash device: MFGID %02x, DEVID %02x\n", id1, id2);
  43 #endif
  44 }
  45
  46
  47 static void southbridge_init(struct device *dev)
  48 {
  49         printk(BIOS_SPEW, "cs5535: %s\n", __func__);
  50         nvram_on(dev);
  51 }
  52
  53 /*
  54 static void dump_south(struct device *dev)
  55 {
  56         int i, j;
  57
  58         for(i=0; i<256; i+=16) {
  59                 printk(BIOS_DEBUG, "0x%02x: ", i);
  60                 for(j=0; j<16; j++)
  61                         printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i+j));
  62                 printk(BIOS_DEBUG, "\n");
  63         }
  64 }
  65 */
  66
  67 static void southbridge_enable(struct device *dev)
  68 {
  69         printk(BIOS_SPEW, "%s: dev is %p\n", __func__, dev);
  70 }
  71
  72 static void cs5535_read_resources(device_t dev)
  73 {
  74         struct resource *res;
  75
  76         pci_dev_read_resources(dev);
  77
  78         res = new_resource(dev, 1);
  79         res->base = 0x0UL;
  80         res->size = 0x1000UL;
  81         res->limit = 0xffffUL;
  82         res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  83
  84         res = new_resource(dev, 3); /* IOAPIC */
  85         res->base = 0xfec00000;
  86         res->size = 0x00001000;
  87         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  88 }
  89
  90 static struct device_operations southbridge_ops = {
  91         .read_resources   = cs5535_read_resources,
  92         .set_resources    = pci_dev_set_resources,
  93         .enable_resources = pci_dev_enable_resources,
  94         .init             = southbridge_init,
  95         .enable           = southbridge_enable,
  96         .scan_bus         = scan_static_bus,
  97 };
  98
  99 static const struct pci_driver cs5535_pci_driver __pci_driver = {
 100         .ops    = &southbridge_ops,
 101         .vendor = PCI_VENDOR_ID_NS,
 102         .device = PCI_DEVICE_ID_NS_CS5535
 103 };
 104
 105 struct chip_operations southbridge_amd_cs5535_ops = {
 106         CHIP_NAME("AMD Geode CS5535 Southbridge")
 107             /* This is only called when this device is listed in the
 108              * static device tree.
 109              */
 110             .enable_dev = southbridge_enable,
 111 };