1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
7 static void *smp_write_config_table(void *v)
9 static const char sig[4] = "PCMP";
10 static const char oem[8] = "COREBOOT";
11 static const char productid[12] = "S2735 ";
12 struct mp_config_table *mc;
15 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
16 memset(mc, 0, sizeof(*mc));
18 memcpy(mc->mpc_signature, sig, sizeof(sig));
19 mc->mpc_length = sizeof(*mc); /* initially just the header */
21 mc->mpc_checksum = 0; /* not yet computed */
22 memcpy(mc->mpc_oem, oem, sizeof(oem));
23 memcpy(mc->mpc_productid, productid, sizeof(productid));
26 mc->mpc_entry_count = 0; /* No entries yet... */
27 mc->mpc_lapic = LAPIC_ADDR;
32 smp_write_processors(mc);
33 mptable_write_buses(mc, NULL, &isa_bus);
34 /*I/O APICs: APIC ID Version State Address*/
35 smp_write_ioapic(mc, 8, 0x20, 0xfec00000);
39 dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
41 res = find_resource(dev, PCI_BASE_ADDRESS_0);
43 smp_write_ioapic(mc, 0x09, 0x20, res->base);
46 dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
48 res = find_resource(dev, PCI_BASE_ADDRESS_0);
50 smp_write_ioapic(mc, 0x0a, 0x20, res->base);
54 mptable_add_isa_interrupts(mc, isa_bus, 0x8, 0);
56 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
59 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7c, 0x8, 0x12);
60 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x8, 0x11);
61 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x8, 0x10);
62 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x8, 0x13);
63 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x8, 0x17);
66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x8, 0x8, 0x12);
68 //onboard intel 82551 10/100
69 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x4, 0x8, 0x11);
71 // onboard Intel 82547 1000
72 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x4, 0xa, 0x0);
73 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x5, 0xa, 0x1);
76 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|0, 0x8, 0x12);
77 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|1, 0x8, 0x13);
78 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|2, 0x8, 0x10);
79 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|3, 0x8, 0x11);
81 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|0, 0x8, 0x13);
82 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|1, 0x8, 0x10);
83 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|2, 0x8, 0x11);
84 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|3, 0x8, 0x12);
86 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|0, 0x9, 0x0);
87 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|1, 0x9, 0x1);
88 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|2, 0x9, 0x2);
89 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|3, 0x9, 0x3);
91 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|0, 0x9, 0x4);
92 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|1, 0x9, 0x5);
93 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|2, 0x9, 0x6);
94 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|3, 0x9, 0x7);
96 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
97 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x0);
98 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x1);
100 MP Config Extended Table Entries:
104 bus ID: 0 address type: I/O address
106 address range: 0x6000
109 bus ID: 0 address type: I/O address
114 bus ID: 0 address type: memory address
115 address base: 0xa0000
116 address range: 0x20000
119 bus ID: 0 address type: memory address
120 address base: 0xfc700000
121 address range: 0x2500000
124 bus ID: 0 address type: prefetch address
125 address base: 0xff600000
126 address range: 0x500000
129 bus ID: 5 bus info: 0x01 parent bus ID: 0--
130 Compatibility Bus Address
131 bus ID: 0 address modifier: add
132 predefined range: 0x00000000--
133 Compatibility Bus Address
134 bus ID: 0 address modifier: add
135 predefined range: 0x00000001 // There is no extension information...
137 /* Compute the checksums */
138 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
139 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
140 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
141 mc, smp_next_mpe_entry(mc));
142 return smp_next_mpe_entry(mc);
145 unsigned long write_smp_table(unsigned long addr)
148 v = smp_write_floating_table(addr);
149 return (unsigned long)smp_write_config_table(v);