1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
6 #if CONFIG_LOGICAL_CPUS==1
7 #include <cpu/amd/multicore.h>
10 #include <cpu/amd/amdk8_sysconf.h>
11 #include "mb_sysconf.h"
15 static void *smp_write_config_table(void *v)
17 static const char sig[4] = "PCMP";
18 static const char oem[8] = "COREBOOT";
19 static const char productid[12] = "DK8-HTX ";
20 struct mp_config_table *mc;
22 unsigned char bus_num;
24 struct mb_sysconf_t *m;
26 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
27 memset(mc, 0, sizeof(*mc));
29 memcpy(mc->mpc_signature, sig, sizeof(sig));
30 mc->mpc_length = sizeof(*mc); /* initially just the header */
32 mc->mpc_checksum = 0; /* not yet computed */
33 memcpy(mc->mpc_oem, oem, sizeof(oem));
34 memcpy(mc->mpc_productid, productid, sizeof(productid));
37 mc->mpc_entry_count = 0; /* No entries yet... */
38 mc->mpc_lapic = LAPIC_ADDR;
43 smp_write_processors(mc);
50 /* define bus and isa numbers */
51 for(bus_num = 0; bus_num < m->bus_isa; bus_num++) {
52 smp_write_bus(mc, bus_num, "PCI ");
54 smp_write_bus(mc, m->bus_isa, "ISA ");
56 /*I/O APICs: APIC ID Version State Address*/
57 smp_write_ioapic(mc, m->apicid_8111, 0x11, 0xfec00000); //8111
61 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
63 res = find_resource(dev, PCI_BASE_ADDRESS_0);
65 smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
68 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
70 res = find_resource(dev, PCI_BASE_ADDRESS_0);
72 smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
78 for(i=1; i< sysconf.hc_possible_num; i++) {
79 if(!(sysconf.pci1234[i] & 0x1) ) continue;
81 switch(sysconf.hcid[i]) {
84 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
86 res = find_resource(dev, PCI_BASE_ADDRESS_0);
88 smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
91 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
93 res = find_resource(dev, PCI_BASE_ADDRESS_0);
95 smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
105 mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_8111, 0);
108 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
111 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
114 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (6<<2)|0, m->apicid_8111, 0x12);
118 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
123 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
127 //Slot 2 PCI-X 133/100/66
129 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (2<<2)|i, m->apicid_8132_2, (2+i)%4); //30
132 //Slot 3 PCI-X 133/100/66
134 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
137 //Slot 4 PCI-X 133/100/66
139 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2<<2)|i, m->apicid_8132_1, (2+i)%4); //26
143 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (3<<2)|0, m->apicid_8132_1, 3); //27
144 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (4<<2)|0, m->apicid_8132_1, 0); //24
147 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (5<<2)|0, m->apicid_8132_1, 1); //25
151 for(i=1; i< sysconf.hc_possible_num; i++) {
152 if(!(sysconf.pci1234[i] & 0x1) ) continue;
155 struct resource *res;
156 switch(sysconf.hcid[i]) {
159 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
161 res = find_resource(dev, PCI_BASE_ADDRESS_0);
163 //Slot 1 PCI-X 133/100/66
164 for(ii=0;ii<4;ii++) {
165 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
170 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
172 res = find_resource(dev, PCI_BASE_ADDRESS_0);
174 //Slot 2 PCI-X 133/100/66
175 for(ii=0;ii<4;ii++) {
176 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
185 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
194 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
195 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
196 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
197 /* There is no extension information... */
199 /* Compute the checksums */
200 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
201 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
202 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
203 mc, smp_next_mpe_entry(mc));
204 return smp_next_mpe_entry(mc);
207 unsigned long write_smp_table(unsigned long addr)
210 v = smp_write_floating_table(addr);
211 return (unsigned long)smp_write_config_table(v);