1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
7 static void *smp_write_config_table(void *v)
9 static const char sig[4] = "PCMP";
10 static const char oem[8] = "COREBOOT";
11 static const char productid[12] = "S2850 ";
12 struct mp_config_table *mc;
13 unsigned char bus_num;
14 unsigned char bus_isa;
15 unsigned char bus_pxhd_1;
16 unsigned char bus_pxhd_2;
17 unsigned char bus_pxhd_3;
18 unsigned char bus_pxhd_4;
19 unsigned char bus_ich5r_1;
21 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
22 memset(mc, 0, sizeof(*mc));
24 memcpy(mc->mpc_signature, sig, sizeof(sig));
25 mc->mpc_length = sizeof(*mc); /* initially just the header */
27 mc->mpc_checksum = 0; /* not yet computed */
28 memcpy(mc->mpc_oem, oem, sizeof(oem));
29 memcpy(mc->mpc_productid, productid, sizeof(productid));
32 mc->mpc_entry_count = 0; /* No entries yet... */
33 mc->mpc_lapic = LAPIC_ADDR;
38 smp_write_processors(mc);
44 dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
46 bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
47 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
51 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
57 dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
59 bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
63 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.0, using defaults\n");
68 dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
70 bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
74 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.2, using defaults\n");
80 dev = dev_find_slot(0, PCI_DEVFN(0x4,0));
82 bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
86 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0, using defaults\n");
91 dev = dev_find_slot(0, PCI_DEVFN(0x06,0));
93 bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
97 printk(BIOS_DEBUG, "ERROR - could not find PCI 0:06.0, using defaults\n");
104 /* define bus and isa numbers */
105 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
106 smp_write_bus(mc, bus_num, "PCI ");
108 smp_write_bus(mc, bus_isa, "ISA ");
110 /* IOAPIC handling */
112 smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
114 struct resource *res;
117 dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
119 res = find_resource(dev, PCI_BASE_ADDRESS_0);
121 smp_write_ioapic(mc, 0x03, 0x20, res->base);
125 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
128 dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
130 res = find_resource(dev, PCI_BASE_ADDRESS_0);
132 smp_write_ioapic(mc, 0x04, 0x20, res->base);
136 printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
140 mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
142 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
143 0x00, 0x74, 0x02, 0x10);
144 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
145 0x00, 0x76, 0x02, 0x12);
146 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
147 0x00, 0x77, 0x02, 0x17);
148 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
149 0x00, 0x75, 0x02, 0x13);
150 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
151 0x00, 0x74, 0x02, 0x10);
152 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
153 0x00, 0x7c, 0x02, 0x12);
154 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
155 0x00, 0x7d, 0x02, 0x11);
156 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
157 bus_pxhd_1, 0x08, 0x03, 0x00);
158 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
159 bus_pxhd_1, 0x0c, 0x03, 0x06);
160 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
161 bus_pxhd_1, 0x0d, 0x03, 0x07);
162 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
163 bus_pxhd_2, 0x08, 0x04, 0x00);
164 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
165 bus_ich5r_1, 0x04, 0x02, 0x10);
166 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
167 bus_pxhd_4, 0x00, 0x02, 0x10);
169 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
170 (bus_isa - 1), 0x04, 0x02, 0x10);
172 /* Standard local interrupt assignments */
174 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
175 bus_isa, 0x00, MP_APIC_ALL, 0x00);
177 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
178 bus_isa, 0x00, MP_APIC_ALL, 0x01);
180 /* There is no extension information... */
182 /* Compute the checksums */
183 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
185 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
186 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
187 mc, smp_next_mpe_entry(mc));
188 return smp_next_mpe_entry(mc);
191 unsigned long write_smp_table(unsigned long addr)
194 v = smp_write_floating_table(addr);
195 return (unsigned long)smp_write_config_table(v);