f612a6a2dfd730cfa0fb13a40bbeb67ba6851a7d
[coreboot.git] / src / southbridge / amd / sb700 / sb700_lpc.c
1 /*
2  * This file is part of the coreboot project.
3  *
4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; version 2 of the License.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
18  */
19
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
23 #include <device/pnp.h>
24 #include <device/pci_ids.h>
25 #include <device/pci_ops.h>
26 #include <pc80/mc146818rtc.h>
27 #include <pc80/isa-dma.h>
28 #include <bitops.h>
29 #include <arch/io.h>
30 #include "sb700.h"
31
32 static void lpc_init(device_t dev)
33 {
34         u8 byte;
35         u32 dword;
36         device_t sm_dev;
37
38         /* Enable the LPC Controller */
39         sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
40         dword = pci_read_config32(sm_dev, 0x64);
41         dword |= 1 << 20;
42         pci_write_config32(sm_dev, 0x64, dword);
43
44         /* Initialize isa dma */
45 #if CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
46         printk(BIOS_DEBUG, "Skipping isa_dma_init() to avoid getting stuck.\n");
47 #else
48         isa_dma_init();
49 #endif
50
51         /* Enable DMA transaction on the LPC bus */
52         byte = pci_read_config8(dev, 0x40);
53         byte |= (1 << 2);
54         pci_write_config8(dev, 0x40, byte);
55
56         /* Disable the timeout mechanism on LPC */
57         byte = pci_read_config8(dev, 0x48);
58         byte &= ~(1 << 7);
59         pci_write_config8(dev, 0x48, byte);
60
61         /* Disable LPC MSI Capability */
62         byte = pci_read_config8(dev, 0x78);
63         byte &= ~(1 << 1);
64         pci_write_config8(dev, 0x78, byte);
65 }
66
67 static void sb700_lpc_read_resources(device_t dev)
68 {
69         struct resource *res;
70
71         /* Get the normal pci resources of this device */
72         pci_dev_read_resources(dev);    /* We got one for APIC, or one more for TRAP */
73
74         pci_get_resource(dev, 0xA0); /* SPI ROM base address */
75
76         /* Add an extra subtractive resource for both memory and I/O. */
77         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
78         res->base = 0;
79         res->size = 0x1000;
80         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
81                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
82
83         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
84         res->base = 0xff800000;
85         res->size = 0x00800000; /* 8 MB for flash */
86         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
87                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
88
89         res = new_resource(dev, 3); /* IOAPIC */
90         res->base = 0xfec00000;
91         res->size = 0x00001000;
92         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
93
94         compact_resources(dev);
95 }
96
97 static void sb700_lpc_set_resources(struct device *dev)
98 {
99         struct resource *res;
100
101         pci_dev_set_resources(dev);
102
103         /* Specical case. SPI Base Address. The SpiRomEnable should be set. */
104         res = find_resource(dev, 0xA0);
105         pci_write_config32(dev, 0xA0, res->base | 1 << 1);
106 }
107
108 /**
109  * @brief Enable resources for children devices
110  *
111  * @param dev the device whose children's resources are to be enabled
112  *
113  */
114 static void sb700_lpc_enable_childrens_resources(device_t dev)
115 {
116         struct bus *link;
117         u32 reg, reg_x;
118         int var_num = 0;
119         u16 reg_var[3];
120
121         reg = pci_read_config32(dev, 0x44);
122         reg_x = pci_read_config32(dev, 0x48);
123
124         for (link = dev->link_list; link; link = link->next) {
125                 device_t child;
126                 for (child = link->children; child;
127                      child = child->sibling) {
128                         if (child->enabled
129                             && (child->path.type == DEVICE_PATH_PNP)) {
130                                 struct resource *res;
131                                 for (res = child->resource_list; res; res = res->next) {
132                                         u32 base, end;  /*  don't need long long */
133                                         if (!(res->flags & IORESOURCE_IO))
134                                                 continue;
135                                         base = res->base;
136                                         end = resource_end(res);
137                                         printk(BIOS_DEBUG, "sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n",
138                                              dev_path(child), base, end);
139                                         switch (base) {
140                                         case 0x60:      /*  KB */
141                                         case 0x64:      /*  MS */
142                                                 reg |= (1 << 29);
143                                                 break;
144                                         case 0x3f8:     /*  COM1 */
145                                                 reg |= (1 << 6);
146                                                 break;
147                                         case 0x2f8:     /*  COM2 */
148                                                 reg |= (1 << 7);
149                                                 break;
150                                         case 0x378:     /*  Parallal 1 */
151                                                 reg |= (1 << 0);
152                                                 break;
153                                         case 0x3f0:     /*  FD0 */
154                                                 reg |= (1 << 26);
155                                                 break;
156                                         case 0x220:     /*  Aduio 0 */
157                                                 reg |= (1 << 8);
158                                                 break;
159                                         case 0x300:     /*  Midi 0 */
160                                                 reg |= (1 << 18);
161                                                 break;
162                                         case 0x400:
163                                                 reg_x |= (1 << 16);
164                                                 break;
165                                         case 0x480:
166                                                 reg_x |= (1 << 17);
167                                                 break;
168                                         case 0x500:
169                                                 reg_x |= (1 << 18);
170                                                 break;
171                                         case 0x580:
172                                                 reg_x |= (1 << 19);
173                                                 break;
174                                         case 0x4700:
175                                                 reg_x |= (1 << 22);
176                                                 break;
177                                         case 0xfd60:
178                                                 reg_x |= (1 << 23);
179                                                 break;
180                                         default:
181                                                 if (var_num >= 3)
182                                                         continue;       /* only 3 var ; compact them ? */
183                                                 switch (var_num) {
184                                                 case 0:
185                                                         reg_x |= (1 << 2);
186                                                         break;
187                                                 case 1:
188                                                         reg_x |= (1 << 24);
189                                                         break;
190                                                 case 2:
191                                                         reg_x |= (1 << 25);
192                                                         break;
193                                                 }
194                                                 reg_var[var_num++] =
195                                                     base & 0xffff;
196                                         }
197                                 }
198                         }
199                 }
200         }
201         pci_write_config32(dev, 0x44, reg);
202         pci_write_config32(dev, 0x48, reg_x);
203         /* Set WideIO for as many IOs found (fall through is on purpose) */
204         switch (var_num) {
205         case 2:
206                 pci_write_config16(dev, 0x90, reg_var[2]);
207         case 1:
208                 pci_write_config16(dev, 0x66, reg_var[1]);
209         case 0:
210                 pci_write_config16(dev, 0x64, reg_var[0]);
211                 break;
212         }
213 }
214
215 static void sb700_lpc_enable_resources(device_t dev)
216 {
217         pci_dev_enable_resources(dev);
218         sb700_lpc_enable_childrens_resources(dev);
219 }
220
221 static struct pci_operations lops_pci = {
222         .set_subsystem = pci_dev_set_subsystem,
223 };
224
225 static struct device_operations lpc_ops = {
226         .read_resources = sb700_lpc_read_resources,
227         .set_resources = sb700_lpc_set_resources,
228         .enable_resources = sb700_lpc_enable_resources,
229         .init = lpc_init,
230         .scan_bus = scan_static_bus,
231         .ops_pci = &lops_pci,
232 };
233 static const struct pci_driver lpc_driver __pci_driver = {
234         .ops = &lpc_ops,
235         .vendor = PCI_VENDOR_ID_ATI,
236         .device = PCI_DEVICE_ID_ATI_SB700_LPC,
237 };