2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
23 #include <device/pnp.h>
24 #include <device/pci_ids.h>
25 #include <device/pci_ops.h>
26 #include <pc80/mc146818rtc.h>
27 #include <pc80/isa-dma.h>
32 static void lpc_init(device_t dev)
38 /* Enable the LPC Controller */
39 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
40 dword = pci_read_config32(sm_dev, 0x64);
42 pci_write_config32(sm_dev, 0x64, dword);
44 /* Initialize isa dma */
45 #if CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
46 printk(BIOS_DEBUG, "Skipping isa_dma_init() to avoid getting stuck.\n");
51 /* Enable DMA transaction on the LPC bus */
52 byte = pci_read_config8(dev, 0x40);
54 pci_write_config8(dev, 0x40, byte);
56 /* Disable the timeout mechanism on LPC */
57 byte = pci_read_config8(dev, 0x48);
59 pci_write_config8(dev, 0x48, byte);
61 /* Disable LPC MSI Capability */
62 byte = pci_read_config8(dev, 0x78);
64 pci_write_config8(dev, 0x78, byte);
67 static void sb700_lpc_read_resources(device_t dev)
71 /* Get the normal pci resources of this device */
72 pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
74 pci_get_resource(dev, 0xA0); /* SPI ROM base address */
76 /* Add an extra subtractive resource for both memory and I/O. */
77 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
80 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
81 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
83 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
84 res->base = 0xff800000;
85 res->size = 0x00800000; /* 8 MB for flash */
86 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
87 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
89 res = new_resource(dev, 3); /* IOAPIC */
90 res->base = 0xfec00000;
91 res->size = 0x00001000;
92 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
94 compact_resources(dev);
97 static void sb700_lpc_set_resources(struct device *dev)
101 pci_dev_set_resources(dev);
103 /* Specical case. SPI Base Address. The SpiRomEnable should be set. */
104 res = find_resource(dev, 0xA0);
105 pci_write_config32(dev, 0xA0, res->base | 1 << 1);
109 * @brief Enable resources for children devices
111 * @param dev the device whose children's resources are to be enabled
114 static void sb700_lpc_enable_childrens_resources(device_t dev)
121 reg = pci_read_config32(dev, 0x44);
122 reg_x = pci_read_config32(dev, 0x48);
124 for (link = dev->link_list; link; link = link->next) {
126 for (child = link->children; child;
127 child = child->sibling) {
129 && (child->path.type == DEVICE_PATH_PNP)) {
130 struct resource *res;
131 for (res = child->resource_list; res; res = res->next) {
132 u32 base, end; /* don't need long long */
133 if (!(res->flags & IORESOURCE_IO))
136 end = resource_end(res);
137 printk(BIOS_DEBUG, "sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n",
138 dev_path(child), base, end);
144 case 0x3f8: /* COM1 */
147 case 0x2f8: /* COM2 */
150 case 0x378: /* Parallal 1 */
153 case 0x3f0: /* FD0 */
156 case 0x220: /* Aduio 0 */
159 case 0x300: /* Midi 0 */
182 continue; /* only 3 var ; compact them ? */
201 pci_write_config32(dev, 0x44, reg);
202 pci_write_config32(dev, 0x48, reg_x);
203 /* Set WideIO for as many IOs found (fall through is on purpose) */
206 pci_write_config16(dev, 0x90, reg_var[2]);
208 pci_write_config16(dev, 0x66, reg_var[1]);
210 pci_write_config16(dev, 0x64, reg_var[0]);
215 static void sb700_lpc_enable_resources(device_t dev)
217 pci_dev_enable_resources(dev);
218 sb700_lpc_enable_childrens_resources(dev);
221 static struct pci_operations lops_pci = {
222 .set_subsystem = pci_dev_set_subsystem,
225 static struct device_operations lpc_ops = {
226 .read_resources = sb700_lpc_read_resources,
227 .set_resources = sb700_lpc_set_resources,
228 .enable_resources = sb700_lpc_enable_resources,
230 .scan_bus = scan_static_bus,
231 .ops_pci = &lops_pci,
233 static const struct pci_driver lpc_driver __pci_driver = {
235 .vendor = PCI_VENDOR_ID_ATI,
236 .device = PCI_DEVICE_ID_ATI_SB700_LPC,