2 * This file is part of the coreboot project.
4 * Copyright (C) 2009 One Laptop per Child, Association, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <device/device.h>
25 static inline void vx800_noop(device_t dev)
31 /* vx800_early_smbus.c */
32 struct mem_controller;
33 void enable_smbus(void);
34 void smbus_fixup(const struct mem_controller *mem_ctrl);
36 /* vx800_early_serial.c */
37 void enable_vx800_serial(void);
50 #define SR_INDEX 0x3c4
52 #define CRTM_INDEX 0x3b4
53 #define CRTM_DATA 0x3b5
54 #define CRTC_INDEX 0x3d4
55 #define CRTC_DATA 0x3d5
57 /* Memory Controller Registers */
58 #define RANK0_END 0x40
59 #define RANK1_END 0x41
60 #define RANK2_END 0x42
61 #define RANK3_END 0x43
62 #define RANK0_START 0x48
63 #define RANK1_START 0x49
64 #define RANK2_START 0x4a
65 #define RANK3_START 0x4b
66 #define DDR_PAGE_CTL 0x69
67 #define DRAM_REFRESH_COUNTER 0x6a
68 #define DRAM_MISC_CTL 0x6b
69 #define CH_A_DQS_OUTPUT_DELAY 0x70
70 #define CH_A_MD_OUTPUT_DELAY 0x71
72 /* RAM Init Commands */
73 #define RAM_COMMAND_NORMAL 0x0
74 #define RAM_COMMAND_NOP 0x1
75 #define RAM_COMMAND_PRECHARGE 0x2
76 #define RAM_COMMAND_MRS 0x3
77 #define RAM_COMMAND_CBR 0x4
79 /* IDE specific bits */
80 #define IDE_MODE_REG 0x09
81 #define IDE0_NATIVE_MODE (1 << 0)
82 #define IDE1_NATIVE_MODE (1 << 2)
84 /* These are default addresses according to Via */
85 #define IDE0_DATA_ADDR 0x1f0
86 #define IDE0_CONTROL_ADDR 0x3f4
87 #define IDE1_DATA_ADDR 0x170
88 #define IDE1_CONTROL_ADDR 0x370
90 /* By Award default, Via default is 0xCC0 */
91 #define BUS_MASTER_ADDR 0xfe00
93 #define CHANNEL_ENABLE_REG 0x40
94 #define ENABLE_IDE0 (1 << 0)
95 #define ENABLE_IDE1 (1 << 1)
97 #define VX800_ACPI_IO_BASE 0x0400
99 #define NB_APIC_REG 0,0,5,
100 #define NB_PXPTRF_REG NB_APIC_REG
101 #define NB_MSGC_REG NB_APIC_REG
102 #define NB_HOST_REG 0,0,2,
103 #define NB_P6IF_REG NB_HOST_REG
105 #define NB_DRAMC_REG 0,0,3,
106 #define NB_PMU_REG 0,0,4,
107 #define NB_VLINK_REG 0,0,7,
108 #define NB_PEG_BRIDGE_REG 0,2, 0,
109 #define NB_D3F0_REG 0,3, 0,
110 #define NB_D3F1_REG 0,3, 1,
112 #define SB_LPC_REG 0,0x11,0,
113 #define SB_VLINK_REG 0,0x11,7,
114 #define SB_SATA_REG 0,0xf, 0,
115 #define SB_IDEC_REG 0,0xf, 0,
116 #define SB_P2PB_REG 0,0x13, 0,
117 #define SB_USB0_REG 0,0x10, 0,
118 #define SB_USB1_REG 0,0x10, 1,
119 #define SB_USB2_REG 0,0x10, 2,
120 #define SB_EHCI_REG 0,0x10, 4,
122 #define VX800SB_APIC_ID 0x4
123 #define VX800SB_APIC_BASE 0xfec00000ULL
124 #define VX800SB_APIC_DATA_OFFSET 0x10
125 #define VX800SB_APIC_ENTRY_NUMBER 0x40
127 #define VX800_D0F5_MMCONFIG_MBAR 0x61