remove trailing whitespace

Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/364
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

diff --git a/src/arch/x86/include/arch/romcc_io.h b/src/arch/x86/include/arch/romcc_io.h
index 79ea26550e62be77f569a081e1c9bdcfad0e264a..b0c8f65f465a57b8bed08d2cba17d981989d3cc5 100644 (file)
--- a/src/arch/x86/include/arch/romcc_io.h
+++ b/src/arch/x86/include/arch/romcc_io.h
@@ -3,7 +3,7 @@
 
 #include <stdint.h>
 
 
 #include <stdint.h>
 

-// arch/io.h is pulled in in many places but it could 
+// arch/io.h is pulled in in many places but it could

 // also be pulled in here for all romcc/romstage code.
 // #include <arch/io.h>
 
 // also be pulled in here for all romcc/romstage code.
 // #include <arch/io.h>
 

diff --git a/src/console/die.c b/src/console/die.c
index 8c97f89b27a9ab8f37037b56abcd25b79b9bc95e..395ab7553858cce26cec30247bcbf5103f1e470f 100644 (file)
--- a/src/console/die.c
+++ b/src/console/die.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
 /*
  * This file is part of the coreboot project.

- * 
+ *

  * Copyright (C) 2003 Eric Biederman
  *
  * This program is free software; you can redistribute it and/or
  * Copyright (C) 2003 Eric Biederman
  *
  * This program is free software; you can redistribute it and/or

diff --git a/src/console/post.c b/src/console/post.c
index 7fc9d6fc6ee9344c3cbedf49057ae809d0481612..08336a28e93cbd1f976739a754823d1e9b63bff3 100644 (file)
--- a/src/console/post.c
+++ b/src/console/post.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
 /*
  * This file is part of the coreboot project.

- * 
+ *

  * Copyright (C) 2003 Eric Biederman
  *
  * This program is free software; you can redistribute it and/or
  * Copyright (C) 2003 Eric Biederman
  *
  * This program is free software; you can redistribute it and/or

diff --git a/src/cpu/amd/agesa/apic_timer.c b/src/cpu/amd/agesa/apic_timer.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/cpu/amd/agesa/family10/chip.h b/src/cpu/amd/agesa/family10/chip.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/cpu/amd/agesa/family10/chip_name.c b/src/cpu/amd/agesa/family10/chip_name.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/cpu/amd/agesa/family12/chip.h b/src/cpu/amd/agesa/family12/chip.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/cpu/amd/agesa/family12/chip_name.c b/src/cpu/amd/agesa/family12/chip_name.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
index 90b83e5bf9c372f2754afad55f436e40b0b64a1a..6df1032d98e78b0880f340b05b0dc3fb0338f770 100644 (file)
--- a/src/cpu/amd/model_10xxx/defaults.h
+++ b/src/cpu/amd/model_10xxx/defaults.h
@@ -91,7 +91,7 @@ static const struct {
 
        { BU_CFG2, AMD_DRBH_Cx, AMD_PTYPE_ALL,
          0x00000000, 1 << (35-32),
 
        { BU_CFG2, AMD_DRBH_Cx, AMD_PTYPE_ALL,
          0x00000000, 1 << (35-32),

-         0x00000000, 1 << (35-32) },   /* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() )  */  
+         0x00000000, 1 << (35-32) },   /* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() )  */

 
        { OSVW_ID_Length, AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL,
          0x00000004, 0x00000000,
 
        { OSVW_ID_Length, AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL,
          0x00000004, 0x00000000,

diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
index 6cbd096f673249860b465729596e9b1683895c90..6be054c87f2157144a5a3a5202708f836437bc72 100644 (file)
--- a/src/cpu/amd/model_10xxx/fidvid.c
+++ b/src/cpu/amd/model_10xxx/fidvid.c
@@ -17,84 +17,84 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 /*
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 /*

- * This file initializes the CPU cores for voltage and frequency settings 
+ * This file initializes the CPU cores for voltage and frequency settings

  * in the different power states.
  */
 /*
 
 checklist (functions are in this file if no source file named)
  * in the different power states.
  */
 /*
 
 checklist (functions are in this file if no source file named)

-Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010 
+Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010

 
 2.4.2.6 Requirements for p-states
 
 1.- F3x[84:80] According to table 100 : prep_fid_change
 
 
 2.4.2.6 Requirements for p-states
 
 1.- F3x[84:80] According to table 100 : prep_fid_change
 

-2.- COF/VID : 
-     2.4.2.9.1 Steps 1,3-6 and warning for 2,7 if they apply 
-               fixPsNbVidBeforeWR(...) 
+2.- COF/VID :
+     2.4.2.9.1 Steps 1,3-6 and warning for 2,7 if they apply
+               fixPsNbVidBeforeWR(...)

      2.4.2.9.1 Step 8 enable_fid_change
      2.4.2.9.1 Step 8 enable_fid_change

-               We do this for all nodes, I don't understand BKDG 100% on 
-               whether this is or isn't meant by "on the local 
+               We do this for all nodes, I don't understand BKDG 100% on
+               whether this is or isn't meant by "on the local

                processor". Must be OK.
      2.4.2.9.1 Steps 9-10 (repeat 1-7 and reset) romstage.c/init_cpus ?
      2.4.2.9.1 Steps 11-12 init_fidvid_stage2
                processor". Must be OK.
      2.4.2.9.1 Steps 9-10 (repeat 1-7 and reset) romstage.c/init_cpus ?
      2.4.2.9.1 Steps 11-12 init_fidvid_stage2

-     2.4.2.9.2 DualPlane PVI : Not supported, don't know how to detect, 
-               needs specific circuitry. 
+     2.4.2.9.2 DualPlane PVI : Not supported, don't know how to detect,
+               needs specific circuitry.

 
 3.-  2.4.2.7 dualPlaneOnly(dev)
 
 4.-  2.4.2.8 applyBoostFIDOffset(dev)
 
 
 3.-  2.4.2.7 dualPlaneOnly(dev)
 
 4.-  2.4.2.8 applyBoostFIDOffset(dev)
 

-5.-  enableNbPState1(dev) 
+5.-  enableNbPState1(dev)

 
 

-6.- 2.4.1.7 
+6.- 2.4.1.7

     a) UpdateSinglePlaneNbVid()
     b) setVSRamp(), called from  prep_fid_change
     c) prep_fid_change
     a) UpdateSinglePlaneNbVid()
     b) setVSRamp(), called from  prep_fid_change
     c) prep_fid_change

-    d) improperly, for lack of voltage regulator details?, 
-        F3xA0[PsiVidEn] in defaults.h 
+    d) improperly, for lack of voltage regulator details?,
+        F3xA0[PsiVidEn] in defaults.h

         F3xA0[PsiVid] in init_cpus.c AMD_SetupPSIVID_d (before prep_fid_change)
 
         F3xA0[PsiVid] in init_cpus.c AMD_SetupPSIVID_d (before prep_fid_change)
 

-7.- TODO (Core Performance Boost is only available in revision E cpus, and we 
-          don't seem to support those yet, at least they don't have any 
+7.- TODO (Core Performance Boost is only available in revision E cpus, and we
+          don't seem to support those yet, at least they don't have any

           constant in amddefs.h )
 
           constant in amddefs.h )
 

-8.- FIXME ? Transition to min Pstate according to 2.4.2.15.3 is required 
-    by 2.4.2.6 after warm reset. But 2.4.2.15 states that it is not required 
-    if the warm reset is issued by coreboot to update NbFid. So it is required 
-    or not ? How can I tell who issued warm reset ? 
-    Coreboot transitions to P0 instead, which is not recommended, and does 
+8.- FIXME ? Transition to min Pstate according to 2.4.2.15.3 is required
+    by 2.4.2.6 after warm reset. But 2.4.2.15 states that it is not required
+    if the warm reset is issued by coreboot to update NbFid. So it is required
+    or not ? How can I tell who issued warm reset ?
+    Coreboot transitions to P0 instead, which is not recommended, and does

     not follow 2.4.2.15.2 to do so.
 
     not follow 2.4.2.15.2 to do so.
 

-9.- TODO Requires information on current delivery capability 
-    (depends on mainboard and maybe power supply ?). One might use a config 
+9.- TODO Requires information on current delivery capability
+    (depends on mainboard and maybe power supply ?). One might use a config

     option with the maximum number of Ampers that the board can deliver to CPU.
 
 10.- [Multiprocessor] TODO 2.4.2.12
     option with the maximum number of Ampers that the board can deliver to CPU.
 
 10.- [Multiprocessor] TODO 2.4.2.12

-     [Uniprocessor] FIXME ? We call setPStateMaxVal() in init_fidvid_stage2, 
-     but not sure this is what is meant by "Determine the valid set of 
-     P-states based on enabled P-states indicated 
+     [Uniprocessor] FIXME ? We call setPStateMaxVal() in init_fidvid_stage2,
+     but not sure this is what is meant by "Determine the valid set of
+     P-states based on enabled P-states indicated

      in MSRC001_00[68:64][PstateEn]" in 2.4.2.6-10
 
 11.- finalPstateChange() from init_fidvid_Stage2 (BKDG says just "may", anyway)
 
      in MSRC001_00[68:64][PstateEn]" in 2.4.2.6-10
 
 11.- finalPstateChange() from init_fidvid_Stage2 (BKDG says just "may", anyway)
 

-12.- generate ACPI for p-states. FIXME 
+12.- generate ACPI for p-states. FIXME

      Needs more assesment. There's some kind of fixed support that
      does not seem to depend on CPU revision or actual MSRC001_00[68:64]
      Needs more assesment. There's some kind of fixed support that
      does not seem to depend on CPU revision or actual MSRC001_00[68:64]

-     as BKDG apparently requires. 
+     as BKDG apparently requires.

      http://www.coreboot.org/ACPI#CPU_Power_Management
      At least for Tilapia board:
      src/mainboard/<vendor>/<model>/acpi_tables.c  write_acpi_tables(...) calls
      http://www.coreboot.org/ACPI#CPU_Power_Management
      At least for Tilapia board:
      src/mainboard/<vendor>/<model>/acpi_tables.c  write_acpi_tables(...) calls

-      acpi_add_ssdt_pstates(...) 
+      acpi_add_ssdt_pstates(...)

      in /src/northbridge/amd/amdfam10/amdfam10_acpi.c
      which apparently copies them from static info in
      in /src/northbridge/amd/amdfam10/amdfam10_acpi.c
      which apparently copies them from static info in

-     src/mainboard/<vendor>/<model>/acpi/cpstate.asl 
-     
+     src/mainboard/<vendor>/<model>/acpi/cpstate.asl
+

 "must also be completed"
 
 a.-  PllLockTime set in ruleset in defaults.h
 "must also be completed"
 
 a.-  PllLockTime set in ruleset in defaults.h

-     BKDG says set it "If MSRC001_00[68:64][CpuFid] is different between 
-     any two enabled P-states", but since it does not say "only if" 
+     BKDG says set it "If MSRC001_00[68:64][CpuFid] is different between
+     any two enabled P-states", but since it does not say "only if"

      I guess it is safe to do it always.
 
 b.-  prep_fid_change(...)
      I guess it is safe to do it always.
 
 b.-  prep_fid_change(...)

diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index ce5c810821886ad76138689e3aa12e40f40b74f3..ae5429d05d7493005da77730f771ad734fb82e5a 100644 (file)
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -265,7 +265,7 @@ static void init_ecc_memory(unsigned node_id)
 
        /* See if we scrubbing should be enabled */
        enable_scrubbing = 1;
 
        /* See if we scrubbing should be enabled */
        enable_scrubbing = 1;

-       if( get_option(&enable_scrubbing, "hw_scrubber") < 0 ) 
+       if( get_option(&enable_scrubbing, "hw_scrubber") < 0 )

        {
                enable_scrubbing = CONFIG_HW_SCRUBBER;
        }
        {
                enable_scrubbing = CONFIG_HW_SCRUBBER;
        }


@@ -443,7 +443,7 @@ static inline void k8_errata(void)
 #endif
        {
                msr = rdmsr(NB_CFG_MSR);
 #endif
        {
                msr = rdmsr(NB_CFG_MSR);

-               
+

 #if CONFIG_K8_REV_F_SUPPORT == 0
                if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
                        /* D0 later don't need it */
 #if CONFIG_K8_REV_F_SUPPORT == 0
                if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
                        /* D0 later don't need it */


@@ -461,11 +461,11 @@ static inline void k8_errata(void)
                 */
                msr.lo |= 1 << 3;
                /* Erratum 169 */
                 */
                msr.lo |= 1 << 3;
                /* Erratum 169 */

-               /* This supersedes erratum 131; 131 should not be applied with 169 
+               /* This supersedes erratum 131; 131 should not be applied with 169

                 * We also need to set some bits in the northbridge, handled in src/northbridge/amdk8/
                 */
                msr.hi |= 1;
                 * We also need to set some bits in the northbridge, handled in src/northbridge/amdk8/
                 */
                msr.hi |= 1;

-               
+

                wrmsr(NB_CFG_MSR, msr);
        }
        /* Erratum 122 */
                wrmsr(NB_CFG_MSR, msr);
        }
        /* Erratum 122 */

diff --git a/src/cpu/amd/model_gx2/cpubug.c b/src/cpu/amd/model_gx2/cpubug.c
index ff61a30f9aee80aa35dde5c4abf52d60e0415269..473766c8a4109d7653a9fb883d897031210ce459 100644 (file)
--- a/src/cpu/amd/model_gx2/cpubug.c
+++ b/src/cpu/amd/model_gx2/cpubug.c
@@ -280,7 +280,7 @@ static void bug118339(void)
 
        /* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled
         * As per Todd Roberts in PBz1094 and PBz1095
 
        /* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled
         * As per Todd Roberts in PBz1094 and PBz1095

-        * Moved from CPUREG to CPUBUG per Tom Sylla 
+        * Moved from CPUREG to CPUBUG per Tom Sylla

         */
        msrnum =  0x04C000042;          /*  GLCP SETMCTL Register */
        msr = rdmsr(msrnum);
         */
        msrnum =  0x04C000042;          /*  GLCP SETMCTL Register */
        msr = rdmsr(msrnum);

diff --git a/src/cpu/amd/model_lx/cpureginit.c b/src/cpu/amd/model_lx/cpureginit.c
index 6e7de84c6abec3bf848ab5954253b563c6b83972..bad98b51bfa44834be8f59c02c4bf48ceb02d1b9 100644 (file)
--- a/src/cpu/amd/model_lx/cpureginit.c
+++ b/src/cpu/amd/model_lx/cpureginit.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
 /*
  * This file is part of the coreboot project.

- * 
+ *

  * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee>
  * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com>
  * Copyright (C) 2007 Advanced Micro Devices, Inc.
  * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee>
  * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com>
  * Copyright (C) 2007 Advanced Micro Devices, Inc.


@@ -83,7 +83,7 @@ static const struct delay_controls {
  * hardware is not an exact science. And, finally, if an FS2 (JTAG debugger)
  * is hooked up, then just don't do anything. This code was written by a master
  * of the Dark Arts at AMD and should not be modified in any way.
  * hardware is not an exact science. And, finally, if an FS2 (JTAG debugger)
  * is hooked up, then just don't do anything. This code was written by a master
  * of the Dark Arts at AMD and should not be modified in any way.

- * 
+ *

  * [1] (http://www.thefreedictionary.com/juju)
  *
  * @param dimm0 The SMBus address of DIMM 0 (mainboard dependent).
  * [1] (http://www.thefreedictionary.com/juju)
  *
  * @param dimm0 The SMBus address of DIMM 0 (mainboard dependent).

diff --git a/src/cpu/amd/model_lx/msrinit.c b/src/cpu/amd/model_lx/msrinit.c
index 6569338a2f63ee7ff7885fdc5d975323e42c35ad..9c6e98e14c598cd682e274c733cacce143bd3556 100644 (file)
--- a/src/cpu/amd/model_lx/msrinit.c
+++ b/src/cpu/amd/model_lx/msrinit.c
@@ -45,7 +45,7 @@ static const msrinit_t msr_table[] =
         * of this extended memory will be to host the coreboot_ram stage at RAMBASE,
         * currently 1Mb.
         * These registers will be set to their correct value by the Northbridge init code.
         * of this extended memory will be to host the coreboot_ram stage at RAMBASE,
         * currently 1Mb.
         * These registers will be set to their correct value by the Northbridge init code.

-        * 
+        *

         * WARNING: if coreboot_ram could not be loaded, these registers are probably
         * incorrectly set here. You may comment the following two lines and set RAMBASE
         * to 0x4000 to revert to the previous behavior for LX-boards.
         * WARNING: if coreboot_ram could not be loaded, these registers are probably
         * incorrectly set here. You may comment the following two lines and set RAMBASE
         * to 0x4000 to revert to the previous behavior for LX-boards.

diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/devices/oprom/x86.c b/src/devices/oprom/x86.c
index 4d7357c93a7280a27afac755d45e6781818b9894..0c15b1560c538a485e3b44952e099eeb6f41e4f1 100644 (file)
--- a/src/devices/oprom/x86.c
+++ b/src/devices/oprom/x86.c
@@ -36,7 +36,7 @@ void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx,
                u32 esi, u32 edi) __attribute__((regparm(0))) =
                                                (void *)&__realmode_call;
 
                u32 esi, u32 edi) __attribute__((regparm(0))) =
                                                (void *)&__realmode_call;
 

-void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, 
+void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx,

                u32 esi, u32 edi) __attribute__((regparm(0))) =
                                                (void *)&__realmode_interrupt;
 
                u32 esi, u32 edi) __attribute__((regparm(0))) =
                                                (void *)&__realmode_interrupt;
 


@@ -361,7 +361,7 @@ void do_vsmbios(void)
        printk(BIOS_DEBUG, "Calling VSA module...\n");
 
        /* ECX gets SMM, EDX gets SYSMEM */
        printk(BIOS_DEBUG, "Calling VSA module...\n");
 
        /* ECX gets SMM, EDX gets SYSMEM */

-       realmode_call(VSA2_ENTRY_POINT, 0x0, 0x0, MSR_GLIU0_SMM, 
+       realmode_call(VSA2_ENTRY_POINT, 0x0, 0x0, MSR_GLIU0_SMM,

                        MSR_GLIU0_SYSMEM, 0x0, 0x0);
 
        printk(BIOS_DEBUG, "... VSA module returned.\n");
                        MSR_GLIU0_SYSMEM, 0x0, 0x0);
 
        printk(BIOS_DEBUG, "... VSA module returned.\n");

diff --git a/src/devices/oprom/x86_asm.S b/src/devices/oprom/x86_asm.S
index 57c5338914b7748ebd214f7935349f8097897642..488bfa6b912e625eae5b56cc4319a053e0e78839 100644 (file)
--- a/src/devices/oprom/x86_asm.S
+++ b/src/devices/oprom/x86_asm.S
@@ -255,7 +255,7 @@ __realmode_interrupt = RELOCATED(.)
        data32 ljmp     $0, $RELOCATED(1f)
 1:
 
        data32 ljmp     $0, $RELOCATED(1f)
 1:
 

-       /* put the stack at the end of page zero.  That way we can easily 
+       /* put the stack at the end of page zero.  That way we can easily

         * share it between real mode and protected mode, because %esp and
         * %ss:%sp point to the same memory.
         */
         * share it between real mode and protected mode, because %esp and
         * %ss:%sp point to the same memory.
         */

diff --git a/src/drivers/ati/ragexl/xlinit.c b/src/drivers/ati/ragexl/xlinit.c
index 26a7caff0d7a559c08da70883c5440ff4f497b0b..747b343cc880587d44ccd120b6ae9b7d547c41d0 100644 (file)
--- a/src/drivers/ati/ragexl/xlinit.c
+++ b/src/drivers/ati/ragexl/xlinit.c
@@ -22,7 +22,7 @@
 #include <device/pci_ops.h>
 
 // FIXME BTEXT console within coreboot has been obsoleted
 #include <device/pci_ops.h>
 
 // FIXME BTEXT console within coreboot has been obsoleted

-// and will go away. The BTEXT code in this file should be 
+// and will go away. The BTEXT code in this file should be

 // fixed to export a framebuffer console through the coreboot
 // table (and possibly make it available for bootsplash use)
 // Hence do only remove this if you fix the code.
 // fixed to export a framebuffer console through the coreboot
 // table (and possibly make it available for bootsplash use)
 // Hence do only remove this if you fix the code.

diff --git a/src/drivers/dec/21143/21143.c b/src/drivers/dec/21143/21143.c
index c89d4f08de480b42b3c0577dc9aedba7fea7276e..416b5ae6d9840fc0db791c137bed66932572a9dd 100644 (file)
--- a/src/drivers/dec/21143/21143.c
+++ b/src/drivers/dec/21143/21143.c
@@ -30,7 +30,7 @@ static void dec_21143_enable(device_t dev)
 
        // The resource allocator should do this. If not, it needs to be fixed
        // differently.
 
        // The resource allocator should do this. If not, it needs to be fixed
        // differently.

-#if 0 
+#if 0

        /* Command and status configuration (offset 0x04) */
        pci_write_config32(dev, 0x04, 0x02800107);
        printk(BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n",
        /* Command and status configuration (offset 0x04) */
        pci_write_config32(dev, 0x04, 0x02800107);
        printk(BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n",

diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c
index 235c52c6549c10212175294c4a42df3b80653ba0..3480654cfe8e322f4c341e1003b1a5629a1b5c8e 100644 (file)
--- a/src/drivers/oxford/oxpcie/oxpcie_early.c
+++ b/src/drivers/oxford/oxpcie/oxpcie_early.c
@@ -29,7 +29,7 @@
                CONFIG_OXFORD_OXPCIE_BRIDGE_FUNCTION)
 
 #define OXPCIE_DEVICE \
                CONFIG_OXFORD_OXPCIE_BRIDGE_FUNCTION)
 
 #define OXPCIE_DEVICE \

-       PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0) 
+       PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0)

 
 void oxford_init(void)
 {
 
 void oxford_init(void)
 {


@@ -57,7 +57,7 @@ void oxford_init(void)
 
        /* Memory window for the OXPCIe952 card */
        // XXX is the calculation of base and limit corect?
 
        /* Memory window for the OXPCIe952 card */
        // XXX is the calculation of base and limit corect?

-       pci_write_config32(PCIE_BRIDGE, PCI_MEMORY_BASE, 
+       pci_write_config32(PCIE_BRIDGE, PCI_MEMORY_BASE,

                        ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS & 0xffff0000) |
                        ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS >> 16) & 0xff00)));
 
                        ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS & 0xffff0000) |
                        ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS >> 16) & 0xff00)));
 


@@ -66,7 +66,7 @@ void oxford_init(void)
        reg16 |= PCI_COMMAND_MEMORY;
        pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16);
 
        reg16 |= PCI_COMMAND_MEMORY;
        pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16);
 

-       // FIXME Add a timeout or this will hang forever if 
+       // FIXME Add a timeout or this will hang forever if

        // no device is in the slot.
        u32 id = 0;
        while ((id == 0) || (id == 0xffffffff))
        // no device is in the slot.
        u32 id = 0;
        while ((id == 0) || (id == 0xffffffff))

diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index f1c12b38e813bc5bb2397d98bd05d5714ed841bb..a72da69bd588c782c8314f7b24dab1816cfc9024 100644 (file)
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -12,7 +12,7 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.

- * 
+ *

  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA


@@ -20,32 +20,32 @@
 
 /**
  * @file post_codes.h
 
 /**
  * @file post_codes.h

- * 
+ *

  * This aims to be a central point for POST codes used throughout coreboot.
  * All POST codes should be declared here as macros, and post_code() should
  * be used with the macros instead of hardcoded values. This allows us to
  * quicly reference POST codes when nothing is working
  * This aims to be a central point for POST codes used throughout coreboot.
  * All POST codes should be declared here as macros, and post_code() should
  * be used with the macros instead of hardcoded values. This allows us to
  * quicly reference POST codes when nothing is working

- * 
+ *

  * The format for a POST code macro is
  * #define POST_WHAT_WE_COMMUNICATE_IS_HAPPENING_WHEN_THIS_CODE_IS_POSTED
  * Lets's keep it at POST_* instead of POST_CODE_*
  * The format for a POST code macro is
  * #define POST_WHAT_WE_COMMUNICATE_IS_HAPPENING_WHEN_THIS_CODE_IS_POSTED
  * Lets's keep it at POST_* instead of POST_CODE_*

- * 
+ *

  * This file is also included by early assembly files. Only use #define s;
  * no function prototypes allowed here
  * This file is also included by early assembly files. Only use #define s;
  * no function prototypes allowed here

- * 
+ *

  * DOCUMENTATION:
  * DOCUMENTATION:

- * Please document any and all post codes using Doxygen style comments. We 
+ * Please document any and all post codes using Doxygen style comments. We

  * want to be able to generate a verbose enough documentation that is useful
  * during debugging. Failure to do so will result in your patch being rejected
  * without any explanation or effort on part of the maintainers.
  * want to be able to generate a verbose enough documentation that is useful
  * during debugging. Failure to do so will result in your patch being rejected
  * without any explanation or effort on part of the maintainers.

- * 
+ *

  */
 #ifndef POST_CODES_H
 #define POST_CODES_H
 
 /**
  * \brief  Entry into 'crt0.s'. reset code jumps to here
  */
 #ifndef POST_CODES_H
 #define POST_CODES_H
 
 /**
  * \brief  Entry into 'crt0.s'. reset code jumps to here

- * 
+ *

  * First instruction that gets executed after the reset vector jumps.
  * This indicates that the reset vector points to the correct code segment.
  */
  * First instruction that gets executed after the reset vector jumps.
  * This indicates that the reset vector points to the correct code segment.
  */


@@ -53,7 +53,7 @@
 
 /**
  * \brief Entry into protected mode
 
 /**
  * \brief Entry into protected mode

- * 
+ *

  * Preparing to enter protected mode. This is POSTed right before changing to
  * protected mode.
  */
  * Preparing to enter protected mode. This is POSTed right before changing to
  * protected mode.
  */


@@ -61,14 +61,14 @@
 
 /**
  * \brief Start copying coreboot to RAM with decompression if compressed
 
 /**
  * \brief Start copying coreboot to RAM with decompression if compressed

- * 
+ *

  * POSTed before ramstage is about to be loaded into memory
  */
 #define POST_PREPARE_RAMSTAGE                  0x11
 
 /**
  * \brief Copy/decompression finished; jumping to RAM
  * POSTed before ramstage is about to be loaded into memory
  */
 #define POST_PREPARE_RAMSTAGE                  0x11
 
 /**
  * \brief Copy/decompression finished; jumping to RAM

- * 
+ *

  * This is called after ramstage is loaded in memory, and before
  * the code jumps there. This represents the end of romstage.
  */
  * This is called after ramstage is loaded in memory, and before
  * the code jumps there. This represents the end of romstage.
  */


@@ -77,14 +77,14 @@
 
 /**
  * \brief Entry into c_start
 
 /**
  * \brief Entry into c_start

- * 
+ *

  * c_start.S is the first code executing in ramstage.
  */
 #define POST_ENTRY_C_START                     0x13
 
 /**
  * \brief Entry into coreboot in hardwaremain (RAM)
  * c_start.S is the first code executing in ramstage.
  */
 #define POST_ENTRY_C_START                     0x13
 
 /**
  * \brief Entry into coreboot in hardwaremain (RAM)

- * 
+ *

  * This is the first call in hardwaremain.c. If this code is POSTed, then
  * ramstage has succesfully loaded and started executing.
  */
  * This is the first call in hardwaremain.c. If this code is POSTed, then
  * ramstage has succesfully loaded and started executing.
  */


@@ -92,14 +92,14 @@
 
 /**
  * \brief Console is initialized
 
 /**
  * \brief Console is initialized

- * 
+ *

  * The console is initialized and is ready for usage
  */
 #define POST_CONSOLE_READY                     0x39
 
 /**
  * \brief Console boot message succeeded
  * The console is initialized and is ready for usage
  */
 #define POST_CONSOLE_READY                     0x39
 
 /**
  * \brief Console boot message succeeded

- * 
+ *

  * First console message has been succesfully sent through the console backend
  * driver.
  */
  * First console message has been succesfully sent through the console backend
  * driver.
  */


@@ -107,28 +107,28 @@
 
 /**
  * \brief Devices have been enumerated
 
 /**
  * \brief Devices have been enumerated

- * 
+ *

  * Bus scan, and device enumeration has completed.
  */
 #define POST_DEVICE_ENUMERATION_COMPLETE       0x66
 
 /**
  * \brief Devices have been configured
  * Bus scan, and device enumeration has completed.
  */
 #define POST_DEVICE_ENUMERATION_COMPLETE       0x66
 
 /**
  * \brief Devices have been configured

- * 
+ *

  * Device confgration has completed.
  */
 #define POST_DEVICE_CONFIGURATION_COMPLETE     0x88
 
 /**
  * \brief Devices have been enabled
  * Device confgration has completed.
  */
 #define POST_DEVICE_CONFIGURATION_COMPLETE     0x88
 
 /**
  * \brief Devices have been enabled

- * 
+ *

  * Devices have been enabled.
  */
 #define POST_DEVICES_ENABLED                   0x89
 
 /**
  * \brief Entry into elf boot
  * Devices have been enabled.
  */
 #define POST_DEVICES_ENABLED                   0x89
 
 /**
  * \brief Entry into elf boot

- * 
+ *

  * This POST code is called right before invoking jmp_to_elf_entry()
  * jmp_to_elf_entry() invokes the payload, and should never return
  */
  * This POST code is called right before invoking jmp_to_elf_entry()
  * jmp_to_elf_entry() invokes the payload, and should never return
  */


@@ -136,7 +136,7 @@
 
 /**
  * \brief Jumping to payload
 
 /**
  * \brief Jumping to payload

- * 
+ *

  * Called right before jumping to a payload. If the boot sequence stops with
  * this code, chances are the payload freezes.
  */
  * Called right before jumping to a payload. If the boot sequence stops with
  * this code, chances are the payload freezes.
  */


@@ -144,16 +144,16 @@
 
 /**
  * \brief Not supposed to get here
 
 /**
  * \brief Not supposed to get here

- * 
+ *

  * A function that should not have returned, returned
  * A function that should not have returned, returned

- * 
+ *

  * Check the console output for details.
  */
 #define POST_DEAD_CODE                         0xee
 
 /**
  * \brief Pre call to hardwaremain()
  * Check the console output for details.
  */
 #define POST_DEAD_CODE                         0xee
 
 /**
  * \brief Pre call to hardwaremain()

- * 
+ *

  * POSTed right before hardwaremain is called from c_start.S
  * TODO: Change this code to a lower number
  */
  * POSTed right before hardwaremain is called from c_start.S
  * TODO: Change this code to a lower number
  */


@@ -161,9 +161,9 @@
 
 /**
  * \brief Elfload fail or die() called
 
 /**
  * \brief Elfload fail or die() called

- * 
+ *

  * Coreboot was not able to load the payload, no payload was detected
  * Coreboot was not able to load the payload, no payload was detected

- * or die() was called. 
+ * or die() was called.

  * \n
  * If this code appears before entering ramstage, then most likely
  * ramstage is corrupted, and reflashing of the ROM chip is needed.
  * \n
  * If this code appears before entering ramstage, then most likely
  * ramstage is corrupted, and reflashing of the ROM chip is needed.


@@ -182,7 +182,7 @@
  * They overlap with previous codes, and most are not even used
  * Some maiboards still require them, but they are deprecated. We want to consolidate
  * our own POST code structure with the codes above.
  * They overlap with previous codes, and most are not even used
  * Some maiboards still require them, but they are deprecated. We want to consolidate
  * our own POST code structure with the codes above.

- * 
+ *

  * standard AMD post definitions for the AMD Geode
  */
 #define POST_Output_Port                       (0x080) /*      port to write post codes to*/
  * standard AMD post definitions for the AMD Geode
  */
 #define POST_Output_Port                       (0x080) /*      port to write post codes to*/

diff --git a/src/include/cpu/amd/amdfam12.h b/src/include/cpu/amd/amdfam12.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h
index a473d66c8fa96e2e701403f6a8aec5a8a526008a..c2de073a521972a6f2edde3a46452a7e3599d5e1 100644 (file)
--- a/src/include/cpu/x86/cache.h
+++ b/src/include/cpu/x86/cache.h
@@ -22,7 +22,7 @@
 
 /*
  * Need two versions because ROMCC chokes on certain clobbers:
 
 /*
  * Need two versions because ROMCC chokes on certain clobbers:

- * cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33: 
+ * cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33:

  * 0x1559920 asm        Internal compiler error: lhs 1 regcm == 0
  */
 
  * 0x1559920 asm        Internal compiler error: lhs 1 regcm == 0
  */
 

diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index e8bc195307ecf52aee2f696b7225ae16c657c5ca..40926df602e4633c61851e9dc956d5b7ef3c9c14 100644 (file)
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -23,7 +23,7 @@ typedef struct msr_struct
        unsigned hi;
 } msr_t;
 
        unsigned hi;
 } msr_t;
 

-typedef struct msrinit_struct 
+typedef struct msrinit_struct

 {
         unsigned index;
         msr_t msr;
 {
         unsigned index;
         msr_t msr;

diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c
index e79cb633467c40444d1e03ad627e6afe72f7f505..75d51ffa8343cea65001301110a302d31e1a4f06 100644 (file)
--- a/src/lib/uart8250mem.c
+++ b/src/lib/uart8250mem.c
@@ -120,7 +120,7 @@ u32 uart_mem_init(void)
 
        if (dev) {
                struct resource *res = find_resource(dev, 0x10);
 
        if (dev) {
                struct resource *res = find_resource(dev, 0x10);

-       
+

                if (res) {
                        uart_bar = res->base + 0x1000; // for 1st UART
                        // uart_bar = res->base + 0x2000; // for 2nd UART
                if (res) {
                        uart_bar = res->base + 0x1000; // for 1st UART
                        // uart_bar = res->base + 0x2000; // for 2nd UART


@@ -131,7 +131,7 @@ u32 uart_mem_init(void)
 #endif
        uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; // 1st UART
        // uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; // 2nd UART
 #endif
        uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; // 1st UART
        // uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; // 2nd UART

-       
+

        div = 4000000 / uart_baud;
 #endif
 
        div = 4000000 / uart_baud;
 #endif
 

diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c
index 6b75acf5237a3b0820141217117eed6eba20ee70..800ee52ae3ccddd67a239d8351a675f610c70fed 100644 (file)
--- a/src/lib/usbdebug.c
+++ b/src/lib/usbdebug.c
@@ -167,7 +167,7 @@ static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
                bytes[i] = (hi >> (8*(i - 4))) & 0xff;
 }
 
                bytes[i] = (hi >> (8*(i - 4))) & 0xff;
 }
 

-static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug, 
+static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug,

                unsigned devnum, unsigned endpoint, const char *bytes, int size)
 {
        u32 pids, addr, ctrl;
                unsigned devnum, unsigned endpoint, const char *bytes, int size)
 {
        u32 pids, addr, ctrl;


@@ -234,7 +234,7 @@ static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, unsigned devnum,
 
 int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size)
 {
 
 int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size)
 {

-       return dbgp_bulk_read(dbg_info->ehci_debug, dbg_info->devnum, 
+       return dbgp_bulk_read(dbg_info->ehci_debug, dbg_info->devnum,

                        dbg_info->endpoint_in, data, size);
 }
 
                        dbg_info->endpoint_in, data, size);
 }
 


@@ -373,7 +373,7 @@ int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *in
        int playtimes = 3;
 
        ehci_caps  = (struct ehci_caps *)ehci_bar;
        int playtimes = 3;
 
        ehci_caps  = (struct ehci_caps *)ehci_bar;

-       ehci_regs  = (struct ehci_regs *)(ehci_bar + 
+       ehci_regs  = (struct ehci_regs *)(ehci_bar +

                        HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase)));
        ehci_debug = (struct ehci_dbg_port *)(ehci_bar + offset);
        info->ehci_debug = (void *)0;
                        HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase)));
        ehci_debug = (struct ehci_dbg_port *)(ehci_bar + offset);
        info->ehci_debug = (void *)0;

diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c
index 7dcdd96098b2a3239437e7fd5322e0cdc8930758..a72f96b4c3b1db164d6f4785e261b252435560e4 100644 (file)
--- a/src/mainboard/amd/inagua/BiosCallOuts.c
+++ b/src/mainboard/amd/inagua/BiosCallOuts.c
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

- 
+

 #include "agesawrapper.h"
 #include "amdlib.h"
 #include "BiosCallOuts.h"
 #include "agesawrapper.h"
 #include "amdlib.h"
 #include "BiosCallOuts.h"


@@ -58,11 +58,11 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[REQUIRED_CALLOUTS] =
   {AGESA_GET_IDS_INIT_DATA,
    BiosGetIdsInitData
   },
   {AGESA_GET_IDS_INIT_DATA,
    BiosGetIdsInitData
   },

-  
+

   {AGESA_HOOKBEFORE_DQS_TRAINING,
    BiosHookBeforeDQSTraining
   },
   {AGESA_HOOKBEFORE_DQS_TRAINING,
    BiosHookBeforeDQSTraining
   },

-  
+

   {AGESA_HOOKBEFORE_DRAM_INIT,
    BiosHookBeforeDramInit
   },
   {AGESA_HOOKBEFORE_DRAM_INIT,
    BiosHookBeforeDramInit
   },


@@ -210,7 +210,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
        to the end of the allocated nodes list.
       */
       /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
        to the end of the allocated nodes list.
       */

-       
+

     }
     /* Find the node that best fits the requested buffer size */
     FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
     }
     /* Find the node that best fits the requested buffer size */
     FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;


@@ -260,7 +260,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 
       /* If BestFitNode is the first buffer in the list, then update
          StartOfFreedNodes to reflect the new free node
 
       /* If BestFitNode is the first buffer in the list, then update
          StartOfFreedNodes to reflect the new free node

-      */         
+      */

       if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
         BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
       } else {
       if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
         BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
       } else {


@@ -345,10 +345,10 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       FreedNodePtr->NextNodeOffset = 0;
 
     } else {
       FreedNodePtr->NextNodeOffset = 0;
 
     } else {

-      /* Otherwise, add freed node to the start of the list 
-         Update NextNodeOffset and BufferSize to include the 
+      /* Otherwise, add freed node to the start of the list
+         Update NextNodeOffset and BufferSize to include the

          size of BIOS_BUFFER_NODE
          size of BIOS_BUFFER_NODE

-      */   
+      */

       AllocNodePtr->NextNodeOffset = FreedNodeOffset;
     }
     /* Update StartOfFreedNodes to the new first node */
       AllocNodePtr->NextNodeOffset = FreedNodeOffset;
     }
     /* Update StartOfFreedNodes to the new first node */


@@ -356,7 +356,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   } else {
     /* Traverse list of freed nodes to find where the deallocated node
        should be place
   } else {
     /* Traverse list of freed nodes to find where the deallocated node
        should be place

-    */   
+    */

     NextNodeOffset = FreedNodeOffset;
     NextNodePtr = FreedNodePtr;
     while (AllocNodeOffset > NextNodeOffset) {
     NextNodeOffset = FreedNodeOffset;
     NextNodePtr = FreedNodePtr;
     while (AllocNodeOffset > NextNodeOffset) {


@@ -370,7 +370,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 
     /* If deallocated node is adjacent to the next node,
        concatenate both nodes
 
     /* If deallocated node is adjacent to the next node,
        concatenate both nodes

-    */   
+    */

     if (NextNodeOffset == EndNodeOffset) {
       NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
       AllocNodePtr->BufferSize += NextNodePtr->BufferSize;
     if (NextNodeOffset == EndNodeOffset) {
       NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
       AllocNodePtr->BufferSize += NextNodePtr->BufferSize;


@@ -384,7 +384,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
     }
     /* If deallocated node is adjacent to the previous node,
        concatenate both nodes
     }
     /* If deallocated node is adjacent to the previous node,
        concatenate both nodes

-    */   
+    */

     PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
     EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
     if (AllocNodeOffset == EndNodeOffset) {
     PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
     EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
     if (AllocNodeOffset == EndNodeOffset) {


@@ -448,10 +448,10 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   UINT8                 Value;
   UINTN               ResetType;
   AMD_CONFIG_PARAMS   *StdHeader;
   UINT8                 Value;
   UINTN               ResetType;
   AMD_CONFIG_PARAMS   *StdHeader;

-  
+

   ResetType = Data;
   StdHeader = ConfigPtr;
   ResetType = Data;
   StdHeader = ConfigPtr;

-    
+

   //
   // Perform the RESET based upon the ResetType. In case of
   // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to
   //
   // Perform the RESET based upon the ResetType. In case of
   // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to


@@ -463,17 +463,17 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   case WARM_RESET_WHENEVER:
   case COLD_RESET_WHENEVER:
     break;
   case WARM_RESET_WHENEVER:
   case COLD_RESET_WHENEVER:
     break;

-    
+

   case WARM_RESET_IMMEDIATELY:
   case COLD_RESET_IMMEDIATELY:
       Value = 0x06;
       LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
     break;
   case WARM_RESET_IMMEDIATELY:
   case COLD_RESET_IMMEDIATELY:
       Value = 0x06;
       LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
     break;

-    
+

   default:
     break;
   }
   default:
     break;
   }

-  
+

   Status = 0;
   return Status;
 }
   Status = 0;
   return Status;
 }


@@ -506,10 +506,10 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   UINT8             Data8;
   UINT16            Data16;
   UINT8             TempData8;
   UINT8             Data8;
   UINT16            Data16;
   UINT8             TempData8;

-    
+

   FcnData = Data;
   MemData = ConfigPtr;
   FcnData = Data;
   MemData = ConfigPtr;

-  
+

   Status  = AGESA_SUCCESS;
   /* Get SB800 MMIO Base (AcpiMmioAddr) */
   WriteIo8 (0xCD6, 0x27);
   Status  = AGESA_SUCCESS;
   /* Get SB800 MMIO Base (AcpiMmioAddr) */
   WriteIo8 (0xCD6, 0x27);


@@ -520,14 +520,14 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   Data16  |= Data8;
   AcpiMmioAddr = (UINT32)Data16 << 16;
   GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
   Data16  |= Data8;
   AcpiMmioAddr = (UINT32)Data16 << 16;
   GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;

-  
+

   Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
   Data8 &= ~BIT5;
   TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
   TempData8 &= 0x03;
   TempData8 |= Data8;
   Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
   Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
   Data8 &= ~BIT5;
   TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
   TempData8 &= 0x03;
   TempData8 |= Data8;
   Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);

-   
+

   Data8 |= BIT2+BIT3;
   Data8 &= ~BIT4;
   TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
   Data8 |= BIT2+BIT3;
   Data8 &= ~BIT4;
   TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);


@@ -546,7 +546,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   TempData8 &= 0x23;
   TempData8 |= Data8;
   Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
   TempData8 &= 0x23;
   TempData8 |= Data8;
   Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);

-  
+

   switch(MemData->ParameterListPtr->DDR3Voltage){
     case VOLT1_35:
       Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
   switch(MemData->ParameterListPtr->DDR3Voltage){
     case VOLT1_35:
       Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);


@@ -586,12 +586,12 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   AGESA_STATUS Status;
   UINTN                 FcnData;
   PCIe_SLOT_RESET_INFO  *ResetInfo;
   AGESA_STATUS Status;
   UINTN                 FcnData;
   PCIe_SLOT_RESET_INFO  *ResetInfo;

-  
+

   UINT32  GpioMmioAddr;
   UINT32  AcpiMmioAddr;
   UINT8   Data8;
   UINT16  Data16;
   UINT32  GpioMmioAddr;
   UINT32  AcpiMmioAddr;
   UINT8   Data8;
   UINT16  Data16;

-  
+

   FcnData   = Data;
   ResetInfo = ConfigPtr;
   // Get SB800 MMIO Base (AcpiMmioAddr)
   FcnData   = Data;
   ResetInfo = ConfigPtr;
   // Get SB800 MMIO Base (AcpiMmioAddr)


@@ -611,13 +611,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       {
       case AssertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
       {
       case AssertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);

-        Data8 &= ~(UINT8)BIT6 ; 
+        Data8 &= ~(UINT8)BIT6 ;

         Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);   // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
         Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);   // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);

-        Data8 |= BIT6 ; 
+        Data8 |= BIT6 ;

         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);       // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;
         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);       // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;


@@ -634,7 +634,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);

-        Data8 |= BIT6 ; 
+        Data8 |= BIT6 ;

         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);       // PCIE_RST#_LAN, GPIO25
         Status = AGESA_SUCCESS;
         break;
         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);       // PCIE_RST#_LAN, GPIO25
         Status = AGESA_SUCCESS;
         break;

diff --git a/src/mainboard/amd/inagua/BiosCallOuts.h b/src/mainboard/amd/inagua/BiosCallOuts.h
index 2912ec6f513ccd245db0f3755bcd6ab566cb89ec..4efe15fa4d55e5efb039ef4dca6e7d3c19ca7f85 100644 (file)
--- a/src/mainboard/amd/inagua/BiosCallOuts.h
+++ b/src/mainboard/amd/inagua/BiosCallOuts.h
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

- 
+

 #ifndef _BIOS_CALLOUT_H_
 #define _BIOS_CALLOUT_H_
 
 #ifndef _BIOS_CALLOUT_H_
 #define _BIOS_CALLOUT_H_
 


@@ -45,7 +45,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 
 /* REQUIRED CALLOUTS
  * AGESA ADVANCED CALLOUTS - CPU
 
 /* REQUIRED CALLOUTS
  * AGESA ADVANCED CALLOUTS - CPU

- */  
+ */

 AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);

diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c
index 1840afc55219b5ed4ca9e241408093d5ecaf9b90..4f000717fee80e66c01cc9de2af4f14bd686ea0a 100644 (file)
--- a/src/mainboard/amd/inagua/PlatformGnbPcie.c
+++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c
@@ -56,7 +56,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
           DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
           PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
           PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
           DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
           PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
           PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)

-        }       
+        }

 };
 
 PCIe_DDI_DESCRIPTOR DdiList [] = {
 };
 
 PCIe_DDI_DESCRIPTOR DdiList [] = {


@@ -116,8 +116,8 @@ OemCustomizeInitEarly (
   //
   // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
   //
   //
   // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
   //

-  AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  + 
-                                         sizeof (PCIe_PORT_DESCRIPTOR) * 5 + 
+  AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  +
+                                         sizeof (PCIe_PORT_DESCRIPTOR) * 5 +

                                          sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
 
   AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
                                          sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
 
   AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;


@@ -125,10 +125,10 @@ OemCustomizeInitEarly (
   Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
   if ( Status!= AGESA_SUCCESS) {
     // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
   Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
   if ( Status!= AGESA_SUCCESS) {
     // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR

-    ASSERT(FALSE); 
+    ASSERT(FALSE);

     return Status;
   }
     return Status;
   }

-  
+

   BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
   BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);


@@ -136,7 +136,7 @@ OemCustomizeInitEarly (
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
   BrazosPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
   BrazosPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;

- 
+

   LibAmdMemFill (BrazosPcieComplexListPtr,
                    0,
                    sizeof (PCIe_COMPLEX_DESCRIPTOR),
   LibAmdMemFill (BrazosPcieComplexListPtr,
                    0,
                    sizeof (PCIe_COMPLEX_DESCRIPTOR),


@@ -146,7 +146,7 @@ OemCustomizeInitEarly (
                    0,
                    sizeof (PCIe_PORT_DESCRIPTOR) * 5,
                    &InitEarly->StdHeader);
                    0,
                    sizeof (PCIe_PORT_DESCRIPTOR) * 5,
                    &InitEarly->StdHeader);

-     
+

   LibAmdMemFill (BrazosPcieDdiPtr,
                    0,
                    sizeof (PCIe_DDI_DESCRIPTOR) * 2,
   LibAmdMemFill (BrazosPcieDdiPtr,
                    0,
                    sizeof (PCIe_DDI_DESCRIPTOR) * 2,


@@ -160,7 +160,7 @@ OemCustomizeInitEarly (
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
 
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
 

-  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; 
-  InitEarly->GnbConfig.PsppPolicy      = 0; 
+  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
+  InitEarly->GnbConfig.PsppPolicy      = 0;

 }
 
 }
 

diff --git a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
index f35d8db723c464a538c7b20f78e3947365e2d5ed..b51089f7f643cdc51ebbc15bf184ca99ca309e76 100644 (file)
--- a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
+++ b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
@@ -25,42 +25,42 @@
 #include "amdlib.h"
 
 //GNB GPP Port4
 #include "amdlib.h"
 
 //GNB GPP Port4

-#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable

 #define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT4_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT4_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1

-#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)

                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port5
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port5

-#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable

 #define GNB_GPP_PORT5_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT5_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT5_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT5_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1

-#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)

                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port6
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port6

-#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable

 #define GNB_GPP_PORT6_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT6_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT6_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT6_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1

-#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)

                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port7
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port7

-#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable

 #define GNB_GPP_PORT7_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT7_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT7_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT7_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1

-#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)

                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port8
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port8

-#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable

 #define GNB_GPP_PORT8_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT8_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT8_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT8_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1

-#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)

                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 


@@ -68,5 +68,5 @@ VOID
 OemCustomizeInitEarly (
   IN  OUT AMD_EARLY_PARAMS    *InitEarly
   );
 OemCustomizeInitEarly (
   IN  OUT AMD_EARLY_PARAMS    *InitEarly
   );

-  
+

 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H
 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H

diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c
index 4c084e0aba784217503b23ea412c274b6bb21b0b..cc37ed24b022d5856c7d1579115f291aa4cead8b 100644 (file)
--- a/src/mainboard/amd/inagua/acpi_tables.c
+++ b/src/mainboard/amd/inagua/acpi_tables.c
@@ -62,18 +62,18 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 
 unsigned long acpi_fill_madt(unsigned long current)
 {
 
 unsigned long acpi_fill_madt(unsigned long current)
 {

-  
+

   /* create all subtables for processors */
   current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
   current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1);
   /* create all subtables for processors */
   current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
   current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1);

-  
+

   /* Write SB800 IOAPIC, only one */
   current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb800,
              IO_APIC_ADDR, 0);
 
   current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
             current, 0, 0, 2, 0);
   /* Write SB800 IOAPIC, only one */
   current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb800,
              IO_APIC_ADDR, 0);
 
   current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
             current, 0, 0, 2, 0);

-  
+

   /* 0: mean bus 0--->ISA */
   /* 0: PIC 0 */
   /* 2: APIC 2 */
   /* 0: mean bus 0--->ISA */
   /* 0: PIC 0 */
   /* 2: APIC 2 */

diff --git a/src/mainboard/amd/inagua/agesawrapper.c b/src/mainboard/amd/inagua/agesawrapper.c
index cbdb23d5ede3b6175c0244f36b5e7ea0bf73f2b6..df5cd1e9a94c616ed0d5f9ee1ca66273407042e0 100644 (file)
--- a/src/mainboard/amd/inagua/agesawrapper.c
+++ b/src/mainboard/amd/inagua/agesawrapper.c
@@ -21,7 +21,7 @@
  *                             M O D U L E S    U S E D
  *----------------------------------------------------------------------------------------
  */
  *                             M O D U L E S    U S E D
  *----------------------------------------------------------------------------------------
  */

- 
+

 #include <stdint.h>
 #include <string.h>
 #include "agesawrapper.h"
 #include <stdint.h>
 #include <string.h>
 #include "agesawrapper.h"


@@ -52,8 +52,8 @@ VOID *AcpiSlit    = NULL;
 
 VOID *AcpiWheaMce = NULL;
 VOID *AcpiWheaCmc = NULL;
 
 VOID *AcpiWheaMce = NULL;
 VOID *AcpiWheaCmc = NULL;

-VOID *AcpiAlib    = NULL; 
- 
+VOID *AcpiAlib    = NULL;
+

 
 /*----------------------------------------------------------------------------------------
  *                  T Y P E D E F S     A N D     S T R U C T U  R E S
 
 /*----------------------------------------------------------------------------------------
  *                  T Y P E D E F S     A N D     S T R U C T U  R E S


@@ -64,17 +64,17 @@ VOID *AcpiAlib    = NULL;
  *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
  *----------------------------------------------------------------------------------------
  */
  *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
  *----------------------------------------------------------------------------------------
  */

- 
+

 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */

- 
+

 /*---------------------------------------------------------------------------------------
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */
 /*---------------------------------------------------------------------------------------
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */

-UINT32 
+UINT32

 agesawrapper_amdinitcpuio (
   VOID
   )
 agesawrapper_amdinitcpuio (
   VOID
   )


@@ -84,30 +84,30 @@ agesawrapper_amdinitcpuio (
   UINT32                        PciData;
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;
   UINT32                        PciData;
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;

-  
+

   /* Enable MMIO on AMD CPU Address Map Controller */
   /* Enable MMIO on AMD CPU Address Map Controller */

-  
+

   /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
   PciData = 0x00000B00;
   /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
   PciData = 0x00000B00;

-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
   PciData = 0x00000A03;
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
   PciData = 0x00000A03;
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

-  
+

   /* Set TOM-DFFFFFFF to Node0 Link0. */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
   PciData = 0x00DFFF00;
   /* Set TOM-DFFFFFFF to Node0 Link0. */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
   PciData = 0x00DFFF00;

-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

   LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
   MsrReg = (MsrReg >> 8) | 3;
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
   PciData = (UINT32)MsrReg;
   LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
   MsrReg = (MsrReg >> 8) | 3;
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
   PciData = (UINT32)MsrReg;

-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

   /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC);
   PciData = 0x00FFFF00 | 0x80;
   /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC);
   PciData = 0x00FFFF00 | 0x80;

-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8);
   PciData = (PCIE_BASE_ADDRESS >> 8) | 03;
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8);
   PciData = (PCIE_BASE_ADDRESS >> 8) | 03;
   LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);


@@ -121,8 +121,8 @@ agesawrapper_amdinitcpuio (
   Status = AGESA_SUCCESS;
   return (UINT32)Status;
 }
   Status = AGESA_SUCCESS;
   return (UINT32)Status;
 }

- 
-UINT32 
+
+UINT32

 agesawrapper_amdinitmmio (
   VOID
   )
 agesawrapper_amdinitmmio (
   VOID
   )


@@ -132,29 +132,29 @@ agesawrapper_amdinitmmio (
   UINT32                        PciData;
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;
   UINT32                        PciData;
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;

-  
+

   /*
    Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
    Address MSR register.
   */
   MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1;
   LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
   /*
    Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
    Address MSR register.
   */
   MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1;
   LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);

-  
+

   /*
    Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
   */
   LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
   MsrReg = MsrReg | 0x0000400000000000;
   LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
   /*
    Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
   */
   LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
   MsrReg = MsrReg | 0x0000400000000000;
   LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);

-  
+

   /* Set Ontario Link Data */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
   PciData = 0x01308002;
   /* Set Ontario Link Data */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
   PciData = 0x01308002;

-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
   PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
   PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;

-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-  
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+

 
   /* Set ROM cache onto WP to decrease post time */
   MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
 
   /* Set ROM cache onto WP to decrease post time */
   MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;


@@ -166,7 +166,7 @@ agesawrapper_amdinitmmio (
   return (UINT32)Status;
 }
 
   return (UINT32)Status;
 }
 

-UINT32 
+UINT32

 agesawrapper_amdinitreset (
   VOID
   )
 agesawrapper_amdinitreset (
   VOID
   )


@@ -174,7 +174,7 @@ agesawrapper_amdinitreset (
   AGESA_STATUS status;
   AMD_INTERFACE_PARAMS AmdParamStruct;
   AMD_RESET_PARAMS AmdResetParams;
   AGESA_STATUS status;
   AMD_INTERFACE_PARAMS AmdParamStruct;
   AMD_RESET_PARAMS AmdResetParams;

-  
+

   LibAmdMemFill (&AmdParamStruct,
                  0,
                  sizeof (AMD_INTERFACE_PARAMS),
   LibAmdMemFill (&AmdParamStruct,
                  0,
                  sizeof (AMD_INTERFACE_PARAMS),


@@ -196,14 +196,14 @@ agesawrapper_amdinitreset (
   AmdParamStruct.StdHeader.ImageBasePtr = 0;
   AmdCreateStruct (&AmdParamStruct);
   AmdResetParams.HtConfig.Depth = 0;
   AmdParamStruct.StdHeader.ImageBasePtr = 0;
   AmdCreateStruct (&AmdParamStruct);
   AmdResetParams.HtConfig.Depth = 0;

-  
+

   status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
   if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
   AmdReleaseStruct (&AmdParamStruct);
   return (UINT32)status;
   status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
   if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
   AmdReleaseStruct (&AmdParamStruct);
   return (UINT32)status;

- }  
-  
-UINT32 
+ }
+
+UINT32

 agesawrapper_amdinitearly (
   VOID
   )
 agesawrapper_amdinitearly (
   VOID
   )


@@ -211,7 +211,7 @@ agesawrapper_amdinitearly (
   AGESA_STATUS status;
   AMD_INTERFACE_PARAMS AmdParamStruct;
   AMD_EARLY_PARAMS     *AmdEarlyParamsPtr;
   AGESA_STATUS status;
   AMD_INTERFACE_PARAMS AmdParamStruct;
   AMD_EARLY_PARAMS     *AmdEarlyParamsPtr;

-  
+

   LibAmdMemFill (&AmdParamStruct,
                  0,
                  sizeof (AMD_INTERFACE_PARAMS),
   LibAmdMemFill (&AmdParamStruct,
                  0,
                  sizeof (AMD_INTERFACE_PARAMS),


@@ -224,10 +224,10 @@ agesawrapper_amdinitearly (
   AmdParamStruct.StdHeader.Func = 0;
   AmdParamStruct.StdHeader.ImageBasePtr = 0;
   AmdCreateStruct (&AmdParamStruct);
   AmdParamStruct.StdHeader.Func = 0;
   AmdParamStruct.StdHeader.ImageBasePtr = 0;
   AmdCreateStruct (&AmdParamStruct);

-  
+

   AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
   OemCustomizeInitEarly (AmdEarlyParamsPtr);
   AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
   OemCustomizeInitEarly (AmdEarlyParamsPtr);

-  
+

   status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
   if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
   AmdReleaseStruct (&AmdParamStruct);
   status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
   if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
   AmdReleaseStruct (&AmdParamStruct);


@@ -235,7 +235,7 @@ agesawrapper_amdinitearly (
   return (UINT32)status;
 }
 
   return (UINT32)status;
 }
 

-UINT32 
+UINT32

 agesawrapper_amdinitpost (
   VOID
   )
 agesawrapper_amdinitpost (
   VOID
   )


@@ -277,7 +277,7 @@ agesawrapper_amdinitpost (
   return (UINT32)status;
 }
 
   return (UINT32)status;
 }
 

-UINT32 
+UINT32

 agesawrapper_amdinitenv (
   VOID
   )
 agesawrapper_amdinitenv (
   VOID
   )


@@ -304,7 +304,7 @@ agesawrapper_amdinitenv (
   /* Initialize Subordinate Bus Number and Secondary Bus Number
    * In platform BIOS this address is allocated by PCI enumeration code
      Modify D1F0x18
   /* Initialize Subordinate Bus Number and Secondary Bus Number
    * In platform BIOS this address is allocated by PCI enumeration code
      Modify D1F0x18

-   */  
+   */

   PciAddress.Address.Bus = 0;
   PciAddress.Address.Device = 1;
   PciAddress.Address.Function = 0;
   PciAddress.Address.Bus = 0;
   PciAddress.Address.Device = 1;
   PciAddress.Address.Function = 0;


@@ -407,17 +407,17 @@ agesawrapper_getlateinitptr (
   }
 }
 
   }
 }
 

-UINT32 
+UINT32

 agesawrapper_amdinitmid (
   VOID
   )
 {
   AGESA_STATUS status;
   AMD_INTERFACE_PARAMS AmdParamStruct;
 agesawrapper_amdinitmid (
   VOID
   )
 {
   AGESA_STATUS status;
   AMD_INTERFACE_PARAMS AmdParamStruct;

-  
+

   /* Enable MMIO on AMD CPU Address Map Controller */
   agesawrapper_amdinitcpuio ();
   /* Enable MMIO on AMD CPU Address Map Controller */
   agesawrapper_amdinitcpuio ();

-  
+

   LibAmdMemFill (&AmdParamStruct,
                  0,
                  sizeof (AMD_INTERFACE_PARAMS),
   LibAmdMemFill (&AmdParamStruct,
                  0,
                  sizeof (AMD_INTERFACE_PARAMS),


@@ -439,7 +439,7 @@ agesawrapper_amdinitmid (
   return (UINT32)status;
 }
 
   return (UINT32)status;
 }
 

-UINT32 
+UINT32

 agesawrapper_amdinitlate (
   VOID
   )
 agesawrapper_amdinitlate (
   VOID
   )


@@ -475,9 +475,9 @@ agesawrapper_amdinitlate (
   return (UINT32)Status;
 }
 
   return (UINT32)Status;
 }
 

-UINT32 
+UINT32

 agesawrapper_amdlaterunaptask (
 agesawrapper_amdlaterunaptask (

-  UINT32 Data, 
+  UINT32 Data,

   VOID *ConfigPtr
   )
 {
   VOID *ConfigPtr
   )
 {


@@ -512,7 +512,7 @@ agesawrapper_amdlaterunaptask (
   return (UINT32)Status;
 }
 
   return (UINT32)Status;
 }
 

-UINT32 
+UINT32

 agesawrapper_amdreadeventlog (
   VOID
   )
 agesawrapper_amdreadeventlog (
   VOID
   )

diff --git a/src/mainboard/amd/inagua/agesawrapper.h b/src/mainboard/amd/inagua/agesawrapper.h
index fd46dc6358038604c3342a6802d20602c812b71e..f6e6decad6a9d89bf66cb0a28ce9d7ba49591d15 100644 (file)
--- a/src/mainboard/amd/inagua/agesawrapper.h
+++ b/src/mainboard/amd/inagua/agesawrapper.h
@@ -21,8 +21,8 @@
  *                             M O D U L E S    U S E D
  *----------------------------------------------------------------------------------------
  */
  *                             M O D U L E S    U S E D
  *----------------------------------------------------------------------------------------
  */

- 
-  
+
+

 #ifndef _AGESAWRAPPER_H_
 #define _AGESAWRAPPER_H_
 
 #ifndef _AGESAWRAPPER_H_
 #define _AGESAWRAPPER_H_
 


@@ -66,17 +66,17 @@ typedef struct {
  *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
  *----------------------------------------------------------------------------------------
  */
  *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
  *----------------------------------------------------------------------------------------
  */

- 
+

 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */

- 
+

 /*---------------------------------------------------------------------------------------
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */
 /*---------------------------------------------------------------------------------------
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */

- 
+

 //void brazos_platform_stage(void);
 UINT32 agesawrapper_amdinitreset (void);
 UINT32 agesawrapper_amdinitearly (void);
 //void brazos_platform_stage(void);
 UINT32 agesawrapper_amdinitreset (void);
 UINT32 agesawrapper_amdinitearly (void);

diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
index 686f7fa717cc4981986f6f2f95e004acd66a5cfe..919f6be907adb3b319d1ba8e637f942effab1d70 100644 (file)
--- a/src/mainboard/amd/inagua/buildOpts.c
+++ b/src/mainboard/amd/inagua/buildOpts.c
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

- 
+

 /**
  * @file
  *
 /**
  * @file
  *


@@ -57,13 +57,13 @@
 #define INSTALL_FT1_SOCKET_SUPPORT  TRUE
 #define INSTALL_AM3_SOCKET_SUPPORT  FALSE
 
 #define INSTALL_FT1_SOCKET_SUPPORT  TRUE
 #define INSTALL_AM3_SOCKET_SUPPORT  FALSE
 

-/* 
- * Agesa optional capabilities selection.  
+/*
+ * Agesa optional capabilities selection.

  * Uncomment and mark FALSE those features you wish to include in the build.
  * Comment out or mark TRUE those features you want to REMOVE from the build.
  */
 
  * Uncomment and mark FALSE those features you wish to include in the build.
  * Comment out or mark TRUE those features you want to REMOVE from the build.
  */
 

-#define BLDOPT_REMOVE_FAMILY_10_SUPPORT       TRUE    
+#define BLDOPT_REMOVE_FAMILY_10_SUPPORT       TRUE

 #define BLDOPT_REMOVE_FAMILY_12_SUPPORT       TRUE
 #define BLDOPT_REMOVE_FAMILY_14_SUPPORT       FALSE
 #define BLDOPT_REMOVE_FAMILY_15_SUPPORT       TRUE
 #define BLDOPT_REMOVE_FAMILY_12_SUPPORT       TRUE
 #define BLDOPT_REMOVE_FAMILY_14_SUPPORT       FALSE
 #define BLDOPT_REMOVE_FAMILY_15_SUPPORT       TRUE


@@ -104,7 +104,7 @@
 //#define BLDOPT_REMOVE_HT_ASSIST         TRUE
 //#define BLDOPT_REMOVE_ATM_MODE          TRUE
 //#define BLDOPT_REMOVE_MSG_BASED_C1E       TRUE
 //#define BLDOPT_REMOVE_HT_ASSIST         TRUE
 //#define BLDOPT_REMOVE_ATM_MODE          TRUE
 //#define BLDOPT_REMOVE_MSG_BASED_C1E       TRUE

-//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE  
+//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE

 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT     FALSE
 //#define BLDOPT_REMOVE_C6_STATE          TRUE
 //#define BLDOPT_REMOVE_GFX_RECOVERY        TRUE
 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT     FALSE
 //#define BLDOPT_REMOVE_C6_STATE          TRUE
 //#define BLDOPT_REMOVE_GFX_RECOVERY        TRUE


@@ -125,10 +125,10 @@
 #define AGESA_ENTRY_INIT_LATE_RESTORE             FALSE
 #define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
 
 #define AGESA_ENTRY_INIT_LATE_RESTORE             FALSE
 #define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
 

-/* 
- * Agesa configuration values selection.  
+/*
+ * Agesa configuration values selection.

  * Uncomment and specify the value for the configuration options
  * Uncomment and specify the value for the configuration options

- * needed by the system. 
+ * needed by the system.

  */
 
 /* The fixed MTRR values to be set after memory initialization. */
  */
 
 /* The fixed MTRR values to be set after memory initialization. */

diff --git a/src/mainboard/amd/inagua/dimmSpd.c b/src/mainboard/amd/inagua/dimmSpd.c
index d6bf5b28e1bc44cd3243b004edbaf99c2ce49ed9..d82cb5d2c019d846eb133bf900dc2bc061bc6641 100644 (file)
--- a/src/mainboard/amd/inagua/dimmSpd.c
+++ b/src/mainboard/amd/inagua/dimmSpd.c
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

- 
+

 #include "Porting.h"
 #include "AGESA.h"
 #include "amdlib.h"
 #include "Porting.h"
 #include "AGESA.h"
 #include "amdlib.h"


@@ -51,7 +51,7 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
    UINT64 limit;
 
    address |= 1; // set read bit
    UINT64 limit;
 
    address |= 1; // set read bit

-   
+

    __outbyte (iobase + 0, 0xFF);                // clear error status
    __outbyte (iobase + 1, 0x1F);                // clear error status
    __outbyte (iobase + 3, offset);              // offset in eeprom
    __outbyte (iobase + 0, 0xFF);                // clear error status
    __outbyte (iobase + 1, 0x1F);                // clear error status
    __outbyte (iobase + 3, offset);              // offset in eeprom


@@ -108,7 +108,7 @@ static int readSmbusByte (int iobase, int address, char *buffer)
  *
  * readspd - Read one or more SPD bytes from a DIMM.
  *           Start with offset zero and read sequentially.
  *
  * readspd - Read one or more SPD bytes from a DIMM.
  *           Start with offset zero and read sequentially.

- *           Optimization relies on autoincrement to avoid 
+ *           Optimization relies on autoincrement to avoid

  *           sending offset for every byte.
  *          Reads 128 bytes in 7-8 ms at 400 KHz.
  */
  *           sending offset for every byte.
  *          Reads 128 bytes in 7-8 ms at 400 KHz.
  */


@@ -127,7 +127,7 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
       error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
       if (error) return error;
       }
       error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
       if (error) return error;
       }

-   
+

    return 0;
    }
 
    return 0;
    }
 


@@ -150,11 +150,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
    {
    int spdAddress, ioBase;
 
    {
    int spdAddress, ioBase;
 

-   if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR; 
-   if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR; 
+   if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR;
+   if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR;

    if (info->DimmId       >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
    if (info->DimmId       >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;

-   
-   spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; 
+
+   spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];

    if (spdAddress == 0) return AGESA_ERROR;
    ioBase = SMBUS_BASE_ADDR;
    setupFch (ioBase);
    if (spdAddress == 0) return AGESA_ERROR;
    ioBase = SMBUS_BASE_ADDR;
    setupFch (ioBase);

diff --git a/src/mainboard/amd/inagua/dimmSpd.h b/src/mainboard/amd/inagua/dimmSpd.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/amd/inagua/get_bus_conf.c b/src/mainboard/amd/inagua/get_bus_conf.c
index fedab7531ae75893b6df91902c904129ecc660c0..ab58c99aea8b52430c52c63b89955354d266777f 100644 (file)
--- a/src/mainboard/amd/inagua/get_bus_conf.c
+++ b/src/mainboard/amd/inagua/get_bus_conf.c
@@ -79,22 +79,22 @@ void get_bus_conf(void)
  * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
  * but functionally within the coreboot model, this is the best place to make the
  * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
  * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
  * but functionally within the coreboot model, this is the best place to make the
  * call.  The logically correct place to call AmdInitLate is after PCI scan is done,

- * after the decision about S3 resume is made, and before the system tables are 
- * written into RAM.  The routine that is responsible for writing the tables is 
- * "write_tables", called near the end of "hardwaremain".  There is no platform 
- * specific entry point between the S3 resume decision point and the call to 
- * "write_tables", and the next platform specific entry points are the calls to 
- * the ACPI table write functions.  The first of ose would seem to be the right 
- * place, but other table write functions, e.g. the PIRQ table write function, are 
+ * after the decision about S3 resume is made, and before the system tables are
+ * written into RAM.  The routine that is responsible for writing the tables is
+ * "write_tables", called near the end of "hardwaremain".  There is no platform
+ * specific entry point between the S3 resume decision point and the call to
+ * "write_tables", and the next platform specific entry points are the calls to
+ * the ACPI table write functions.  The first of ose would seem to be the right
+ * place, but other table write functions, e.g. the PIRQ table write function, are

  * called before the ACPI tables are written.  This routine is called at the beginning
  * of each of the write functions called prior to the ACPI write functions, so this
  * becomes the best place for this call.
  */
  * called before the ACPI tables are written.  This routine is called at the beginning
  * of each of the write functions called prior to the ACPI write functions, so this
  * becomes the best place for this call.
  */

-  status = agesawrapper_amdinitlate(); 
+  status = agesawrapper_amdinitlate();

   if(status) {
     printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
   }
   if(status) {
     printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
   }

-  
+

   sbdn_sb800 = 0;
 
   for (i = 0; i < 3; i++) {
   sbdn_sb800 = 0;
 
   for (i = 0; i < 3; i++) {

diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index fa7de7d122087d90709f4304cab4d7d08dda6129..7278936902d2aa860f4d8c21b17567be0cdbf6ff 100644 (file)
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -37,15 +37,15 @@ extern u32 sbdn_sb800;
 u32 apicid_sb800;
 
 u8 picr_data[] = {
 u32 apicid_sb800;
 
 u8 picr_data[] = {

-  0x0B,0x0A,0x0B,0x05,0x1F,0x1F,0x1F,0x1F,0x50,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, 
-  0x1F,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 
+  0x0B,0x0A,0x0B,0x05,0x1F,0x1F,0x1F,0x1F,0x50,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+  0x1F,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

   0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x0A,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x0B,0x0A,0x0B,0x05
 };
 u8 intr_data[] = {
   0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x0A,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x0B,0x0A,0x0B,0x05
 };
 u8 intr_data[] = {

-  0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, 
+  0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,

   0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,


@@ -96,7 +96,7 @@ static void *smp_write_config_table(void *v)
       0, apic_version,
       cpu_flag, cpu_features, cpu_feature_flags
     );
       0, apic_version,
       cpu_flag, cpu_features, cpu_feature_flags
     );

-  
+

   cpu_flag = MPC_CPU_ENABLED;
   smp_write_processor(mc,
       1, apic_version,
   cpu_flag = MPC_CPU_ENABLED;
   smp_write_processor(mc,
       1, apic_version,


@@ -112,11 +112,11 @@ static void *smp_write_config_table(void *v)
   my_smp_write_bus(mc, bus_isa, "ISA   ");
 
   /* I/O APICs:   APIC ID Version State   Address */
   my_smp_write_bus(mc, bus_isa, "ISA   ");
 
   /* I/O APICs:   APIC ID Version State   Address */

-  
+

   device_t dev;
   u32 dword;
   u8 byte;
   device_t dev;
   u32 dword;
   u8 byte;

-    
+

   ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
   dword &= 0xFFFFFFF0;
   /* Set IO APIC ID onto IO_APIC_ID */
   ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
   dword &= 0xFFFFFFF0;
   /* Set IO APIC ID onto IO_APIC_ID */


@@ -124,13 +124,13 @@ static void *smp_write_config_table(void *v)
   write32 (dword + 0x10, IO_APIC_ID << 24);
   apicid_sb800 = IO_APIC_ID;
   smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
   write32 (dword + 0x10, IO_APIC_ID << 24);
   apicid_sb800 = IO_APIC_ID;
   smp_write_ioapic(mc, apicid_sb800, 0x21, dword);

-  
+

   /* PIC IRQ routine */
   for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
     outb(byte, 0xC00);
     outb(picr_data[byte], 0xC01);
   }
   /* PIC IRQ routine */
   for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
     outb(byte, 0xC00);
     outb(picr_data[byte], 0xC01);
   }

-  
+

   /* APIC IRQ routine */
   for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
     outb(byte | 0x80, 0xC00);
   /* APIC IRQ routine */
   for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
     outb(byte | 0x80, 0xC00);


@@ -168,12 +168,12 @@ static void *smp_write_config_table(void *v)
 
   /* SMBUS */
   PCI_INT(0x0, 0x14, 0x0, 0x10);
 
   /* SMBUS */
   PCI_INT(0x0, 0x14, 0x0, 0x10);

-  
+

   /* HD Audio */
   PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
   /* HD Audio */
   PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);

-  
+

   /* USB */
   /* USB */

-  PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); 
+  PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);

   PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
   PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
   PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
   PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
   PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
   PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);


@@ -187,7 +187,7 @@ static void *smp_write_config_table(void *v)
 
 
   /* on board NIC & Slot PCIE.  */
 
 
   /* on board NIC & Slot PCIE.  */

-  
+

   /* PCI slots */
   /* PCI_SLOT 0. */
   PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
   /* PCI slots */
   /* PCI_SLOT 0. */
   PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);

diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c
index 3fb0e875db9fe11b9e937286fbfab4bd05421318..3cfd7417557a694e31a7feeb92def1af542d89d3 100644 (file)
--- a/src/mainboard/amd/persimmon/BiosCallOuts.c
+++ b/src/mainboard/amd/persimmon/BiosCallOuts.c
@@ -91,7 +91,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       return CalloutStatus;
     }
   }
       return CalloutStatus;
     }
   }

- 
+

   return CalloutStatus;
 }
 
   return CalloutStatus;
 }
 


@@ -289,7 +289,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 
     } else {
       /* Otherwise, add freed node to the start of the list
 
     } else {
       /* Otherwise, add freed node to the start of the list

-         Update NextNodeOffset and BufferSize to include the 
+         Update NextNodeOffset and BufferSize to include the

          size of BIOS_BUFFER_NODE
       */
       AllocNodePtr->NextNodeOffset = FreedNodeOffset;
          size of BIOS_BUFFER_NODE
       */
       AllocNodePtr->NextNodeOffset = FreedNodeOffset;


@@ -470,7 +470,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   TempData8 &= 0x03;
   TempData8 |= Data8;
   Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
   TempData8 &= 0x03;
   TempData8 |= Data8;
   Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);

-   
+

   Data8 |= BIT2+BIT3;
   Data8 &= ~BIT4;
   TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
   Data8 |= BIT2+BIT3;
   Data8 &= ~BIT4;
   TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);


@@ -563,13 +563,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       {
       case AssertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
       {
       case AssertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);

-        Data8 &= ~(UINT8)BIT6 ; 
+        Data8 &= ~(UINT8)BIT6 ;

         Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);   // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
         Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);   // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);

-        Data8 |= BIT6 ; 
+        Data8 |= BIT6 ;

         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);       // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;
         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);       // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;


@@ -586,7 +586,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);

-        Data8 |= BIT6 ; 
+        Data8 |= BIT6 ;

         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);       // PCIE_RST#_LAN, GPIO25
         Status = AGESA_SUCCESS;
         break;
         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);       // PCIE_RST#_LAN, GPIO25
         Status = AGESA_SUCCESS;
         break;

diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h
index b187fa25c04de482b925868da3ce9bf9fa478da5..b7c78830b4fd9b372d9b850d1c3ec5f171ca8120 100644 (file)
--- a/src/mainboard/amd/persimmon/BiosCallOuts.h
+++ b/src/mainboard/amd/persimmon/BiosCallOuts.h
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

- 
+

 #ifndef _BIOS_CALLOUT_H_
 #define _BIOS_CALLOUT_H_
 
 #ifndef _BIOS_CALLOUT_H_
 #define _BIOS_CALLOUT_H_
 

diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c
index 59d31efb777ee298695ff32c2ee2b22b2d2ba8ba..b0389b82d9bd7e711562d42c5cbd1e96564bddd6 100644 (file)
--- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c
+++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c
@@ -86,7 +86,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
           DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
           PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
           PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
           DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
           PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
           PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)

-        }       
+        }

 };
 
 PCIe_DDI_DESCRIPTOR DdiList [] = {
 };
 
 PCIe_DDI_DESCRIPTOR DdiList [] = {


@@ -118,8 +118,8 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
   //
   // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
   //
   //
   // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
   //

-  AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  + 
-                                         sizeof (PCIe_PORT_DESCRIPTOR) * 5 + 
+  AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  +
+                                         sizeof (PCIe_PORT_DESCRIPTOR) * 5 +

                                          sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
 
   AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
                                          sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
 
   AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;


@@ -127,10 +127,10 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
   Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
   if ( Status!= AGESA_SUCCESS) {
     // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
   Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
   if ( Status!= AGESA_SUCCESS) {
     // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR

-    ASSERT(FALSE); 
+    ASSERT(FALSE);

     return;
   }
     return;
   }

-  
+

   BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
   BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);


@@ -138,7 +138,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
   BrazosPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
   BrazosPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;

- 
+

   LibAmdMemFill (BrazosPcieComplexListPtr,
                    0,
                    sizeof (PCIe_COMPLEX_DESCRIPTOR),
   LibAmdMemFill (BrazosPcieComplexListPtr,
                    0,
                    sizeof (PCIe_COMPLEX_DESCRIPTOR),


@@ -148,7 +148,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
                    0,
                    sizeof (PCIe_PORT_DESCRIPTOR) * 5,
                    &InitEarly->StdHeader);
                    0,
                    sizeof (PCIe_PORT_DESCRIPTOR) * 5,
                    &InitEarly->StdHeader);

-     
+

   LibAmdMemFill (BrazosPcieDdiPtr,
                    0,
                    sizeof (PCIe_DDI_DESCRIPTOR) * 2,
   LibAmdMemFill (BrazosPcieDdiPtr,
                    0,
                    sizeof (PCIe_DDI_DESCRIPTOR) * 2,


@@ -162,7 +162,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
 
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
 

-  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; 
-  InitEarly->GnbConfig.PsppPolicy      = 0; 
+  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
+  InitEarly->GnbConfig.PsppPolicy      = 0;

 }
 
 }
 

diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h
index f35d8db723c464a538c7b20f78e3947365e2d5ed..b51089f7f643cdc51ebbc15bf184ca99ca309e76 100644 (file)
--- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h
+++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h
@@ -25,42 +25,42 @@
 #include "amdlib.h"
 
 //GNB GPP Port4
 #include "amdlib.h"
 
 //GNB GPP Port4

-#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable

 #define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT4_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT4_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1

-#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)

                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port5
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port5

-#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable

 #define GNB_GPP_PORT5_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT5_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT5_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT5_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1

-#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)

                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port6
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port6

-#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable

 #define GNB_GPP_PORT6_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT6_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT6_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT6_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1

-#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)

                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port7
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port7

-#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable

 #define GNB_GPP_PORT7_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT7_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT7_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT7_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1

-#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)

                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port8
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port8

-#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable

 #define GNB_GPP_PORT8_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT8_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT8_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT8_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1

-#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)

                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 


@@ -68,5 +68,5 @@ VOID
 OemCustomizeInitEarly (
   IN  OUT AMD_EARLY_PARAMS    *InitEarly
   );
 OemCustomizeInitEarly (
   IN  OUT AMD_EARLY_PARAMS    *InitEarly
   );

-  
+

 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H
 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H

diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c
index 74aa73d49fe0e334deaccfa7b691be7901d65585..9d9f8641419acdd3ed3de9624dfe89d89c796721 100644 (file)
--- a/src/mainboard/amd/persimmon/agesawrapper.c
+++ b/src/mainboard/amd/persimmon/agesawrapper.c
@@ -86,11 +86,11 @@ agesawrapper_amdinitcpuio (
   UINT32                        PciData;
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;
   UINT32                        PciData;
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;

-  
+

   /* Enable legacy video routing: D18F1xF4 VGA Enable */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
   PciData = 1;
   /* Enable legacy video routing: D18F1xF4 VGA Enable */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
   PciData = 1;

-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

 
   /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
    * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
 
   /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
    * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are


@@ -99,21 +99,21 @@ agesawrapper_amdinitcpuio (
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
   PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
   PciData |= 1 << 7;    // set NP (non-posted) bit
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
   PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
   PciData |= 1 << 7;    // set NP (non-posted) bit

-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
   PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
   PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000

-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-   
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+

   /* Map the remaining PCI hole as posted MMIO */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
   PciData = 0x00FECF00; // last address before non-posted range
   /* Map the remaining PCI hole as posted MMIO */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
   PciData = 0x00FECF00; // last address before non-posted range

-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

   LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
   MsrReg = (MsrReg >> 8) | 3;
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
   PciData = (UINT32)MsrReg;
   LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
   MsrReg = (MsrReg >> 8) | 3;
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
   PciData = (UINT32)MsrReg;

-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-   
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+

   /* Send all IO (0000-FFFF) to southbridge. */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
   PciData = 0x0000F000;
   /* Send all IO (0000-FFFF) to southbridge. */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
   PciData = 0x0000F000;


@@ -135,7 +135,7 @@ agesawrapper_amdinitmmio (
   UINT32                        PciData;
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;
   UINT32                        PciData;
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;

-  
+

   UINT8                         BusRangeVal = 0;
   UINT8                         BusNum;
   UINT8                         Index;
   UINT8                         BusRangeVal = 0;
   UINT8                         BusNum;
   UINT8                         Index;


@@ -166,10 +166,10 @@ agesawrapper_amdinitmmio (
   /* Set Ontario Link Data */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
   PciData = 0x01308002;
   /* Set Ontario Link Data */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
   PciData = 0x01308002;

-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
   PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
   PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;

-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

 
   Status = AGESA_SUCCESS;
   return (UINT32)Status;
 
   Status = AGESA_SUCCESS;
   return (UINT32)Status;


@@ -313,7 +313,7 @@ agesawrapper_amdinitenv (
   /* Initialize Subordinate Bus Number and Secondary Bus Number
    * In platform BIOS this address is allocated by PCI enumeration code
      Modify D1F0x18
   /* Initialize Subordinate Bus Number and Secondary Bus Number
    * In platform BIOS this address is allocated by PCI enumeration code
      Modify D1F0x18

-   */  
+   */

   PciAddress.Address.Bus = 0;
   PciAddress.Address.Device = 1;
   PciAddress.Address.Function = 0;
   PciAddress.Address.Bus = 0;
   PciAddress.Address.Device = 1;
   PciAddress.Address.Function = 0;


@@ -480,10 +480,10 @@ agesawrapper_amdinitlate (
   return (UINT32)Status;
 }
 
   return (UINT32)Status;
 }
 

-UINT32 
+UINT32

 agesawrapper_amdlaterunaptask (
 agesawrapper_amdlaterunaptask (

-  UINT32 Func, 
-  UINT32 Data, 
+  UINT32 Func,
+  UINT32 Data,

   VOID *ConfigPtr
   )
 {
   VOID *ConfigPtr
   )
 {

diff --git a/src/mainboard/amd/persimmon/dimmSpd.c b/src/mainboard/amd/persimmon/dimmSpd.c
index 9da0e0e3a8984fadf014a6434f0c8e9d2af85ce0..2bd27d6f4253662b157967e1bc373f76a3014f99 100644 (file)
--- a/src/mainboard/amd/persimmon/dimmSpd.c
+++ b/src/mainboard/amd/persimmon/dimmSpd.c
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

- 
+

 #include "Porting.h"
 #include "AGESA.h"
 #include "amdlib.h"
 #include "Porting.h"
 #include "AGESA.h"
 #include "amdlib.h"


@@ -55,7 +55,7 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
    UINT64 limit;
 
    address |= 1; // set read bit
    UINT64 limit;
 
    address |= 1; // set read bit

-   
+

    __outbyte (iobase + 0, 0xFF);                // clear error status
    __outbyte (iobase + 1, 0x1F);                // clear error status
    __outbyte (iobase + 3, offset);              // offset in eeprom
    __outbyte (iobase + 0, 0xFF);                // clear error status
    __outbyte (iobase + 1, 0x1F);                // clear error status
    __outbyte (iobase + 3, offset);              // offset in eeprom


@@ -112,7 +112,7 @@ static int readSmbusByte (int iobase, int address, char *buffer)
  *
  * readspd - Read one or more SPD bytes from a DIMM.
  *           Start with offset zero and read sequentially.
  *
  * readspd - Read one or more SPD bytes from a DIMM.
  *           Start with offset zero and read sequentially.

- *           Optimization relies on autoincrement to avoid 
+ *           Optimization relies on autoincrement to avoid

  *           sending offset for every byte.
  *          Reads 128 bytes in 7-8 ms at 400 KHz.
  */
  *           sending offset for every byte.
  *          Reads 128 bytes in 7-8 ms at 400 KHz.
  */


@@ -131,7 +131,7 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
       error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
       if (error) return error;
       }
       error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
       if (error) return error;
       }

-   
+

    return 0;
    }
 
    return 0;
    }
 


@@ -154,11 +154,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
    {
    int spdAddress, ioBase;
 
    {
    int spdAddress, ioBase;
 

-   if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR; 
-   if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR; 
+   if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR;
+   if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR;

    if (info->DimmId       >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
    if (info->DimmId       >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;

-   
-   spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; 
+
+   spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];

    if (spdAddress == 0) return AGESA_ERROR;
    ioBase = 0xB00;
    setupFch (ioBase);
    if (spdAddress == 0) return AGESA_ERROR;
    ioBase = 0xB00;
    setupFch (ioBase);

diff --git a/src/mainboard/amd/persimmon/dimmSpd.h b/src/mainboard/amd/persimmon/dimmSpd.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c
index 4bc5b482186e3df8cc5b6f5dcbd531e8d1e538b7..2d280235747f179ff1bc847f9746fb7c5476e3f3 100644 (file)
--- a/src/mainboard/amd/persimmon/get_bus_conf.c
+++ b/src/mainboard/amd/persimmon/get_bus_conf.c
@@ -69,22 +69,22 @@ void get_bus_conf(void)
  * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
  * but functionally within the coreboot model, this is the best place to make the
  * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
  * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
  * but functionally within the coreboot model, this is the best place to make the
  * call.  The logically correct place to call AmdInitLate is after PCI scan is done,

- * after the decision about S3 resume is made, and before the system tables are 
- * written into RAM.  The routine that is responsible for writing the tables is 
- * "write_tables", called near the end of "hardwaremain".  There is no platform 
- * specific entry point between the S3 resume decision point and the call to 
- * "write_tables", and the next platform specific entry points are the calls to 
- * the ACPI table write functions.  The first of ose would seem to be the right 
- * place, but other table write functions, e.g. the PIRQ table write function, are 
+ * after the decision about S3 resume is made, and before the system tables are
+ * written into RAM.  The routine that is responsible for writing the tables is
+ * "write_tables", called near the end of "hardwaremain".  There is no platform
+ * specific entry point between the S3 resume decision point and the call to
+ * "write_tables", and the next platform specific entry points are the calls to
+ * the ACPI table write functions.  The first of ose would seem to be the right
+ * place, but other table write functions, e.g. the PIRQ table write function, are

  * called before the ACPI tables are written.  This routine is called at the beginning
  * of each of the write functions called prior to the ACPI write functions, so this
  * becomes the best place for this call.
  */
  * called before the ACPI tables are written.  This routine is called at the beginning
  * of each of the write functions called prior to the ACPI write functions, so this
  * becomes the best place for this call.
  */

-  status = agesawrapper_amdinitlate(); 
+  status = agesawrapper_amdinitlate();

   if(status) {
     printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
   }
   if(status) {
     printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
   }

-       
+

   sbdn_sb800 = 0;
 
   for (i = 0; i < 3; i++) {
   sbdn_sb800 = 0;
 
   for (i = 0; i < 3; i++) {

diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index a3b4b5c95e1bd6dd498b3f58b3fb954315f85eb2..546d9bd393a423f0d55861b13c5802b18622ecf9 100644 (file)
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -61,10 +61,10 @@ static void *smp_write_config_table(void *v)
   mptable_write_buses(mc, NULL, &bus_isa);
 
   /* I/O APICs:   APIC ID Version State   Address */
   mptable_write_buses(mc, NULL, &bus_isa);
 
   /* I/O APICs:   APIC ID Version State   Address */

-  
+

   u32 dword;
   u8 byte;
   u32 dword;
   u8 byte;

-    
+

   ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
   dword &= 0xFFFFFFF0;
   smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
   ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
   dword &= 0xFFFFFFF0;
   smp_write_ioapic(mc, apicid_sb800, 0x21, dword);


@@ -108,7 +108,7 @@ static void *smp_write_config_table(void *v)
   /* PCI_INT(0x0, 0x14, 0x2, 0x12); */
 
   /* on board NIC & Slot PCIE.  */
   /* PCI_INT(0x0, 0x14, 0x2, 0x12); */
 
   /* on board NIC & Slot PCIE.  */

-  
+

   /* PCI slots */
   /* PCI_SLOT 0. */
   PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
   /* PCI slots */
   /* PCI_SLOT 0. */
   PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);

diff --git a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
index 126b4643052fbf7c1ddf3cc4c6ecabb8496597f0..65ac2e641cbe9fad293a749db745793b402f9807 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
@@ -57,7 +57,7 @@ void hardwaremain(int ret_addr)
        train_ram(id.nodeid, sysinfo, sysinfox);
 
        /*
        train_ram(id.nodeid, sysinfo, sysinfox);
 
        /*

-        * go back, but can not use stack any more, because we 
+        * go back, but can not use stack any more, because we

         * only keep ret_addr and can not restore esp, and ebp.
         */
 
         * only keep ret_addr and can not restore esp, and ebp.
         */
 

diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.h b/src/mainboard/amd/torpedo/BiosCallOuts.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/amd/torpedo/OptionsIds.h b/src/mainboard/amd/torpedo/OptionsIds.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcie.c b/src/mainboard/amd/torpedo/PlatformGnbPcie.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h
old mode 100755 (executable)
new mode 100644 (file)
index f35d8db..b51089f
--- a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h
+++ b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h
@@ -25,42 +25,42 @@
 #include "amdlib.h"
 
 //GNB GPP Port4
 #include "amdlib.h"
 
 //GNB GPP Port4

-#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable

 #define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT4_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT4_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1

-#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)

                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port5
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port5

-#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable

 #define GNB_GPP_PORT5_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT5_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT5_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT5_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1

-#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)

                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port6
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port6

-#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable

 #define GNB_GPP_PORT6_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT6_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT6_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT6_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1

-#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)

                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port7
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port7

-#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable

 #define GNB_GPP_PORT7_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT7_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT7_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT7_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1

-#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)

                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port8
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port8

-#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable

 #define GNB_GPP_PORT8_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT8_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT8_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT8_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1

-#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)

                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 


@@ -68,5 +68,5 @@ VOID
 OemCustomizeInitEarly (
   IN  OUT AMD_EARLY_PARAMS    *InitEarly
   );
 OemCustomizeInitEarly (
   IN  OUT AMD_EARLY_PARAMS    *InitEarly
   );

-  
+

 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H
 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H

diff --git a/src/mainboard/amd/torpedo/acpi_tables.c b/src/mainboard/amd/torpedo/acpi_tables.c
old mode 100755 (executable)
new mode 100644 (file)
index 7f4f2d9..4710b57
--- a/src/mainboard/amd/torpedo/acpi_tables.c
+++ b/src/mainboard/amd/torpedo/acpi_tables.c
@@ -62,13 +62,13 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 
 unsigned long acpi_fill_madt(unsigned long current)
 {
 
 unsigned long acpi_fill_madt(unsigned long current)
 {

-  
+

   /* create all subtables for processors */
   current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
   current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1);
   current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 2);
   current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 3);
   /* create all subtables for processors */
   current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
   current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1);
   current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 2);
   current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 3);

-  
+

   /* Write SB900 IOAPIC, only one */
   current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb900,
              IO_APIC_ADDR, 0);
   /* Write SB900 IOAPIC, only one */
   current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb900,
              IO_APIC_ADDR, 0);


@@ -77,7 +77,7 @@ unsigned long acpi_fill_madt(unsigned long current)
             current, 0, 0, 2, 0);
   current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
             current, 0, 9, 9, 0xF);
             current, 0, 0, 2, 0);
   current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
             current, 0, 9, 9, 0xF);

-  
+

   /* 0: mean bus 0--->ISA */
   /* 0: PIC 0 */
   /* 2: APIC 2 */
   /* 0: mean bus 0--->ISA */
   /* 0: PIC 0 */
   /* 2: APIC 2 */

diff --git a/src/mainboard/amd/torpedo/agesawrapper.c b/src/mainboard/amd/torpedo/agesawrapper.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/amd/torpedo/agesawrapper.h b/src/mainboard/amd/torpedo/agesawrapper.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/amd/torpedo/chip.h b/src/mainboard/amd/torpedo/chip.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/amd/torpedo/dimmSpd.c b/src/mainboard/amd/torpedo/dimmSpd.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/amd/torpedo/dimmSpd.h b/src/mainboard/amd/torpedo/dimmSpd.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/amd/torpedo/get_bus_conf.c b/src/mainboard/amd/torpedo/get_bus_conf.c
old mode 100755 (executable)
new mode 100644 (file)
index f9b4c84..13019ff
--- a/src/mainboard/amd/torpedo/get_bus_conf.c
+++ b/src/mainboard/amd/torpedo/get_bus_conf.c
@@ -79,23 +79,23 @@ void get_bus_conf(void)
  * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
  * but functionally within the coreboot model, this is the best place to make the
  * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
  * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
  * but functionally within the coreboot model, this is the best place to make the
  * call.  The logically correct place to call AmdInitLate is after PCI scan is done,

- * after the decision about S3 resume is made, and before the system tables are 
- * written into RAM.  The routine that is responsible for writing the tables is 
- * "write_tables", called near the end of "hardwaremain".  There is no platform 
- * specific entry point between the S3 resume decision point and the call to 
- * "write_tables", and the next platform specific entry points are the calls to 
- * the ACPI table write functions.  The first of ose would seem to be the right 
- * place, but other table write functions, e.g. the PIRQ table write function, are 
+ * after the decision about S3 resume is made, and before the system tables are
+ * written into RAM.  The routine that is responsible for writing the tables is
+ * "write_tables", called near the end of "hardwaremain".  There is no platform
+ * specific entry point between the S3 resume decision point and the call to
+ * "write_tables", and the next platform specific entry points are the calls to
+ * the ACPI table write functions.  The first of ose would seem to be the right
+ * place, but other table write functions, e.g. the PIRQ table write function, are

  * called before the ACPI tables are written.  This routine is called at the beginning
  * of each of the write functions called prior to the ACPI write functions, so this
  * becomes the best place for this call.
  */
  * called before the ACPI tables are written.  This routine is called at the beginning
  * of each of the write functions called prior to the ACPI write functions, so this
  * becomes the best place for this call.
  */

-  status = agesawrapper_amdinitlate(); 
+  status = agesawrapper_amdinitlate();

   if(status) {
     printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
   }
   printk(BIOS_DEBUG, "Got past agesawrapper_amdinitlate\n");
   if(status) {
     printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
   }
   printk(BIOS_DEBUG, "Got past agesawrapper_amdinitlate\n");

-  
+

   sbdn_sb900 = 0;
 
   for (i = 0; i < 3; i++) {
   sbdn_sb900 = 0;
 
   for (i = 0; i < 3; i++) {

diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c
old mode 100755 (executable)
new mode 100644 (file)
index 14dcd2c..2633fb5
--- a/src/mainboard/amd/torpedo/gpio.c
+++ b/src/mainboard/amd/torpedo/gpio.c
@@ -21,7 +21,7 @@
  *                             M O D U L E S    U S E D
  *----------------------------------------------------------------------------------------
  */
  *                             M O D U L E S    U S E D
  *----------------------------------------------------------------------------------------
  */

- 
+

 #include "Filecode.h"
 #include "Hudson-2.h"
 #include "AmdSbLib.h"
 #include "Filecode.h"
 #include "Hudson-2.h"
 #include "AmdSbLib.h"


@@ -63,12 +63,12 @@
  *----------------------------------------------------------------------------------------
  */
        void gpioEarlyInit (void);
  *----------------------------------------------------------------------------------------
  */
        void gpioEarlyInit (void);

- 
+

 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */

- 
+

 /*---------------------------------------------------------------------------------------
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
 /*---------------------------------------------------------------------------------------
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------


@@ -98,7 +98,7 @@ gpioEarlyInit(
        Data8 |= BIT0;
        WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
        // Get HUDSON MMIO Base (AcpiMmioAddr)
        Data8 |= BIT0;
        WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
        // Get HUDSON MMIO Base (AcpiMmioAddr)

-       ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8);  
+       ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8);

        Data16 = Data8 << 8;
        ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8);
        Data16 |= Data8;
        Data16 = Data8 << 8;
        ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8);
        Data16 |= Data8;


@@ -113,14 +113,14 @@ gpioEarlyInit(
        Data8 = Mmio8_G (GpioMmioAddr, GPIO_30);
        StripInfo = (Data8 & BIT7) >> 7;
        Data8 = Mmio8_G (GpioMmioAddr, GPIO_31);
        Data8 = Mmio8_G (GpioMmioAddr, GPIO_30);
        StripInfo = (Data8 & BIT7) >> 7;
        Data8 = Mmio8_G (GpioMmioAddr, GPIO_31);

-       StripInfo |= (Data8 & BIT7) >> 6;         
-       if (StripInfo < boardRevC) {            // for old board. Rev B 
+       StripInfo |= (Data8 & BIT7) >> 6;
+       if (StripInfo < boardRevC) {            // for old board. Rev B

                Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3);                // function 3
                Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3);                // function 3

-               Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0);                // function 0    
+               Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0);                // function 0

        }
        for (Index = 0; Index < MAX_GPIO_NO; Index++) {
                if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) {
        }
        for (Index = 0; Index < MAX_GPIO_NO; Index++) {
                if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) {

-                       if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) {  
+                       if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) {

                                // Configure multi-funtion
                                Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio));
                        }
                                // Configure multi-funtion
                                Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio));
                        }


@@ -138,7 +138,7 @@ gpioEarlyInit(
                // Configure GEVENT
                if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) {
                        SmiMmioAddr = AcpiMmioAddr + SMI_BASE;
                // Configure GEVENT
                if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) {
                        SmiMmioAddr = AcpiMmioAddr + SMI_BASE;

-    
+

                        andMask32 = ~(1 << (Index - GEVENT_00));
 
                        //EventEnable: 0-Disable, 1-Enable
                        andMask32 = ~(1 << (Index - GEVENT_00));
 
                        //EventEnable: 0-Disable, 1-Enable


@@ -159,12 +159,12 @@ gpioEarlyInit(
                        //SciMap: 00000b ~ 11111b
                        RegIndex8=(u8)((Index - GEVENT_00) >> 2);
                        Data8=(u8)(((Index - GEVENT_00) & 0x3) * 8);
                        //SciMap: 00000b ~ 11111b
                        RegIndex8=(u8)((Index - GEVENT_00) >> 2);
                        Data8=(u8)(((Index - GEVENT_00) & 0x3) * 8);

-                       Mmio32_And_Or     (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8));        
-      
+                       Mmio32_And_Or     (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8));
+

                        //SmiTrig: 0-Active Low, 1-Active High
                        Mmio32_And_Or     (SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)));
                        //SmiTrig: 0-Active Low, 1-Active High
                        Mmio32_And_Or     (SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)));

-    
-                       //SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 
+
+                       //SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13

                        RegIndex8=(u8)((Index - GEVENT_00) >> 4);
                        Data8=(u8)(((Index - GEVENT_00) & 0xF) * 2);
                        Mmio32_And_Or     (SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8));
                        RegIndex8=(u8)((Index - GEVENT_00) >> 4);
                        Data8=(u8)(((Index - GEVENT_00) & 0xF) * 2);
                        Mmio32_And_Or     (SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8));


@@ -180,7 +180,7 @@ gpioEarlyInit(
        //      GPIO45: Output for MXM Power Enable, active HIGH
        //      GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable
        //      GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO
        //      GPIO45: Output for MXM Power Enable, active HIGH
        //      GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable
        //      GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO

-       //      
+       //

                // set INTE#/GPIO32 as GPO for PCIE_SW
                RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1);      // GPIO
                RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0);       // GPO
                // set INTE#/GPIO32 as GPO for PCIE_SW
                RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1);      // GPIO
                RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0);       // GPO


@@ -224,7 +224,7 @@ gpioEarlyInit(
                //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20));
                //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20)));
 
                //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20));
                //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20)));
 

-               // check if there any GFX card          
+               // check if there any GFX card

                Flags = 0;
                // Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL);
                // Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09);
                Flags = 0;
                // Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL);
                // Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09);


@@ -244,13 +244,13 @@ gpioEarlyInit(
                        RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0);
 
                        // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH
                        RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0);
 
                        // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH

-                       RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6);        
-                   
-                       //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)    
+                       RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6);
+
+                       //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)

                        SbStall (10000);
 
                        // Write the GPIO55(MXM_PWR_EN) to enable the integrated power module
                        SbStall (10000);
 
                        // Write the GPIO55(MXM_PWR_EN) to enable the integrated power module

-                       RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6);        
+                       RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6);

 
                        //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
                        // WAIT POWER READY: GPIO28 (MXM_PWRGD)
 
                        //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
                        // WAIT POWER READY: GPIO28 (MXM_PWRGD)


@@ -261,7 +261,7 @@ gpioEarlyInit(
                                ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
                        }
                        // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset
                                ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
                        }
                        // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset

-                   //  RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6);        
+                   //  RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6);

                }
                else
                {
                }
                else
                {


@@ -270,9 +270,9 @@ gpioEarlyInit(
 
                        //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
                        SbStall (10000);
 
                        //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
                        SbStall (10000);

-       
+

                        // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down
                        // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down

-                       RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0);                                                                   
+                       RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0);

                }
 
        //
                }
 
        //


@@ -288,7 +288,7 @@ gpioEarlyInit(
                RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6);       // output HIGH
                RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3);       // pullup DISABLE
 
                RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6);       // output HIGH
                RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3);       // pullup DISABLE
 

-               // Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: 
+               // Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN:

                RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1);          // GPIO
 //             RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0);           // GPO
                RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6);        // output HIGH
                RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1);          // GPIO
 //             RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0);           // GPO
                RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6);        // output HIGH


@@ -298,7 +298,7 @@ gpioEarlyInit(
                // set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ#
                RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0);          // CLK_REQ3#
                RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0);       // Enable GPP_CLK3
                // set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ#
                RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0);          // CLK_REQ3#
                RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0);       // Enable GPP_CLK3

-               
+

        //
        // APU GPP1: WUSB
        //      GPIO1: MPCIE_RST2#, LOW active
        //
        // APU GPP1: WUSB
        //      GPIO1: MPCIE_RST2#, LOW active


@@ -354,7 +354,7 @@ gpioEarlyInit(
        //      GPIO41: CLKREQ#
        //      Clock: GPP_CLK8
        //
        //      GPIO41: CLKREQ#
        //      Clock: GPP_CLK8
        //

-               // Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: 
+               // Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON:

                RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2);         // GPIO
 //             RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0);          // GPO
                RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6);       // output HIGH
                RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2);         // GPIO
 //             RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0);          // GPO
                RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6);       // output HIGH


@@ -382,8 +382,8 @@ gpioEarlyInit(
                if (!CONFIG_ONBOARD_LAN)
                { // 1 - DISABLED
                        RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0);      // LOM_POWER off
                if (!CONFIG_ONBOARD_LAN)
                { // 1 - DISABLED
                        RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0);      // LOM_POWER off

-                       RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0);   
-                       RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3);    // PULL UP - DISABLED       
+                       RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0);
+                       RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3);    // PULL UP - DISABLED

                        RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0);     // Disable GPP_CLK3
                }
 //             else
                        RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0);     // Disable GPP_CLK3
                }
 //             else


@@ -409,11 +409,11 @@ gpioEarlyInit(
 //             else
 //             { // 0 - AUTO
 //                     // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=1 (output HIGH)
 //             else
 //             { // 0 - AUTO
 //                     // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=1 (output HIGH)

-//                     RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); 
+//                     RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6);

 //                     RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3);
 //
 //                     RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6);
 //                     RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3);
 //
 //                     RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6);

-//                     RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3);        
+//                     RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3);

 //             }
 
 //
 //             }
 
 //


@@ -430,7 +430,7 @@ gpioEarlyInit(
                RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0);
                RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0);
                RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3);   // PULL_UP DISABLE
                RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0);
                RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0);
                RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3);   // PULL_UP DISABLE

-               RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0);    // DISABLE GPP_CLK7  
+               RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0);    // DISABLE GPP_CLK7

                RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0);  // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
                }
 //     }
                RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0);  // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
                }
 //     }


@@ -447,25 +447,25 @@ if (!CONFIG_ONBOARD_BLUETOOTH) {
 }
 
 //
 }
 
 //

-// WebCam control: 
+// WebCam control:

 //    amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE
 //       GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF
 //
 if (!CONFIG_ONBOARD_WEBCAM) {
 //-    if (SystemConfiguration.amdWebCam == 1) {
                RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6);
 //    amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE
 //       GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF
 //
 if (!CONFIG_ONBOARD_WEBCAM) {
 //-    if (SystemConfiguration.amdWebCam == 1) {
                RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6);

-//-    }  
+//-    }

 }
 
 //
 }
 
 //

-// Travis enable: 
+// Travis enable:

 //    amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE
 //           GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE
 //
 if (!CONFIG_ONBOARD_TRAVIS) {
 //-    if (SystemConfiguration.amdTravisCtrl == 0) {
                RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6);
 //    amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE
 //           GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE
 //
 if (!CONFIG_ONBOARD_TRAVIS) {
 //-    if (SystemConfiguration.amdTravisCtrl == 0) {
                RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6);

-//-    } 
+//-    }

 }
 
 //
 }
 
 //

diff --git a/src/mainboard/amd/torpedo/gpio.h b/src/mainboard/amd/torpedo/gpio.h
old mode 100755 (executable)
new mode 100644 (file)
index 159394e..45394ef
--- a/src/mainboard/amd/torpedo/gpio.h
+++ b/src/mainboard/amd/torpedo/gpio.h
@@ -21,8 +21,8 @@
  *                             M O D U L E S    U S E D
  *----------------------------------------------------------------------------------------
  */
  *                             M O D U L E S    U S E D
  *----------------------------------------------------------------------------------------
  */

- 
-  
+
+

 #ifndef _GPIO_H_
 #define _GPIO_H_
 
 #ifndef _GPIO_H_
 #define _GPIO_H_
 


@@ -121,8 +121,8 @@
 #define GPIO_18_SELECT      FUNCTION0+NonGpio   // NOT USED
 #define GPIO_19_SELECT      FUNCTION1           // For LASSO_DET# detection when Gevent14# is asserted.
 #define GPIO_20_SELECT      FUNCTION1           // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option)
 #define GPIO_18_SELECT      FUNCTION0+NonGpio   // NOT USED
 #define GPIO_19_SELECT      FUNCTION1           // For LASSO_DET# detection when Gevent14# is asserted.
 #define GPIO_20_SELECT      FUNCTION1           // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option)

-#define GPIO_21_SELECT      FUNCTION1           // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) 
-#define GPIO_22_SELECT      FUNCTION1           // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE 
+#define GPIO_21_SELECT      FUNCTION1           // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option)
+#define GPIO_22_SELECT      FUNCTION1           // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE

                                                 //      1:BATTERY IS FINE(DEFAULT)
                                                 //      0:BATTERY IS LOW
 #define GPIO_23_SELECT      FUNCTION1          // CODEC_ON.1: CODEC ON (default)0: CODEC OFF
                                                 //      1:BATTERY IS FINE(DEFAULT)
                                                 //      0:BATTERY IS LOW
 #define GPIO_23_SELECT      FUNCTION1          // CODEC_ON.1: CODEC ON (default)0: CODEC OFF


@@ -143,7 +143,7 @@
                                                 //      0:USB3.0 I/F in Express CARD
                                                 //      1:PCIE I/F  in Express CARD detection
 #define GPIO_34_SELECT      FUNCTION1           // WEBCAM_ON#. 0: ON (default) 1: OFF
                                                 //      0:USB3.0 I/F in Express CARD
                                                 //      1:PCIE I/F  in Express CARD detection
 #define GPIO_34_SELECT      FUNCTION1           // WEBCAM_ON#. 0: ON (default) 1: OFF

-#define GPIO_35_SELECT      FUNCTION1           // ODD_DA_INTH# 
+#define GPIO_35_SELECT      FUNCTION1           // ODD_DA_INTH#

 #define GPIO_36_SELECT      FUNCTION0+NonGpio   // PCICLK FOR KBC
 #define GPIO_37_SELECT      FUNCTION0+NonGpio   // NOT USED
 #define GPIO_38_SELECT      FUNCTION0+NonGpio   // NOT USED
 #define GPIO_36_SELECT      FUNCTION0+NonGpio   // PCICLK FOR KBC
 #define GPIO_37_SELECT      FUNCTION0+NonGpio   // NOT USED
 #define GPIO_38_SELECT      FUNCTION0+NonGpio   // NOT USED


@@ -152,7 +152,7 @@
 #define GPIO_41_SELECT      FUNCTION1+NonGpio   // 1394 CLK REQ#
 #define GPIO_42_SELECT      FUNCTION1+NonGpio   // X4 GPP CLK REQ#
 #define GPIO_43_SELECT      FUNCTION0+NonGpio   // SMBUS0, CLOCK
 #define GPIO_41_SELECT      FUNCTION1+NonGpio   // 1394 CLK REQ#
 #define GPIO_42_SELECT      FUNCTION1+NonGpio   // X4 GPP CLK REQ#
 #define GPIO_43_SELECT      FUNCTION0+NonGpio   // SMBUS0, CLOCK

-#define GPIO_44_SELECT      FUNCTION1+NonGpio   // PEGPIO0, RESET THE MXM MODULE 
+#define GPIO_44_SELECT      FUNCTION1+NonGpio   // PEGPIO0, RESET THE MXM MODULE

 #define GPIO_45_SELECT      FUNCTION2+NonGpio   // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF
 #define GPIO_46_SELECT      FUNCTION1+NonGpio   // USB3.0_CLKREQ#
 #define GPIO_47_SELECT      FUNCTION0+NonGpio   // SMBUS0, DATA
 #define GPIO_45_SELECT      FUNCTION2+NonGpio   // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF
 #define GPIO_46_SELECT      FUNCTION1+NonGpio   // USB3.0_CLKREQ#
 #define GPIO_47_SELECT      FUNCTION0+NonGpio   // SMBUS0, DATA


@@ -215,7 +215,7 @@
 #define GPIO_101_SELECT     FUNCTION1           // LPC_PD#/GEVENT5# -> hotplug of express card, low active
 #define GPIO_102_SELECT     FUNCTION0+NonGpio   // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED,
                                                 // there is a confliction to IR function when this pin is as a GEVENT.
 #define GPIO_101_SELECT     FUNCTION1           // LPC_PD#/GEVENT5# -> hotplug of express card, low active
 #define GPIO_102_SELECT     FUNCTION0+NonGpio   // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED,
                                                 // there is a confliction to IR function when this pin is as a GEVENT.

-#define GPIO_103_SELECT     FUNCTION0+NonGpio   // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, 
+#define GPIO_103_SELECT     FUNCTION0+NonGpio   // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD,

                                                 // special pin difination for SB900 VGA OUTPUT, high active,
                                                 // VGA power for Hudson-M2 will be down when it was asserted.
 #define GPIO_104_SELECT     FUNCTION0           // WAKE#/GEVENT8# -> WAKEUP, low active
                                                 // special pin difination for SB900 VGA OUTPUT, high active,
                                                 // VGA power for Hudson-M2 will be down when it was asserted.
 #define GPIO_104_SELECT     FUNCTION0           // WAKE#/GEVENT8# -> WAKEUP, low active


@@ -223,7 +223,7 @@
 #define GPIO_106_SELECT     FUNCTION0           // GBE_LED2/GEVENT10# -> GBE_LED2
 #define GPIO_107_SELECT     FUNCTION0+NonGpio   // GBE_STAT0/GEVENT11# -> GBE_STAT0
 #define GPIO_108_SELECT     FUNCTION2           // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active
 #define GPIO_106_SELECT     FUNCTION0           // GBE_LED2/GEVENT10# -> GBE_LED2
 #define GPIO_107_SELECT     FUNCTION0+NonGpio   // GBE_STAT0/GEVENT11# -> GBE_STAT0
 #define GPIO_108_SELECT     FUNCTION2           // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active

-                                                // [option for SPI_TPM_CS# in Hudson-M2 A12)] 
+                                                // [option for SPI_TPM_CS# in Hudson-M2 A12)]

 #define GPIO_109_SELECT     FUNCTION0           // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) &
                                                 //  USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time
 #define GPIO_110_SELECT     FUNCTION2           // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect,
 #define GPIO_109_SELECT     FUNCTION0           // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) &
                                                 //  USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time
 #define GPIO_110_SELECT     FUNCTION2           // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect,


@@ -238,7 +238,7 @@
 #define GPIO_115_SELECT     FUNCTION0           // SYS_RESET#/GEVENT19# -> SYS_RST#
 #define GPIO_116_SELECT     FUNCTION0           // R_RX1/GEVENT20# -> IR INPUT
 #define GPIO_117_SELECT     FUNCTION1+NonGpio   // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1
 #define GPIO_115_SELECT     FUNCTION0           // SYS_RESET#/GEVENT19# -> SYS_RST#
 #define GPIO_116_SELECT     FUNCTION0           // R_RX1/GEVENT20# -> IR INPUT
 #define GPIO_117_SELECT     FUNCTION1+NonGpio   // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1

-#define GPIO_118_SELECT     FUNCTION1           // RI#/GEVENT22# -> LID_CLOSED# 
+#define GPIO_118_SELECT     FUNCTION1           // RI#/GEVENT22# -> LID_CLOSED#

 #define GPIO_119_SELECT     FUNCTION0           // LPC_SMI#/GEVENT23# -> EC_SMI
 #define GPIO_120_SELECT     FUNCTION0+NonGpio
 #define GPIO_121_SELECT     FUNCTION0+NonGpio
 #define GPIO_119_SELECT     FUNCTION0           // LPC_SMI#/GEVENT23# -> EC_SMI
 #define GPIO_120_SELECT     FUNCTION0+NonGpio
 #define GPIO_121_SELECT     FUNCTION0+NonGpio


@@ -287,7 +287,7 @@
 #define GPIO_162_SELECT     FUNCTION0+NonGpio   // SPI ROM
 #define GPIO_163_SELECT     FUNCTION0+NonGpio   // SPI ROM
 #define GPIO_164_SELECT     FUNCTION0+NonGpio   // SPI ROM
 #define GPIO_162_SELECT     FUNCTION0+NonGpio   // SPI ROM
 #define GPIO_163_SELECT     FUNCTION0+NonGpio   // SPI ROM
 #define GPIO_164_SELECT     FUNCTION0+NonGpio   // SPI ROM

-#define GPIO_165_SELECT     FUNCTION0+NonGpio   // SPI ROM 
+#define GPIO_165_SELECT     FUNCTION0+NonGpio   // SPI ROM

 #define GPIO_166_SELECT     FUNCTION1+NonGpio   // GBE_STAT2
 #define GPIO_167_SELECT     FUNCTION0+NonGpio   // AZ_SDATA_IN0
 #define GPIO_168_SELECT     FUNCTION0+NonGpio   // AZ_SDATA_IN1
 #define GPIO_166_SELECT     FUNCTION1+NonGpio   // GBE_STAT2
 #define GPIO_167_SELECT     FUNCTION0+NonGpio   // AZ_SDATA_IN0
 #define GPIO_168_SELECT     FUNCTION0+NonGpio   // AZ_SDATA_IN1


@@ -357,18 +357,18 @@
 
 #define TYPE_GPI  (1<<5)
 #define TYPE_GPO  (0<<5)
 
 #define TYPE_GPI  (1<<5)
 #define TYPE_GPO  (0<<5)

-                    
-#define GPIO_00_TYPE        TYPE_GPO 
+
+#define GPIO_00_TYPE        TYPE_GPO

 #define GPIO_01_TYPE        TYPE_GPO
 #define GPIO_02_TYPE        TYPE_GPO
 #define GPIO_03_TYPE        TYPE_GPO
 #define GPIO_04_TYPE        TYPE_GPO
 #define GPIO_01_TYPE        TYPE_GPO
 #define GPIO_02_TYPE        TYPE_GPO
 #define GPIO_03_TYPE        TYPE_GPO
 #define GPIO_04_TYPE        TYPE_GPO

-#define GPIO_05_TYPE        TYPE_GPO 
+#define GPIO_05_TYPE        TYPE_GPO

 #define GPIO_06_TYPE        TYPE_GPO
 #define GPIO_07_TYPE        TYPE_GPO
 #define GPIO_08_TYPE        TYPE_GPO
 #define GPIO_09_TYPE        TYPE_GPI
 #define GPIO_06_TYPE        TYPE_GPO
 #define GPIO_07_TYPE        TYPE_GPO
 #define GPIO_08_TYPE        TYPE_GPO
 #define GPIO_09_TYPE        TYPE_GPI

-#define GPIO_10_TYPE        TYPE_GPI 
+#define GPIO_10_TYPE        TYPE_GPI

 #define GPIO_11_TYPE        TYPE_GPO
 #define GPIO_12_TYPE        TYPE_GPO
 #define GPIO_13_TYPE        TYPE_GPO
 #define GPIO_11_TYPE        TYPE_GPO
 #define GPIO_12_TYPE        TYPE_GPO
 #define GPIO_13_TYPE        TYPE_GPO


@@ -397,33 +397,33 @@
 #define GPIO_36_TYPE        TYPE_GPO
 #define GPIO_37_TYPE        TYPE_GPO
 #define GPIO_38_TYPE        TYPE_GPO
 #define GPIO_36_TYPE        TYPE_GPO
 #define GPIO_37_TYPE        TYPE_GPO
 #define GPIO_38_TYPE        TYPE_GPO

-#define GPIO_39_TYPE        TYPE_GPO 
+#define GPIO_39_TYPE        TYPE_GPO

 #define GPIO_40_TYPE        TYPE_GPO
 #define GPIO_40_TYPE        TYPE_GPO

-#define GPIO_41_TYPE        TYPE_GPI 
+#define GPIO_41_TYPE        TYPE_GPI

 #define GPIO_42_TYPE        TYPE_GPI
 #define GPIO_43_TYPE        TYPE_GPO
 #define GPIO_44_TYPE        TYPE_GPO
 #define GPIO_45_TYPE        TYPE_GPO
 #define GPIO_46_TYPE        TYPE_GPI
 #define GPIO_47_TYPE        TYPE_GPO
 #define GPIO_42_TYPE        TYPE_GPI
 #define GPIO_43_TYPE        TYPE_GPO
 #define GPIO_44_TYPE        TYPE_GPO
 #define GPIO_45_TYPE        TYPE_GPO
 #define GPIO_46_TYPE        TYPE_GPI
 #define GPIO_47_TYPE        TYPE_GPO

-#define GPIO_48_TYPE        TYPE_GPO 
-#define GPIO_49_TYPE        TYPE_GPO 
+#define GPIO_48_TYPE        TYPE_GPO
+#define GPIO_49_TYPE        TYPE_GPO

 #define GPIO_50_TYPE        TYPE_GPO
 #define GPIO_51_TYPE        TYPE_GPO
 #define GPIO_52_TYPE        TYPE_GPO
 #define GPIO_50_TYPE        TYPE_GPO
 #define GPIO_51_TYPE        TYPE_GPO
 #define GPIO_52_TYPE        TYPE_GPO

-#define GPIO_53_TYPE        TYPE_GPO 
-#define GPIO_54_TYPE        TYPE_GPO 
-#define GPIO_55_TYPE        TYPE_GPO 
+#define GPIO_53_TYPE        TYPE_GPO
+#define GPIO_54_TYPE        TYPE_GPO
+#define GPIO_55_TYPE        TYPE_GPO

 #define GPIO_56_TYPE        TYPE_GPI
 #define GPIO_57_TYPE        TYPE_GPO
 #define GPIO_56_TYPE        TYPE_GPI
 #define GPIO_57_TYPE        TYPE_GPO

-#define GPIO_58_TYPE        TYPE_GPO 
+#define GPIO_58_TYPE        TYPE_GPO

 #define GPIO_59_TYPE        TYPE_GPO
 #define GPIO_60_TYPE        TYPE_GPI
 #define GPIO_61_TYPE        TYPE_GPI
 #define GPIO_62_TYPE        TYPE_GPI
 #define GPIO_63_TYPE        TYPE_GPI
 #define GPIO_64_TYPE        TYPE_GPI
 #define GPIO_59_TYPE        TYPE_GPO
 #define GPIO_60_TYPE        TYPE_GPI
 #define GPIO_61_TYPE        TYPE_GPI
 #define GPIO_62_TYPE        TYPE_GPI
 #define GPIO_63_TYPE        TYPE_GPI
 #define GPIO_64_TYPE        TYPE_GPI

-#define GPIO_65_TYPE        TYPE_GPI  
+#define GPIO_65_TYPE        TYPE_GPI

 #define GPIO_66_TYPE        TYPE_GPO
 #define GPIO_67_TYPE        TYPE_GPO
 #define GPIO_68_TYPE        TYPE_GPO
 #define GPIO_66_TYPE        TYPE_GPO
 #define GPIO_67_TYPE        TYPE_GPO
 #define GPIO_68_TYPE        TYPE_GPO


@@ -460,17 +460,17 @@
 #define GPIO_97_TYPE        TYPE_GPI
 #define GPIO_98_TYPE        TYPE_GPI
 #define GPIO_99_TYPE        TYPE_GPI
 #define GPIO_97_TYPE        TYPE_GPI
 #define GPIO_98_TYPE        TYPE_GPI
 #define GPIO_99_TYPE        TYPE_GPI

-#define GPIO_100_TYPE       TYPE_GPI 
+#define GPIO_100_TYPE       TYPE_GPI

 #define GPIO_101_TYPE       TYPE_GPI
 #define GPIO_102_TYPE       TYPE_GPO
 #define GPIO_103_TYPE       TYPE_GPO
 #define GPIO_104_TYPE       TYPE_GPI
 #define GPIO_101_TYPE       TYPE_GPI
 #define GPIO_102_TYPE       TYPE_GPO
 #define GPIO_103_TYPE       TYPE_GPO
 #define GPIO_104_TYPE       TYPE_GPI

-#define GPIO_105_TYPE       TYPE_GPI 
+#define GPIO_105_TYPE       TYPE_GPI

 #define GPIO_106_TYPE       TYPE_GPO
 #define GPIO_107_TYPE       TYPE_GPI
 #define GPIO_108_TYPE       TYPE_GPI
 #define GPIO_109_TYPE       TYPE_GPI
 #define GPIO_106_TYPE       TYPE_GPO
 #define GPIO_107_TYPE       TYPE_GPI
 #define GPIO_108_TYPE       TYPE_GPI
 #define GPIO_109_TYPE       TYPE_GPI

-#define GPIO_110_TYPE       TYPE_GPI 
+#define GPIO_110_TYPE       TYPE_GPI

 #define GPIO_111_TYPE       TYPE_GPI
 #define GPIO_112_TYPE       TYPE_GPI
 #define GPIO_113_TYPE       TYPE_GPI
 #define GPIO_111_TYPE       TYPE_GPI
 #define GPIO_112_TYPE       TYPE_GPI
 #define GPIO_113_TYPE       TYPE_GPI


@@ -500,33 +500,33 @@
 #define GPIO_136_TYPE       TYPE_GPO
 #define GPIO_137_TYPE       TYPE_GPO
 #define GPIO_138_TYPE       TYPE_GPO
 #define GPIO_136_TYPE       TYPE_GPO
 #define GPIO_137_TYPE       TYPE_GPO
 #define GPIO_138_TYPE       TYPE_GPO

-#define GPIO_139_TYPE       TYPE_GPO 
+#define GPIO_139_TYPE       TYPE_GPO

 #define GPIO_140_TYPE       TYPE_GPO
 #define GPIO_140_TYPE       TYPE_GPO

-#define GPIO_141_TYPE       TYPE_GPO 
+#define GPIO_141_TYPE       TYPE_GPO

 #define GPIO_142_TYPE       TYPE_GPO
 #define GPIO_143_TYPE       TYPE_GPO
 #define GPIO_144_TYPE       TYPE_GPO
 #define GPIO_145_TYPE       TYPE_GPO
 #define GPIO_146_TYPE       TYPE_GPO
 #define GPIO_147_TYPE       TYPE_GPO
 #define GPIO_142_TYPE       TYPE_GPO
 #define GPIO_143_TYPE       TYPE_GPO
 #define GPIO_144_TYPE       TYPE_GPO
 #define GPIO_145_TYPE       TYPE_GPO
 #define GPIO_146_TYPE       TYPE_GPO
 #define GPIO_147_TYPE       TYPE_GPO

-#define GPIO_148_TYPE       TYPE_GPO 
-#define GPIO_149_TYPE       TYPE_GPO 
+#define GPIO_148_TYPE       TYPE_GPO
+#define GPIO_149_TYPE       TYPE_GPO

 #define GPIO_150_TYPE       TYPE_GPO
 #define GPIO_151_TYPE       TYPE_GPO
 #define GPIO_152_TYPE       TYPE_GPO
 #define GPIO_150_TYPE       TYPE_GPO
 #define GPIO_151_TYPE       TYPE_GPO
 #define GPIO_152_TYPE       TYPE_GPO

-#define GPIO_153_TYPE       TYPE_GPO 
-#define GPIO_154_TYPE       TYPE_GPO 
-#define GPIO_155_TYPE       TYPE_GPO 
+#define GPIO_153_TYPE       TYPE_GPO
+#define GPIO_154_TYPE       TYPE_GPO
+#define GPIO_155_TYPE       TYPE_GPO

 #define GPIO_156_TYPE       TYPE_GPO
 #define GPIO_157_TYPE       TYPE_GPO
 #define GPIO_156_TYPE       TYPE_GPO
 #define GPIO_157_TYPE       TYPE_GPO

-#define GPIO_158_TYPE       TYPE_GPO 
+#define GPIO_158_TYPE       TYPE_GPO

 #define GPIO_159_TYPE       TYPE_GPO
 #define GPIO_160_TYPE       TYPE_GPO
 #define GPIO_161_TYPE       TYPE_GPO
 #define GPIO_162_TYPE       TYPE_GPO
 #define GPIO_163_TYPE       TYPE_GPO
 #define GPIO_164_TYPE       TYPE_GPI
 #define GPIO_159_TYPE       TYPE_GPO
 #define GPIO_160_TYPE       TYPE_GPO
 #define GPIO_161_TYPE       TYPE_GPO
 #define GPIO_162_TYPE       TYPE_GPO
 #define GPIO_163_TYPE       TYPE_GPO
 #define GPIO_164_TYPE       TYPE_GPI

-#define GPIO_165_TYPE       TYPE_GPO  
+#define GPIO_165_TYPE       TYPE_GPO

 #define GPIO_166_TYPE       TYPE_GPI
 #define GPIO_167_TYPE       TYPE_GPI
 #define GPIO_168_TYPE       TYPE_GPI
 #define GPIO_166_TYPE       TYPE_GPI
 #define GPIO_167_TYPE       TYPE_GPI
 #define GPIO_168_TYPE       TYPE_GPI


@@ -561,17 +561,17 @@
 #define GPIO_197_TYPE       TYPE_GPO
 #define GPIO_198_TYPE       TYPE_GPO
 #define GPIO_199_TYPE       TYPE_GPI
 #define GPIO_197_TYPE       TYPE_GPO
 #define GPIO_198_TYPE       TYPE_GPO
 #define GPIO_199_TYPE       TYPE_GPI

-#define GPIO_200_TYPE       TYPE_GPO 
+#define GPIO_200_TYPE       TYPE_GPO

 #define GPIO_201_TYPE       TYPE_GPI
 #define GPIO_202_TYPE       TYPE_GPI
 #define GPIO_203_TYPE       TYPE_GPI
 #define GPIO_204_TYPE       TYPE_GPI
 #define GPIO_201_TYPE       TYPE_GPI
 #define GPIO_202_TYPE       TYPE_GPI
 #define GPIO_203_TYPE       TYPE_GPI
 #define GPIO_204_TYPE       TYPE_GPI

-#define GPIO_205_TYPE       TYPE_GPI 
+#define GPIO_205_TYPE       TYPE_GPI

 #define GPIO_206_TYPE       TYPE_GPI
 #define GPIO_207_TYPE       TYPE_GPI
 #define GPIO_208_TYPE       TYPE_GPI
 #define GPIO_209_TYPE       TYPE_GPO
 #define GPIO_206_TYPE       TYPE_GPI
 #define GPIO_207_TYPE       TYPE_GPI
 #define GPIO_208_TYPE       TYPE_GPI
 #define GPIO_209_TYPE       TYPE_GPO

-#define GPIO_210_TYPE       TYPE_GPO 
+#define GPIO_210_TYPE       TYPE_GPO

 #define GPIO_211_TYPE       TYPE_GPO
 #define GPIO_212_TYPE       TYPE_GPO
 #define GPIO_213_TYPE       TYPE_GPO
 #define GPIO_211_TYPE       TYPE_GPO
 #define GPIO_212_TYPE       TYPE_GPO
 #define GPIO_213_TYPE       TYPE_GPO


@@ -595,17 +595,17 @@
 #define GPO_LOW   (0<<6)
 #define GPO_HI    (1<<6)
 
 #define GPO_LOW   (0<<6)
 #define GPO_HI    (1<<6)
 

-#define GPO_00_LEVEL        GPO_HI 
+#define GPO_00_LEVEL        GPO_HI

 #define GPO_01_LEVEL        GPO_HI
 #define GPO_02_LEVEL        GPO_HI
 #define GPO_03_LEVEL        GPO_HI
 #define GPO_04_LEVEL        GPO_HI
 #define GPO_01_LEVEL        GPO_HI
 #define GPO_02_LEVEL        GPO_HI
 #define GPO_03_LEVEL        GPO_HI
 #define GPO_04_LEVEL        GPO_HI

-#define GPO_05_LEVEL        GPO_HI  
+#define GPO_05_LEVEL        GPO_HI

 #define GPO_06_LEVEL        GPO_HI
 #define GPO_07_LEVEL        GPO_HI
 #define GPO_08_LEVEL        GPO_HI
 #define GPO_09_LEVEL        GPO_LOW
 #define GPO_06_LEVEL        GPO_HI
 #define GPO_07_LEVEL        GPO_HI
 #define GPO_08_LEVEL        GPO_HI
 #define GPO_09_LEVEL        GPO_LOW

-#define GPO_10_LEVEL        GPO_LOW 
+#define GPO_10_LEVEL        GPO_LOW

 #define GPO_11_LEVEL        GPO_HI
 #define GPO_12_LEVEL        GPO_HI
 #define GPO_13_LEVEL        GPO_HI
 #define GPO_11_LEVEL        GPO_HI
 #define GPO_12_LEVEL        GPO_HI
 #define GPO_13_LEVEL        GPO_HI


@@ -634,16 +634,16 @@
 #define GPO_36_LEVEL        GPO_LOW
 #define GPO_37_LEVEL        GPO_HI
 #define GPO_38_LEVEL        GPO_HI
 #define GPO_36_LEVEL        GPO_LOW
 #define GPO_37_LEVEL        GPO_HI
 #define GPO_38_LEVEL        GPO_HI

-#define GPO_39_LEVEL        GPO_HI  
+#define GPO_39_LEVEL        GPO_HI

 #define GPO_40_LEVEL        GPO_LOW
 #define GPO_40_LEVEL        GPO_LOW

-#define GPO_41_LEVEL        GPO_LOW 
+#define GPO_41_LEVEL        GPO_LOW

 #define GPO_42_LEVEL        GPO_LOW
 #define GPO_43_LEVEL        GPO_LOW
 #define GPO_44_LEVEL        GPO_HI
 #define GPO_45_LEVEL        GPO_HI
 #define GPO_46_LEVEL        GPO_LOW
 #define GPO_47_LEVEL        GPO_LOW
 #define GPO_42_LEVEL        GPO_LOW
 #define GPO_43_LEVEL        GPO_LOW
 #define GPO_44_LEVEL        GPO_HI
 #define GPO_45_LEVEL        GPO_HI
 #define GPO_46_LEVEL        GPO_LOW
 #define GPO_47_LEVEL        GPO_LOW

-#define GPO_48_LEVEL        GPO_LOW 
+#define GPO_48_LEVEL        GPO_LOW

 #define GPO_49_LEVEL        GPO_HI
 #define GPO_50_LEVEL        GPO_HI
 #define GPO_51_LEVEL        GPO_LOW
 #define GPO_49_LEVEL        GPO_HI
 #define GPO_50_LEVEL        GPO_HI
 #define GPO_51_LEVEL        GPO_LOW


@@ -667,7 +667,7 @@
 #define GPO_69_LEVEL        GPO_LOW
 #define GPO_70_LEVEL        GPO_LOW
 #define GPO_71_LEVEL        GPO_LOW
 #define GPO_69_LEVEL        GPO_LOW
 #define GPO_70_LEVEL        GPO_LOW
 #define GPO_71_LEVEL        GPO_LOW

-#define GPO_72_LEVEL        GPO_LOW 
+#define GPO_72_LEVEL        GPO_LOW

 #define GPO_73_LEVEL        GPO_LOW
 #define GPO_74_LEVEL        GPO_LOW
 #define GPO_75_LEVEL        GPO_LOW
 #define GPO_73_LEVEL        GPO_LOW
 #define GPO_74_LEVEL        GPO_LOW
 #define GPO_75_LEVEL        GPO_LOW


@@ -695,17 +695,17 @@
 #define GPO_97_LEVEL        GPO_LOW
 #define GPO_98_LEVEL        GPO_LOW
 #define GPO_99_LEVEL        GPO_LOW
 #define GPO_97_LEVEL        GPO_LOW
 #define GPO_98_LEVEL        GPO_LOW
 #define GPO_99_LEVEL        GPO_LOW

-#define GPO_100_LEVEL       GPO_LOW 
+#define GPO_100_LEVEL       GPO_LOW

 #define GPO_101_LEVEL       GPO_LOW
 #define GPO_102_LEVEL       GPO_LOW
 #define GPO_103_LEVEL       GPO_LOW
 #define GPO_104_LEVEL       GPO_LOW
 #define GPO_101_LEVEL       GPO_LOW
 #define GPO_102_LEVEL       GPO_LOW
 #define GPO_103_LEVEL       GPO_LOW
 #define GPO_104_LEVEL       GPO_LOW

-#define GPO_105_LEVEL       GPO_LOW  
+#define GPO_105_LEVEL       GPO_LOW

 #define GPO_106_LEVEL       GPO_LOW
 #define GPO_107_LEVEL       GPO_LOW
 #define GPO_108_LEVEL       GPO_HI
 #define GPO_109_LEVEL       GPO_LOW
 #define GPO_106_LEVEL       GPO_LOW
 #define GPO_107_LEVEL       GPO_LOW
 #define GPO_108_LEVEL       GPO_HI
 #define GPO_109_LEVEL       GPO_LOW

-#define GPO_110_LEVEL       GPO_HI 
+#define GPO_110_LEVEL       GPO_HI

 #define GPO_111_LEVEL       GPO_HI
 #define GPO_112_LEVEL       GPO_HI
 #define GPO_113_LEVEL       GPO_LOW
 #define GPO_111_LEVEL       GPO_HI
 #define GPO_112_LEVEL       GPO_HI
 #define GPO_113_LEVEL       GPO_LOW


@@ -734,16 +734,16 @@
 #define GPO_136_LEVEL       GPO_LOW
 #define GPO_137_LEVEL       GPO_LOW
 #define GPO_138_LEVEL       GPO_LOW
 #define GPO_136_LEVEL       GPO_LOW
 #define GPO_137_LEVEL       GPO_LOW
 #define GPO_138_LEVEL       GPO_LOW

-#define GPO_139_LEVEL       GPO_LOW  
+#define GPO_139_LEVEL       GPO_LOW

 #define GPO_140_LEVEL       GPO_LOW
 #define GPO_140_LEVEL       GPO_LOW

-#define GPO_141_LEVEL       GPO_LOW 
+#define GPO_141_LEVEL       GPO_LOW

 #define GPO_142_LEVEL       GPO_LOW
 #define GPO_143_LEVEL       GPO_LOW
 #define GPO_144_LEVEL       GPO_LOW
 #define GPO_145_LEVEL       GPO_LOW
 #define GPO_146_LEVEL       GPO_LOW
 #define GPO_147_LEVEL       GPO_LOW
 #define GPO_142_LEVEL       GPO_LOW
 #define GPO_143_LEVEL       GPO_LOW
 #define GPO_144_LEVEL       GPO_LOW
 #define GPO_145_LEVEL       GPO_LOW
 #define GPO_146_LEVEL       GPO_LOW
 #define GPO_147_LEVEL       GPO_LOW

-#define GPO_148_LEVEL       GPO_LOW 
+#define GPO_148_LEVEL       GPO_LOW

 #define GPO_149_LEVEL       GPO_LOW
 #define GPO_150_LEVEL       GPO_LOW
 #define GPO_151_LEVEL       GPO_LOW
 #define GPO_149_LEVEL       GPO_LOW
 #define GPO_150_LEVEL       GPO_LOW
 #define GPO_151_LEVEL       GPO_LOW


@@ -795,17 +795,17 @@
 #define GPO_197_LEVEL       GPO_LOW
 #define GPO_198_LEVEL       GPO_LOW
 #define GPO_199_LEVEL       GPO_LOW
 #define GPO_197_LEVEL       GPO_LOW
 #define GPO_198_LEVEL       GPO_LOW
 #define GPO_199_LEVEL       GPO_LOW

-#define GPO_200_LEVEL       GPO_HI 
+#define GPO_200_LEVEL       GPO_HI

 #define GPO_201_LEVEL       GPO_LOW
 #define GPO_202_LEVEL       GPO_LOW
 #define GPO_203_LEVEL       GPO_LOW
 #define GPO_204_LEVEL       GPO_LOW
 #define GPO_201_LEVEL       GPO_LOW
 #define GPO_202_LEVEL       GPO_LOW
 #define GPO_203_LEVEL       GPO_LOW
 #define GPO_204_LEVEL       GPO_LOW

-#define GPO_205_LEVEL       GPO_LOW  
+#define GPO_205_LEVEL       GPO_LOW

 #define GPO_206_LEVEL       GPO_LOW
 #define GPO_207_LEVEL       GPO_LOW
 #define GPO_208_LEVEL       GPO_LOW
 #define GPO_209_LEVEL       GPO_LOW
 #define GPO_206_LEVEL       GPO_LOW
 #define GPO_207_LEVEL       GPO_LOW
 #define GPO_208_LEVEL       GPO_LOW
 #define GPO_209_LEVEL       GPO_LOW

-#define GPO_210_LEVEL       GPO_LOW 
+#define GPO_210_LEVEL       GPO_LOW

 #define GPO_211_LEVEL       GPO_LOW
 #define GPO_212_LEVEL       GPO_LOW
 #define GPO_213_LEVEL       GPO_LOW
 #define GPO_211_LEVEL       GPO_LOW
 #define GPO_212_LEVEL       GPO_LOW
 #define GPO_213_LEVEL       GPO_LOW


@@ -2278,9 +2278,9 @@ typedef struct _GEVENT_SETTINGS
     u8 SciLevl;          // 0: Edge trigger, 1: Level Trigger
     u8 SmiSciEn;         // 0: Not send SMI, 1: Send SMI
     u8 SciS0En;          // 0: Disable, 1: Enable
     u8 SciLevl;          // 0: Edge trigger, 1: Level Trigger
     u8 SmiSciEn;         // 0: Not send SMI, 1: Send SMI
     u8 SciS0En;          // 0: Disable, 1: Enable

-    u8 SciMap;           // 0000b->1111b 
+    u8 SciMap;           // 0000b->1111b

     u8 SmiTrig;          // 0: Active Low, 1: Active High
     u8 SmiTrig;          // 0: Active Low, 1: Active High

-    u8 SmiControl;       // 0: Disable, 1: SMI 2: NMI 3: IRQ13     
+    u8 SmiControl;       // 0: Disable, 1: SMI 2: NMI 3: IRQ13

 } GEVENT_SETTINGS;
 
 GEVENT_SETTINGS gevent_table[] =
 } GEVENT_SETTINGS;
 
 GEVENT_SETTINGS gevent_table[] =


@@ -2315,15 +2315,15 @@ GEVENT_SETTINGS gevent_table[] =
  *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
  *----------------------------------------------------------------------------------------
  */
  *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
  *----------------------------------------------------------------------------------------
  */

- 
+

 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */

- 
+

 /*---------------------------------------------------------------------------------------
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */
 /*---------------------------------------------------------------------------------------
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */

- 
+

 #endif
 #endif

diff --git a/src/mainboard/amd/torpedo/irq_tables.c b/src/mainboard/amd/torpedo/irq_tables.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
old mode 100755 (executable)
new mode 100644 (file)
index 0381206..2e171a1
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -37,15 +37,15 @@ extern u32 sbdn_sb900;
 u32 apicid_sb900;
 
 u8 picr_data[] = {
 u32 apicid_sb900;
 
 u8 picr_data[] = {

-  0x0B,0x0B,0x0B,0x0B,0x1F,0x1F,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, 
-  0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 
+  0x0B,0x0B,0x0B,0x0B,0x1F,0x1F,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+  0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

   0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x0B,0x0B,0x0B,0x0B
 };
 u8 intr_data[] = {
   0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x0B,0x0B,0x0B,0x0B
 };
 u8 intr_data[] = {

-  0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, 
+  0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,

   0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
   0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,


@@ -96,7 +96,7 @@ static void *smp_write_config_table(void *v)
       0, apic_version,
       cpu_flag, cpu_features, cpu_feature_flags
     );
       0, apic_version,
       cpu_flag, cpu_features, cpu_feature_flags
     );

-  
+

   cpu_flag = MPC_CPU_ENABLED;
   smp_write_processor(mc,
       1, apic_version,
   cpu_flag = MPC_CPU_ENABLED;
   smp_write_processor(mc,
       1, apic_version,


@@ -112,11 +112,11 @@ static void *smp_write_config_table(void *v)
   my_smp_write_bus(mc, bus_isa, "ISA   ");
 
   /* I/O APICs:   APIC ID Version State   Address */
   my_smp_write_bus(mc, bus_isa, "ISA   ");
 
   /* I/O APICs:   APIC ID Version State   Address */

-  
+

   device_t dev;
   u32 dword;
   u8 byte;
   device_t dev;
   u32 dword;
   u8 byte;

-    
+

   dword = 0;
   dword = pm_ioread(0x34) & 0xF0;
   dword |= (pm_ioread(0x35) & 0xFF) << 8;
   dword = 0;
   dword = pm_ioread(0x34) & 0xF0;
   dword |= (pm_ioread(0x35) & 0xFF) << 8;


@@ -127,13 +127,13 @@ static void *smp_write_config_table(void *v)
   write32 (dword + 0x10, IO_APIC_ID << 24);
   apicid_sb900 = IO_APIC_ID;
   smp_write_ioapic(mc, apicid_sb900, 0x21, dword);
   write32 (dword + 0x10, IO_APIC_ID << 24);
   apicid_sb900 = IO_APIC_ID;
   smp_write_ioapic(mc, apicid_sb900, 0x21, dword);

-  
+

   /* PIC IRQ routine */
   for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
     outb(byte, 0xC00);
     outb(picr_data[byte], 0xC01);
   }
   /* PIC IRQ routine */
   for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
     outb(byte, 0xC00);
     outb(picr_data[byte], 0xC01);
   }

-  
+

   /* APIC IRQ routine */
   for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
     outb(byte | 0x80, 0xC00);
   /* APIC IRQ routine */
   for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
     outb(byte | 0x80, 0xC00);


@@ -172,15 +172,15 @@ static void *smp_write_config_table(void *v)
   /* Internal VGA */
   PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
   PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
   /* Internal VGA */
   PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
   PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);

-  
+

   /* SMBUS */
   PCI_INT(0x0, 0x14, 0x0, 0x10);
   /* SMBUS */
   PCI_INT(0x0, 0x14, 0x0, 0x10);

-  
+

   /* HD Audio */
   PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
   /* HD Audio */
   PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);

-  
+

   /* USB */
   /* USB */

-  PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); 
+  PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);

   PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
   PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
   PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
   PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
   PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
   PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);


@@ -194,7 +194,7 @@ static void *smp_write_config_table(void *v)
 
 
   /* on board NIC & Slot PCIE.  */
 
 
   /* on board NIC & Slot PCIE.  */

-  
+

   /* PCI slots */
   /* PCI_SLOT 0. */
   PCI_INT(bus_sb900[1], 0x5, 0x0, 0x14);
   /* PCI slots */
   /* PCI_SLOT 0. */
   PCI_INT(bus_sb900[1], 0x5, 0x0, 0x14);

diff --git a/src/mainboard/amd/torpedo/pmio.c b/src/mainboard/amd/torpedo/pmio.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/amd/torpedo/pmio.h b/src/mainboard/amd/torpedo/pmio.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/amd/torpedo/reset.c b/src/mainboard/amd/torpedo/reset.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c
index ae67c3fd6ea036cc23a6e98e8804b595d85acd68..a0d64a72471a54e5cf0a9d76541ec72071aa43b4 100644 (file)
--- a/src/mainboard/asrock/e350m1/BiosCallOuts.c
+++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

- 
+

 #include "agesawrapper.h"
 #include "amdlib.h"
 #include "BiosCallOuts.h"
 #include "agesawrapper.h"
 #include "amdlib.h"
 #include "BiosCallOuts.h"


@@ -61,7 +61,7 @@ CONST BIOS_CALLOUT_STRUCT BiosCallouts[REQUIRED_CALLOUTS] =
   {AGESA_HOOKBEFORE_DQS_TRAINING,
    BiosHookBeforeDQSTraining
   },
   {AGESA_HOOKBEFORE_DQS_TRAINING,
    BiosHookBeforeDQSTraining
   },

-  
+

   {AGESA_HOOKBEFORE_DRAM_INIT,
    BiosHookBeforeDramInit
   },
   {AGESA_HOOKBEFORE_DRAM_INIT,
    BiosHookBeforeDramInit
   },


@@ -149,7 +149,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
        to the end of the allocated nodes list.
       */
       /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
        to the end of the allocated nodes list.
       */

-       
+

     }
     /* Find the node that best fits the requested buffer size */
     FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
     }
     /* Find the node that best fits the requested buffer size */
     FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;


@@ -199,7 +199,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 
       /* If BestFitNode is the first buffer in the list, then update
          StartOfFreedNodes to reflect the new free node
 
       /* If BestFitNode is the first buffer in the list, then update
          StartOfFreedNodes to reflect the new free node

-      */         
+      */

       if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
         BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
       } else {
       if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
         BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
       } else {


@@ -284,10 +284,10 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       FreedNodePtr->NextNodeOffset = 0;
 
     } else {
       FreedNodePtr->NextNodeOffset = 0;
 
     } else {

-      /* Otherwise, add freed node to the start of the list 
-         Update NextNodeOffset and BufferSize to include the 
+      /* Otherwise, add freed node to the start of the list
+         Update NextNodeOffset and BufferSize to include the

          size of BIOS_BUFFER_NODE
          size of BIOS_BUFFER_NODE

-      */   
+      */

       AllocNodePtr->NextNodeOffset = FreedNodeOffset;
     }
     /* Update StartOfFreedNodes to the new first node */
       AllocNodePtr->NextNodeOffset = FreedNodeOffset;
     }
     /* Update StartOfFreedNodes to the new first node */


@@ -295,7 +295,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   } else {
     /* Traverse list of freed nodes to find where the deallocated node
        should be place
   } else {
     /* Traverse list of freed nodes to find where the deallocated node
        should be place

-    */   
+    */

     NextNodeOffset = FreedNodeOffset;
     NextNodePtr = FreedNodePtr;
     while (AllocNodeOffset > NextNodeOffset) {
     NextNodeOffset = FreedNodeOffset;
     NextNodePtr = FreedNodePtr;
     while (AllocNodeOffset > NextNodeOffset) {


@@ -309,7 +309,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 
     /* If deallocated node is adjacent to the next node,
        concatenate both nodes
 
     /* If deallocated node is adjacent to the next node,
        concatenate both nodes

-    */   
+    */

     if (NextNodeOffset == EndNodeOffset) {
       NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
       AllocNodePtr->BufferSize += NextNodePtr->BufferSize;
     if (NextNodeOffset == EndNodeOffset) {
       NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
       AllocNodePtr->BufferSize += NextNodePtr->BufferSize;


@@ -323,7 +323,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
     }
     /* If deallocated node is adjacent to the previous node,
        concatenate both nodes
     }
     /* If deallocated node is adjacent to the previous node,
        concatenate both nodes

-    */   
+    */

     PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
     EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
     if (AllocNodeOffset == EndNodeOffset) {
     PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
     EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
     if (AllocNodeOffset == EndNodeOffset) {


@@ -387,10 +387,10 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   UINT8                 Value;
   UINTN               ResetType;
   AMD_CONFIG_PARAMS   *StdHeader;
   UINT8                 Value;
   UINTN               ResetType;
   AMD_CONFIG_PARAMS   *StdHeader;

-  
+

   ResetType = Data;
   StdHeader = ConfigPtr;
   ResetType = Data;
   StdHeader = ConfigPtr;

-    
+

   //
   // Perform the RESET based upon the ResetType. In case of
   // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to
   //
   // Perform the RESET based upon the ResetType. In case of
   // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to


@@ -402,17 +402,17 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   case WARM_RESET_WHENEVER:
   case COLD_RESET_WHENEVER:
     break;
   case WARM_RESET_WHENEVER:
   case COLD_RESET_WHENEVER:
     break;

-    
+

   case WARM_RESET_IMMEDIATELY:
   case COLD_RESET_IMMEDIATELY:
       Value = 0x06;
       LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
     break;
   case WARM_RESET_IMMEDIATELY:
   case COLD_RESET_IMMEDIATELY:
       Value = 0x06;
       LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
     break;

-    
+

   default:
     break;
   }
   default:
     break;
   }

-  
+

   Status = 0;
   return Status;
 }
   Status = 0;
   return Status;
 }


@@ -445,10 +445,10 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   UINT8             Data8;
   UINT16            Data16;
   UINT8             TempData8;
   UINT8             Data8;
   UINT16            Data16;
   UINT8             TempData8;

-    
+

   FcnData = Data;
   MemData = ConfigPtr;
   FcnData = Data;
   MemData = ConfigPtr;

-  
+

   Status  = AGESA_SUCCESS;
   /* Get SB800 MMIO Base (AcpiMmioAddr) */
   WriteIo8 (0xCD6, 0x27);
   Status  = AGESA_SUCCESS;
   /* Get SB800 MMIO Base (AcpiMmioAddr) */
   WriteIo8 (0xCD6, 0x27);


@@ -459,14 +459,14 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   Data16  |= Data8;
   AcpiMmioAddr = (UINT32)Data16 << 16;
   GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
   Data16  |= Data8;
   AcpiMmioAddr = (UINT32)Data16 << 16;
   GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;

-  
+

   Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
   Data8 &= ~BIT5;
   TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
   TempData8 &= 0x03;
   TempData8 |= Data8;
   Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
   Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
   Data8 &= ~BIT5;
   TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
   TempData8 &= 0x03;
   TempData8 |= Data8;
   Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);

-   
+

   Data8 |= BIT2+BIT3;
   Data8 &= ~BIT4;
   TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
   Data8 |= BIT2+BIT3;
   Data8 &= ~BIT4;
   TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);


@@ -485,7 +485,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   TempData8 &= 0x23;
   TempData8 |= Data8;
   Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
   TempData8 &= 0x23;
   TempData8 |= Data8;
   Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);

-  
+

   switch(MemData->ParameterListPtr->DDR3Voltage){
     case VOLT1_35:
       Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
   switch(MemData->ParameterListPtr->DDR3Voltage){
     case VOLT1_35:
       Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);


@@ -527,12 +527,12 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   AGESA_STATUS Status;
   UINTN                 FcnData;
   PCIe_SLOT_RESET_INFO  *ResetInfo;
   AGESA_STATUS Status;
   UINTN                 FcnData;
   PCIe_SLOT_RESET_INFO  *ResetInfo;

-  
+

   UINT32  GpioMmioAddr;
   UINT32  AcpiMmioAddr;
   UINT8   Data8;
   UINT16  Data16;
   UINT32  GpioMmioAddr;
   UINT32  AcpiMmioAddr;
   UINT8   Data8;
   UINT16  Data16;

-  
+

   FcnData   = Data;
   ResetInfo = ConfigPtr;
   // Get SB800 MMIO Base (AcpiMmioAddr)
   FcnData   = Data;
   ResetInfo = ConfigPtr;
   // Get SB800 MMIO Base (AcpiMmioAddr)


@@ -552,13 +552,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       {
       case AssertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
       {
       case AssertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);

-        Data8 &= ~(UINT8)BIT6 ; 
+        Data8 &= ~(UINT8)BIT6 ;

         Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);   // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
         Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);   // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);

-        Data8 |= BIT6 ; 
+        Data8 |= BIT6 ;

         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);       // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;
         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);       // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;


@@ -575,7 +575,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);

-        Data8 |= BIT6 ; 
+        Data8 |= BIT6 ;

         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);       // PCIE_RST#_LAN, GPIO25
         Status = AGESA_SUCCESS;
         break;
         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);       // PCIE_RST#_LAN, GPIO25
         Status = AGESA_SUCCESS;
         break;

diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.h b/src/mainboard/asrock/e350m1/BiosCallOuts.h
index 2912ec6f513ccd245db0f3755bcd6ab566cb89ec..4efe15fa4d55e5efb039ef4dca6e7d3c19ca7f85 100644 (file)
--- a/src/mainboard/asrock/e350m1/BiosCallOuts.h
+++ b/src/mainboard/asrock/e350m1/BiosCallOuts.h
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

- 
+

 #ifndef _BIOS_CALLOUT_H_
 #define _BIOS_CALLOUT_H_
 
 #ifndef _BIOS_CALLOUT_H_
 #define _BIOS_CALLOUT_H_
 


@@ -45,7 +45,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 
 /* REQUIRED CALLOUTS
  * AGESA ADVANCED CALLOUTS - CPU
 
 /* REQUIRED CALLOUTS
  * AGESA ADVANCED CALLOUTS - CPU

- */  
+ */

 AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);

diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c
index 0d790773d4bf9dc32155842e8c967ba4003f8814..a79dfab62ef2f285f922de2d94c2daf5b514d2b1 100644 (file)
--- a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c
+++ b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c
@@ -86,7 +86,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
           DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
           PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
           PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
           DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
           PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
           PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)

-        }       
+        }

 };
 
 PCIe_DDI_DESCRIPTOR DdiList [] = {
 };
 
 PCIe_DDI_DESCRIPTOR DdiList [] = {


@@ -118,8 +118,8 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
   //
   // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
   //
   //
   // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
   //

-  AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  + 
-                                         sizeof (PCIe_PORT_DESCRIPTOR) * 5 + 
+  AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  +
+                                         sizeof (PCIe_PORT_DESCRIPTOR) * 5 +

                                          sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
 
   AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
                                          sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
 
   AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;


@@ -127,10 +127,10 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
   Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
   if ( Status!= AGESA_SUCCESS) {
     // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
   Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
   if ( Status!= AGESA_SUCCESS) {
     // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR

-    ASSERT(FALSE); 
+    ASSERT(FALSE);

     return Status;
   }
     return Status;
   }

-  
+

   BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
   BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);


@@ -138,7 +138,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
   BrazosPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
   BrazosPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;

- 
+

   LibAmdMemFill (BrazosPcieComplexListPtr,
                    0,
                    sizeof (PCIe_COMPLEX_DESCRIPTOR),
   LibAmdMemFill (BrazosPcieComplexListPtr,
                    0,
                    sizeof (PCIe_COMPLEX_DESCRIPTOR),


@@ -148,7 +148,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
                    0,
                    sizeof (PCIe_PORT_DESCRIPTOR) * 5,
                    &InitEarly->StdHeader);
                    0,
                    sizeof (PCIe_PORT_DESCRIPTOR) * 5,
                    &InitEarly->StdHeader);

-     
+

   LibAmdMemFill (BrazosPcieDdiPtr,
                    0,
                    sizeof (PCIe_DDI_DESCRIPTOR) * 2,
   LibAmdMemFill (BrazosPcieDdiPtr,
                    0,
                    sizeof (PCIe_DDI_DESCRIPTOR) * 2,


@@ -162,7 +162,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
 
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
 

-  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; 
-  InitEarly->GnbConfig.PsppPolicy      = 0; 
+  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
+  InitEarly->GnbConfig.PsppPolicy      = 0;

 }
 
 }
 

diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h
index f35d8db723c464a538c7b20f78e3947365e2d5ed..b51089f7f643cdc51ebbc15bf184ca99ca309e76 100644 (file)
--- a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h
+++ b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h
@@ -25,42 +25,42 @@
 #include "amdlib.h"
 
 //GNB GPP Port4
 #include "amdlib.h"
 
 //GNB GPP Port4

-#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable

 #define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT4_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT4_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1

-#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)

                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port5
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port5

-#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable

 #define GNB_GPP_PORT5_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT5_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT5_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT5_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1

-#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)

                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port6
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port6

-#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable

 #define GNB_GPP_PORT6_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT6_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT6_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT6_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1

-#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)

                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port7
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port7

-#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable

 #define GNB_GPP_PORT7_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT7_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT7_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT7_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1

-#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)

                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port8
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port8

-#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable

 #define GNB_GPP_PORT8_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT8_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT8_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT8_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1

-#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)

                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 


@@ -68,5 +68,5 @@ VOID
 OemCustomizeInitEarly (
   IN  OUT AMD_EARLY_PARAMS    *InitEarly
   );
 OemCustomizeInitEarly (
   IN  OUT AMD_EARLY_PARAMS    *InitEarly
   );

-  
+

 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H
 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H

diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c
index 802e00e1fe9756e14fdb8d8eed502d74d1c582aa..7fc2fd6da445994a4599a909c0003ebdfcf1ab1b 100644 (file)
--- a/src/mainboard/asrock/e350m1/agesawrapper.c
+++ b/src/mainboard/asrock/e350m1/agesawrapper.c
@@ -21,7 +21,7 @@
  *                             M O D U L E S    U S E D
  *----------------------------------------------------------------------------------------
  */
  *                             M O D U L E S    U S E D
  *----------------------------------------------------------------------------------------
  */

- 
+

 #include <stdint.h>
 #include <string.h>
 #include "agesawrapper.h"
 #include <stdint.h>
 #include <string.h>
 #include "agesawrapper.h"


@@ -52,8 +52,8 @@ VOID *AcpiSlit    = NULL;
 
 VOID *AcpiWheaMce = NULL;
 VOID *AcpiWheaCmc = NULL;
 
 VOID *AcpiWheaMce = NULL;
 VOID *AcpiWheaCmc = NULL;

-VOID *AcpiAlib    = NULL; 
- 
+VOID *AcpiAlib    = NULL;
+

 
 /*----------------------------------------------------------------------------------------
  *                  T Y P E D E F S     A N D     S T R U C T U  R E S
 
 /*----------------------------------------------------------------------------------------
  *                  T Y P E D E F S     A N D     S T R U C T U  R E S


@@ -64,17 +64,17 @@ VOID *AcpiAlib    = NULL;
  *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
  *----------------------------------------------------------------------------------------
  */
  *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
  *----------------------------------------------------------------------------------------
  */

- 
+

 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */

- 
+

 /*---------------------------------------------------------------------------------------
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */
 /*---------------------------------------------------------------------------------------
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */

-UINT32 
+UINT32

 agesawrapper_amdinitcpuio (
   VOID
   )
 agesawrapper_amdinitcpuio (
   VOID
   )


@@ -84,11 +84,11 @@ agesawrapper_amdinitcpuio (
   UINT32                        PciData;
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;
   UINT32                        PciData;
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;

-  
+

   /* Enable legacy video routing: D18F1xF4 VGA Enable */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
   PciData = 1;
   /* Enable legacy video routing: D18F1xF4 VGA Enable */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
   PciData = 1;

-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

 
   /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
    * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
 
   /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
    * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are


@@ -97,21 +97,21 @@ agesawrapper_amdinitcpuio (
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
   PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
   PciData |= 1 << 7;    // set NP (non-posted) bit
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
   PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
   PciData |= 1 << 7;    // set NP (non-posted) bit

-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
   PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
   PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000

-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-   
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+

   /* Map the remaining PCI hole as posted MMIO */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
   PciData = 0x00FECF00; // last address before non-posted range
   /* Map the remaining PCI hole as posted MMIO */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
   PciData = 0x00FECF00; // last address before non-posted range

-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

   LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
   MsrReg = (MsrReg >> 8) | 3;
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
   PciData = (UINT32)MsrReg;
   LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
   MsrReg = (MsrReg >> 8) | 3;
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
   PciData = (UINT32)MsrReg;

-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-   
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+

   /* Send all IO (0000-FFFF) to southbridge. */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
   PciData = 0x0000F000;
   /* Send all IO (0000-FFFF) to southbridge. */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
   PciData = 0x0000F000;


@@ -122,8 +122,8 @@ agesawrapper_amdinitcpuio (
   Status = AGESA_SUCCESS;
   return (UINT32)Status;
 }
   Status = AGESA_SUCCESS;
   return (UINT32)Status;
 }

- 
-UINT32 
+
+UINT32

 agesawrapper_amdinitmmio (
   VOID
   )
 agesawrapper_amdinitmmio (
   VOID
   )


@@ -133,7 +133,7 @@ agesawrapper_amdinitmmio (
   UINT32                        PciData;
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;
   UINT32                        PciData;
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;

-  
+

   /*
    Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
    Address MSR register.
   /*
    Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
    Address MSR register.


@@ -141,27 +141,27 @@ agesawrapper_amdinitmmio (
 
   MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
   LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
 
   MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
   LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);

-  
+

   /*
    Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
   */
   LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
   MsrReg = MsrReg | 0x0000400000000000;
   LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
   /*
    Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
   */
   LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
   MsrReg = MsrReg | 0x0000400000000000;
   LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);

-  
+

   /* Set Ontario Link Data */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
   PciData = 0x01308002;
   /* Set Ontario Link Data */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
   PciData = 0x01308002;

-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
   PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
   PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;

-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-  
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+

   Status = AGESA_SUCCESS;
   return (UINT32)Status;
 }
 
   Status = AGESA_SUCCESS;
   return (UINT32)Status;
 }
 

-UINT32 
+UINT32

 agesawrapper_amdinitreset (
   VOID
   )
 agesawrapper_amdinitreset (
   VOID
   )


@@ -169,7 +169,7 @@ agesawrapper_amdinitreset (
   AGESA_STATUS status;
   AMD_INTERFACE_PARAMS AmdParamStruct;
   AMD_RESET_PARAMS AmdResetParams;
   AGESA_STATUS status;
   AMD_INTERFACE_PARAMS AmdParamStruct;
   AMD_RESET_PARAMS AmdResetParams;

-  
+

   LibAmdMemFill (&AmdParamStruct,
                  0,
                  sizeof (AMD_INTERFACE_PARAMS),
   LibAmdMemFill (&AmdParamStruct,
                  0,
                  sizeof (AMD_INTERFACE_PARAMS),


@@ -191,14 +191,14 @@ agesawrapper_amdinitreset (
   AmdParamStruct.StdHeader.ImageBasePtr = 0;
   AmdCreateStruct (&AmdParamStruct);
   AmdResetParams.HtConfig.Depth = 0;
   AmdParamStruct.StdHeader.ImageBasePtr = 0;
   AmdCreateStruct (&AmdParamStruct);
   AmdResetParams.HtConfig.Depth = 0;

-  
+

   status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
   if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
   AmdReleaseStruct (&AmdParamStruct);
   return (UINT32)status;
   status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
   if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
   AmdReleaseStruct (&AmdParamStruct);
   return (UINT32)status;

- }  
-  
-UINT32 
+ }
+
+UINT32

 agesawrapper_amdinitearly (
   VOID
   )
 agesawrapper_amdinitearly (
   VOID
   )


@@ -206,7 +206,7 @@ agesawrapper_amdinitearly (
   AGESA_STATUS status;
   AMD_INTERFACE_PARAMS AmdParamStruct;
   AMD_EARLY_PARAMS     *AmdEarlyParamsPtr;
   AGESA_STATUS status;
   AMD_INTERFACE_PARAMS AmdParamStruct;
   AMD_EARLY_PARAMS     *AmdEarlyParamsPtr;

-  
+

   LibAmdMemFill (&AmdParamStruct,
                  0,
                  sizeof (AMD_INTERFACE_PARAMS),
   LibAmdMemFill (&AmdParamStruct,
                  0,
                  sizeof (AMD_INTERFACE_PARAMS),


@@ -219,10 +219,10 @@ agesawrapper_amdinitearly (
   AmdParamStruct.StdHeader.Func = 0;
   AmdParamStruct.StdHeader.ImageBasePtr = 0;
   AmdCreateStruct (&AmdParamStruct);
   AmdParamStruct.StdHeader.Func = 0;
   AmdParamStruct.StdHeader.ImageBasePtr = 0;
   AmdCreateStruct (&AmdParamStruct);

-  
+

   AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
   OemCustomizeInitEarly (AmdEarlyParamsPtr);
   AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
   OemCustomizeInitEarly (AmdEarlyParamsPtr);

-  
+

   status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
   if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
   AmdReleaseStruct (&AmdParamStruct);
   status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
   if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
   AmdReleaseStruct (&AmdParamStruct);


@@ -230,7 +230,7 @@ agesawrapper_amdinitearly (
   return (UINT32)status;
 }
 
   return (UINT32)status;
 }
 

-UINT32 
+UINT32

 agesawrapper_amdinitpost (
   VOID
   )
 agesawrapper_amdinitpost (
   VOID
   )


@@ -272,7 +272,7 @@ agesawrapper_amdinitpost (
   return (UINT32)status;
 }
 
   return (UINT32)status;
 }
 

-UINT32 
+UINT32

 agesawrapper_amdinitenv (
   VOID
   )
 agesawrapper_amdinitenv (
   VOID
   )


@@ -299,7 +299,7 @@ agesawrapper_amdinitenv (
   /* Initialize Subordinate Bus Number and Secondary Bus Number
    * In platform BIOS this address is allocated by PCI enumeration code
      Modify D1F0x18
   /* Initialize Subordinate Bus Number and Secondary Bus Number
    * In platform BIOS this address is allocated by PCI enumeration code
      Modify D1F0x18

-   */  
+   */

   PciAddress.Address.Bus = 0;
   PciAddress.Address.Device = 1;
   PciAddress.Address.Function = 0;
   PciAddress.Address.Bus = 0;
   PciAddress.Address.Device = 1;
   PciAddress.Address.Function = 0;


@@ -399,17 +399,17 @@ agesawrapper_getlateinitptr (
   }
 }
 
   }
 }
 

-UINT32 
+UINT32

 agesawrapper_amdinitmid (
   VOID
   )
 {
   AGESA_STATUS status;
   AMD_INTERFACE_PARAMS AmdParamStruct;
 agesawrapper_amdinitmid (
   VOID
   )
 {
   AGESA_STATUS status;
   AMD_INTERFACE_PARAMS AmdParamStruct;

-  
+

   /* Enable MMIO on AMD CPU Address Map Controller */
   agesawrapper_amdinitcpuio ();
   /* Enable MMIO on AMD CPU Address Map Controller */
   agesawrapper_amdinitcpuio ();

-  
+

   LibAmdMemFill (&AmdParamStruct,
                  0,
                  sizeof (AMD_INTERFACE_PARAMS),
   LibAmdMemFill (&AmdParamStruct,
                  0,
                  sizeof (AMD_INTERFACE_PARAMS),


@@ -431,7 +431,7 @@ agesawrapper_amdinitmid (
   return (UINT32)status;
 }
 
   return (UINT32)status;
 }
 

-UINT32 
+UINT32

 agesawrapper_amdinitlate (
   VOID
   )
 agesawrapper_amdinitlate (
   VOID
   )


@@ -467,10 +467,10 @@ agesawrapper_amdinitlate (
   return (UINT32)Status;
 }
 
   return (UINT32)Status;
 }
 

-UINT32 
+UINT32

 agesawrapper_amdlaterunaptask (
 agesawrapper_amdlaterunaptask (

-  UINT32 Func, 
-  UINT32 Data, 
+  UINT32 Func,
+  UINT32 Data,

   VOID *ConfigPtr
   )
 {
   VOID *ConfigPtr
   )
 {


@@ -499,7 +499,7 @@ agesawrapper_amdlaterunaptask (
   return (UINT32)Status;
 }
 
   return (UINT32)Status;
 }
 

-UINT32 
+UINT32

 agesawrapper_amdreadeventlog (
   VOID
   )
 agesawrapper_amdreadeventlog (
   VOID
   )

diff --git a/src/mainboard/asrock/e350m1/agesawrapper.h b/src/mainboard/asrock/e350m1/agesawrapper.h
index 6d7d9cd196b031fa4d6b208bc5a295f6650f3012..21e43fe23839faa98542d9eb45a0dccd4d6696c0 100644 (file)
--- a/src/mainboard/asrock/e350m1/agesawrapper.h
+++ b/src/mainboard/asrock/e350m1/agesawrapper.h
@@ -21,8 +21,8 @@
  *                             M O D U L E S    U S E D
  *----------------------------------------------------------------------------------------
  */
  *                             M O D U L E S    U S E D
  *----------------------------------------------------------------------------------------
  */

- 
-  
+
+

 #ifndef _AGESAWRAPPER_H_
 #define _AGESAWRAPPER_H_
 
 #ifndef _AGESAWRAPPER_H_
 #define _AGESAWRAPPER_H_
 


@@ -66,17 +66,17 @@ typedef struct {
  *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
  *----------------------------------------------------------------------------------------
  */
  *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
  *----------------------------------------------------------------------------------------
  */

- 
+

 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */

- 
+

 /*---------------------------------------------------------------------------------------
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */
 /*---------------------------------------------------------------------------------------
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */

- 
+

 UINT32 agesawrapper_amdinitreset (void);
 UINT32 agesawrapper_amdinitearly (void);
 UINT32 agesawrapper_amdinitenv (void);
 UINT32 agesawrapper_amdinitreset (void);
 UINT32 agesawrapper_amdinitearly (void);
 UINT32 agesawrapper_amdinitenv (void);

diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c
index cde9df7c5f8657ac0d64e53d8080b49a2a00e3f1..2707605b9b725a923a523c0a7603763628f53c5d 100644 (file)
--- a/src/mainboard/asrock/e350m1/buildOpts.c
+++ b/src/mainboard/asrock/e350m1/buildOpts.c
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

- 
+

 /**
  * @file
  *
 /**
  * @file
  *


@@ -57,13 +57,13 @@
 #define INSTALL_FT1_SOCKET_SUPPORT  TRUE
 #define INSTALL_AM3_SOCKET_SUPPORT  FALSE
 
 #define INSTALL_FT1_SOCKET_SUPPORT  TRUE
 #define INSTALL_AM3_SOCKET_SUPPORT  FALSE
 

-/* 
- * Agesa optional capabilities selection.  
+/*
+ * Agesa optional capabilities selection.

  * Uncomment and mark FALSE those features you wish to include in the build.
  * Comment out or mark TRUE those features you want to REMOVE from the build.
  */
 
  * Uncomment and mark FALSE those features you wish to include in the build.
  * Comment out or mark TRUE those features you want to REMOVE from the build.
  */
 

-#define BLDOPT_REMOVE_FAMILY_10_SUPPORT       TRUE    
+#define BLDOPT_REMOVE_FAMILY_10_SUPPORT       TRUE

 #define BLDOPT_REMOVE_FAMILY_12_SUPPORT       TRUE
 #define BLDOPT_REMOVE_FAMILY_14_SUPPORT       FALSE
 #define BLDOPT_REMOVE_FAMILY_15_SUPPORT       TRUE
 #define BLDOPT_REMOVE_FAMILY_12_SUPPORT       TRUE
 #define BLDOPT_REMOVE_FAMILY_14_SUPPORT       FALSE
 #define BLDOPT_REMOVE_FAMILY_15_SUPPORT       TRUE


@@ -104,7 +104,7 @@
 #define BLDOPT_REMOVE_HT_ASSIST         TRUE
 #define BLDOPT_REMOVE_ATM_MODE          TRUE
 //#define BLDOPT_REMOVE_MSG_BASED_C1E       TRUE
 #define BLDOPT_REMOVE_HT_ASSIST         TRUE
 #define BLDOPT_REMOVE_ATM_MODE          TRUE
 //#define BLDOPT_REMOVE_MSG_BASED_C1E       TRUE

-//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE  
+//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE

 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT     FALSE
 //#define BLDOPT_REMOVE_C6_STATE          TRUE
 #define BLDOPT_REMOVE_GFX_RECOVERY        TRUE
 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT     FALSE
 //#define BLDOPT_REMOVE_C6_STATE          TRUE
 #define BLDOPT_REMOVE_GFX_RECOVERY        TRUE


@@ -125,10 +125,10 @@
 #define AGESA_ENTRY_INIT_LATE_RESTORE             FALSE
 #define AGESA_ENTRY_INIT_GENERAL_SERVICES         FALSE
 
 #define AGESA_ENTRY_INIT_LATE_RESTORE             FALSE
 #define AGESA_ENTRY_INIT_GENERAL_SERVICES         FALSE
 

-/* 
- * Agesa configuration values selection.  
+/*
+ * Agesa configuration values selection.

  * Uncomment and specify the value for the configuration options
  * Uncomment and specify the value for the configuration options

- * needed by the system. 
+ * needed by the system.

  */
 
 /* The fixed MTRR values to be set after memory initialization. */
  */
 
 /* The fixed MTRR values to be set after memory initialization. */

diff --git a/src/mainboard/asrock/e350m1/dimmSpd.c b/src/mainboard/asrock/e350m1/dimmSpd.c
index 8ef1b4c6500c9346e8b59120d15a21d09817f779..24e2617c0f86aa6cc242c52669ecb111352f5a60 100644 (file)
--- a/src/mainboard/asrock/e350m1/dimmSpd.c
+++ b/src/mainboard/asrock/e350m1/dimmSpd.c
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

- 
+

 #include "Porting.h"
 #include "AGESA.h"
 #include "amdlib.h"
 #include "Porting.h"
 #include "AGESA.h"
 #include "amdlib.h"


@@ -55,7 +55,7 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
    UINT64 limit;
 
    address |= 1; // set read bit
    UINT64 limit;
 
    address |= 1; // set read bit

-   
+

    __outbyte (iobase + 0, 0xFF);                // clear error status
    __outbyte (iobase + 1, 0x1F);                // clear error status
    __outbyte (iobase + 3, offset);              // offset in eeprom
    __outbyte (iobase + 0, 0xFF);                // clear error status
    __outbyte (iobase + 1, 0x1F);                // clear error status
    __outbyte (iobase + 3, offset);              // offset in eeprom


@@ -112,7 +112,7 @@ static int readSmbusByte (int iobase, int address, char *buffer)
  *
  * readspd - Read one or more SPD bytes from a DIMM.
  *           Start with offset zero and read sequentially.
  *
  * readspd - Read one or more SPD bytes from a DIMM.
  *           Start with offset zero and read sequentially.

- *           Optimization relies on autoincrement to avoid 
+ *           Optimization relies on autoincrement to avoid

  *           sending offset for every byte.
  *          Reads 128 bytes in 7-8 ms at 400 KHz.
  */
  *           sending offset for every byte.
  *          Reads 128 bytes in 7-8 ms at 400 KHz.
  */


@@ -131,7 +131,7 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
       error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
       if (error) return error;
       }
       error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
       if (error) return error;
       }

-   
+

    return 0;
    }
 
    return 0;
    }
 


@@ -154,11 +154,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
    {
    int spdAddress, ioBase;
 
    {
    int spdAddress, ioBase;
 

-   if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR; 
-   if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR; 
+   if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR;
+   if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR;

    if (info->DimmId       >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
    if (info->DimmId       >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;

-   
-   spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; 
+
+   spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];

    if (spdAddress == 0) return AGESA_ERROR;
    ioBase = 0xB00;
    setupFch (ioBase);
    if (spdAddress == 0) return AGESA_ERROR;
    ioBase = 0xB00;
    setupFch (ioBase);

diff --git a/src/mainboard/asrock/e350m1/get_bus_conf.c b/src/mainboard/asrock/e350m1/get_bus_conf.c
index 43867172d52e6e630388381a661ccb10d37c7d03..9746248e8734abe042e5df2a56ab90ac8be90a4a 100644 (file)
--- a/src/mainboard/asrock/e350m1/get_bus_conf.c
+++ b/src/mainboard/asrock/e350m1/get_bus_conf.c
@@ -68,22 +68,22 @@ void get_bus_conf(void)
  * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
  * but functionally within the coreboot model, this is the best place to make the
  * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
  * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
  * but functionally within the coreboot model, this is the best place to make the
  * call.  The logically correct place to call AmdInitLate is after PCI scan is done,

- * after the decision about S3 resume is made, and before the system tables are 
- * written into RAM.  The routine that is responsible for writing the tables is 
- * "write_tables", called near the end of "hardwaremain".  There is no platform 
- * specific entry point between the S3 resume decision point and the call to 
- * "write_tables", and the next platform specific entry points are the calls to 
- * the ACPI table write functions.  The first of ose would seem to be the right 
- * place, but other table write functions, e.g. the PIRQ table write function, are 
+ * after the decision about S3 resume is made, and before the system tables are
+ * written into RAM.  The routine that is responsible for writing the tables is
+ * "write_tables", called near the end of "hardwaremain".  There is no platform
+ * specific entry point between the S3 resume decision point and the call to
+ * "write_tables", and the next platform specific entry points are the calls to
+ * the ACPI table write functions.  The first of ose would seem to be the right
+ * place, but other table write functions, e.g. the PIRQ table write function, are

  * called before the ACPI tables are written.  This routine is called at the beginning
  * of each of the write functions called prior to the ACPI write functions, so this
  * becomes the best place for this call.
  */
  * called before the ACPI tables are written.  This routine is called at the beginning
  * of each of the write functions called prior to the ACPI write functions, so this
  * becomes the best place for this call.
  */

-  status = agesawrapper_amdinitlate(); 
+  status = agesawrapper_amdinitlate();

   if(status) {
     printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
   }
   if(status) {
     printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
   }

-       
+

   sbdn_sb800 = 0;
 
   for (i = 0; i < 3; i++) {
   sbdn_sb800 = 0;
 
   for (i = 0; i < 3; i++) {

diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index 397e82995a8988f8d532a23d59d3ffc766674af6..960c2c86f1892bfc298d913645cf4c2d7d0eb339 100644 (file)
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -60,11 +60,11 @@ static void *smp_write_config_table(void *v)
   mptable_write_buses(mc, NULL, &bus_isa);
 
   /* I/O APICs:   APIC ID Version State   Address */
   mptable_write_buses(mc, NULL, &bus_isa);
 
   /* I/O APICs:   APIC ID Version State   Address */

-  
+

   device_t dev;
   u32 dword;
   u8 byte;
   device_t dev;
   u32 dword;
   u8 byte;

-    
+

   ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
   dword &= 0xFFFFFFF0;
   smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
   ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
   dword &= 0xFFFFFFF0;
   smp_write_ioapic(mc, apicid_sb800, 0x21, dword);


@@ -108,7 +108,7 @@ static void *smp_write_config_table(void *v)
   /* PCI_INT(0x0, 0x14, 0x2, 0x12); */
 
   /* on board NIC & Slot PCIE.  */
   /* PCI_INT(0x0, 0x14, 0x2, 0x12); */
 
   /* on board NIC & Slot PCIE.  */

-  
+

   /* PCI slots */
   /* PCI_SLOT 0. */
   PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
   /* PCI slots */
   /* PCI_SLOT 0. */
   PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);

diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c
index f7782439709ff23c8b0f15878aa3b7010fc49fcb..7fa4ee7404753e717de5f9906c3376ce9f5c75d9 100644 (file)
--- a/src/mainboard/asus/m5a88-v/mainboard.c
+++ b/src/mainboard/asus/m5a88-v/mainboard.c
@@ -43,7 +43,7 @@ void enable_int_gfx(void)
 #ifdef UNUSED_CODE
        RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */
        RWPMIO(SB_PMIOA_REGF6, AccWidthuint8, ~(BIT0), BIT0); /* Disable Gec */
 #ifdef UNUSED_CODE
        RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */
        RWPMIO(SB_PMIOA_REGF6, AccWidthuint8, ~(BIT0), BIT0); /* Disable Gec */

-#endif 
+#endif

        /* make sure the MMIO(fed80000) is accessible */
        RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
 
        /* make sure the MMIO(fed80000) is accessible */
        RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
 

diff --git a/src/mainboard/getac/p470/acpi_slic.c b/src/mainboard/getac/p470/acpi_slic.c
index 5744efad903fb5eb33d7b22f6f5b6a5fd958eb5e..b042f36c7c9989f343b79efbe7852e226c92115e 100644 (file)
--- a/src/mainboard/getac/p470/acpi_slic.c
+++ b/src/mainboard/getac/p470/acpi_slic.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
 /*
  * This file is part of the coreboot project.

- * 
+ *

  * Copyright (C) 2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
  * Copyright (C) 2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or

diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c
index 46e7b886b1601ec7245ac96ab9c602cc5e11be61..676d6610bea33ac25f31904a0c3aef830525844e 100644 (file)
--- a/src/mainboard/getac/p470/acpi_tables.c
+++ b/src/mainboard/getac/p470/acpi_tables.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
 /*
  * This file is part of the coreboot project.

- * 
+ *

  * Copyright (C) 2007-2010 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
  * Copyright (C) 2007-2010 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or


@@ -87,7 +87,7 @@ static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
 
 static long acpi_create_ecdt(acpi_ecdt_t * ecdt)
 {
 
 static long acpi_create_ecdt(acpi_ecdt_t * ecdt)
 {

-       /* Attention: Make sure these match the values from 
+       /* Attention: Make sure these match the values from

         * the DSDT's ec.asl
         */
        static const char ec_id[] = "\\_SB.PCI0.LPCB.EC0";
         * the DSDT's ec.asl
         */
        static const char ec_id[] = "\\_SB.PCI0.LPCB.EC0";


@@ -120,7 +120,7 @@ static long acpi_create_ecdt(acpi_ecdt_t * ecdt)
        ecdt->ec_data.addrh = 0;
 
        ecdt->uid = 1; // Must match _UID of the EC0 node.
        ecdt->ec_data.addrh = 0;
 
        ecdt->uid = 1; // Must match _UID of the EC0 node.

-       
+

        ecdt->gpe_bit = 23; // SCI interrupt within GPEx_STS
 
        strncpy((char *)ecdt->ec_id, ec_id, strlen(ec_id));
        ecdt->gpe_bit = 23; // SCI interrupt within GPEx_STS
 
        strncpy((char *)ecdt->ec_id, ec_id, strlen(ec_id));


@@ -260,7 +260,7 @@ unsigned long write_acpi_tables(unsigned long start)
        current += dsdt->length;
        memcpy(dsdt, &AmlCode, dsdt->length);
 
        current += dsdt->length;
        memcpy(dsdt, &AmlCode, dsdt->length);
 

-       /* Fix up global NVS region for SMI handler. The GNVS region lives 
+       /* Fix up global NVS region for SMI handler. The GNVS region lives

         * in the (high) table area. The low memory map looks like this:
         *
         * 0x00000000 - 0x000003ff      Real Mode IVT
         * in the (high) table area. The low memory map looks like this:
         *
         * 0x00000000 - 0x000003ff      Real Mode IVT


@@ -313,7 +313,7 @@ unsigned long write_acpi_tables(unsigned long start)
 
        current += 0x100;
        ALIGN_CURRENT;
 
        current += 0x100;
        ALIGN_CURRENT;

-       
+

        /* And tell SMI about it */
        smm_setup_structures(gnvs, NULL, smi1);
 
        /* And tell SMI about it */
        smm_setup_structures(gnvs, NULL, smi1);
 

diff --git a/src/mainboard/getac/p470/chip.h b/src/mainboard/getac/p470/chip.h
index db732d287659a01e3997fce620d119b4c44de319..b75c381e31f72b6a62e9e57e44bd98d33fdf1c35 100644 (file)
--- a/src/mainboard/getac/p470/chip.h
+++ b/src/mainboard/getac/p470/chip.h
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
 /*
  * This file is part of the coreboot project.

- * 
+ *

  * Copyright (C) 2007-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
  * Copyright (C) 2007-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or

diff --git a/src/mainboard/getac/p470/ec_oem.c b/src/mainboard/getac/p470/ec_oem.c
index 30d41359cf2a668e3bc4ce76fa2ee1a5a1c3352c..f742f3f72abb1b782b0740d5c8bde608df808967 100644 (file)
--- a/src/mainboard/getac/p470/ec_oem.c
+++ b/src/mainboard/getac/p470/ec_oem.c
@@ -36,7 +36,7 @@ int send_ec_oem_command(u8 command)
                        printk(BIOS_SPEW, ".");
        }
        if (!timeout) {
                        printk(BIOS_SPEW, ".");
        }
        if (!timeout) {

-               printk(BIOS_DEBUG, "Timeout while sending OEM command 0x%02x to EC!\n", 
+               printk(BIOS_DEBUG, "Timeout while sending OEM command 0x%02x to EC!\n",

                                command);
                // return -1;
        }
                                command);
                // return -1;
        }


@@ -124,7 +124,7 @@ int ec_oem_dump_status(void)
        if (ec_sc & (1 << 1)) printk(BIOS_DEBUG, "IBF ");
        if (ec_sc & (1 << 0)) printk(BIOS_DEBUG, "OBF ");
        printk(BIOS_DEBUG, "\n");
        if (ec_sc & (1 << 1)) printk(BIOS_DEBUG, "IBF ");
        if (ec_sc & (1 << 0)) printk(BIOS_DEBUG, "OBF ");
        printk(BIOS_DEBUG, "\n");

-       
+

        return ec_sc;
 }
 
        return ec_sc;
 }
 

diff --git a/src/mainboard/getac/p470/hda_verb.h b/src/mainboard/getac/p470/hda_verb.h
index 0edd0f3607134d5cfd9f88efa6a9bd78190d81c8..98a77c6e12f4c0ad4f0321f5c9ded6228d9caaec 100644 (file)
--- a/src/mainboard/getac/p470/hda_verb.h
+++ b/src/mainboard/getac/p470/hda_verb.h
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
 /*
  * This file is part of the coreboot project.

- * 
+ *

  * Copyright (C) 2007-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
  * Copyright (C) 2007-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or

diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c
index 8f8a39544c0cf0cd67a2b854a18b86a1cdb97d19..b7a248dbfd0ec1d1c12153b62efc49c6f7be20f3 100644 (file)
--- a/src/mainboard/getac/p470/mainboard.c
+++ b/src/mainboard/getac/p470/mainboard.c
@@ -32,7 +32,7 @@
 
 #define MAX_LCD_BRIGHTNESS     0xd8
 
 
 #define MAX_LCD_BRIGHTNESS     0xd8
 

-static void ec_enable(void) 
+static void ec_enable(void)

 {
        u16 keymap;
        /* Enable Hotkey SCI */
 {
        u16 keymap;
        /* Enable Hotkey SCI */


@@ -59,11 +59,11 @@ static void pcie_limit_power(void)
 {
 #if 0
        // This piece of code needs further debugging as it crashes the
 {
 #if 0
        // This piece of code needs further debugging as it crashes the

-       // machine. It should set the slot numbers and enable power 
+       // machine. It should set the slot numbers and enable power

        // limitation for the PCIe slots.
 
        device_t dev;
        // limitation for the PCIe slots.
 
        device_t dev;

-       
+

        dev = dev_find_slot(0, PCI_DEVFN(28,0));
        if (dev) pci_write_config32(dev, 0x54, 0x0010a0e0);
 
        dev = dev_find_slot(0, PCI_DEVFN(28,0));
        if (dev) pci_write_config32(dev, 0x54, 0x0010a0e0);
 


@@ -89,9 +89,9 @@ static void mainboard_init(device_t dev)
        ec_enable();
 }
 
        ec_enable();
 }
 

-// mainboard_enable is executed as first thing after 
+// mainboard_enable is executed as first thing after

 // enumerate_buses(). Is there no mainboard_init()?
 // enumerate_buses(). Is there no mainboard_init()?

-static void mainboard_enable(device_t dev) 
+static void mainboard_enable(device_t dev)

 {
        dev->ops->init = mainboard_init;
        pcie_limit_power();
 {
        dev->ops->init = mainboard_init;
        pcie_limit_power();

diff --git a/src/mainboard/getac/p470/mainboard_smi.c b/src/mainboard/getac/p470/mainboard_smi.c
index d29fe587c8ac69bddb13a5f69d32a752f1755403..4a5a3ffbbb8bf61a8e303aa5cca049bc2d40ad5c 100644 (file)
--- a/src/mainboard/getac/p470/mainboard_smi.c
+++ b/src/mainboard/getac/p470/mainboard_smi.c
@@ -30,7 +30,7 @@
 
 #define MAX_LCD_BRIGHTNESS 0xd8
 
 
 #define MAX_LCD_BRIGHTNESS 0xd8
 

-/* The southbridge SMI handler checks whether gnvs has a 
+/* The southbridge SMI handler checks whether gnvs has a

  * valid pointer before calling the trap handler
  */
 extern global_nvs_t *gnvs;
  * valid pointer before calling the trap handler
  */
 extern global_nvs_t *gnvs;

diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 6fa26202579ca899d85744676824e41ed792059a..afad4bc82093d83633051410c340f935395aaae8 100644 (file)
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
 /*
  * This file is part of the coreboot project.

- * 
+ *

  * Copyright (C) 2007-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
  * Copyright (C) 2007-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or


@@ -320,7 +320,7 @@ void main(unsigned long bist)
 
        /* Enable SPD ROMs and DDR-II DRAM */
        enable_smbus();
 
        /* Enable SPD ROMs and DDR-II DRAM */
        enable_smbus();

-       
+

 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
        dump_spd_registers();
 #endif
 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
        dump_spd_registers();
 #endif


@@ -330,8 +330,8 @@ void main(unsigned long bist)
        /* Perform some initialization that must run before stage2 */
        early_ich7_init();
 
        /* Perform some initialization that must run before stage2 */
        early_ich7_init();
 

-       /* This should probably go away. Until now it is required 
-        * and mainboard specific 
+       /* This should probably go away. Until now it is required
+        * and mainboard specific

         */
        rcba_config();
 
         */
        rcba_config();
 


@@ -373,7 +373,7 @@ void main(unsigned long bist)
                 * memory completely, but that's a wonderful clean up task for another
                 * day.
                 */
                 * memory completely, but that's a wonderful clean up task for another
                 * day.
                 */

-               if (resume_backup_memory) 
+               if (resume_backup_memory)

                        memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
 
                /* Magic for S3 resume */
                        memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
 
                /* Magic for S3 resume */

diff --git a/src/mainboard/getac/p470/rtl8168.c b/src/mainboard/getac/p470/rtl8168.c
index f0f98d20f49b7d4102fe758a53638aeea20d3985..37ef6743623a417929d51f27e31b24554e57bb73 100644 (file)
--- a/src/mainboard/getac/p470/rtl8168.c
+++ b/src/mainboard/getac/p470/rtl8168.c
@@ -29,7 +29,7 @@
 static void nic_init(struct device *dev)
 {
        printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n");
 static void nic_init(struct device *dev)
 {
        printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n");

-       // Nothing to do yet, but this has to be here to keep 
+       // Nothing to do yet, but this has to be here to keep

        // coreboot from trying to execute an option ROM.
 
 #ifdef RTL8168_DEBUG
        // coreboot from trying to execute an option ROM.
 
 #ifdef RTL8168_DEBUG

diff --git a/src/mainboard/gigabyte/m57sli/mainboard.c b/src/mainboard/gigabyte/m57sli/mainboard.c
index 3b7eb7d49fb451b24ccee23325c1080aecbf9265..b198fb67c5d00ab580bc0da99782816b30e2d7b9 100644 (file)
--- a/src/mainboard/gigabyte/m57sli/mainboard.c
+++ b/src/mainboard/gigabyte/m57sli/mainboard.c
@@ -34,7 +34,7 @@ static void verb_setup(void)
        // cim_verb_data_size = sizeof(mainboard_cim_verb_data);
 }
 
        // cim_verb_data_size = sizeof(mainboard_cim_verb_data);
 }
 

-static void mainboard_enable(device_t dev) 
+static void mainboard_enable(device_t dev)

 {
        verb_setup();
 }
 {
        verb_setup();
 }

diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index d40df6b95d2bcf66f0b592d0ba2501cfd104ca1a..32a94d425bc8f795192ae7e130ec9f815b5be9fe 100644 (file)
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -105,7 +105,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        struct sys_info *sysinfo =  (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
        u32 bsp_apicid = 0, val;
        msr_t msr;
        struct sys_info *sysinfo =  (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
        u32 bsp_apicid = 0, val;
        msr_t msr;

- 
+

        if (!cpu_init_detectedx && boot_cpu()) {
                /* Nothing special needs to be done to find bus 0 */
                /* Allow the HT devices to be found */
        if (!cpu_init_detectedx && boot_cpu()) {
                /* Nothing special needs to be done to find bus 0 */
                /* Allow the HT devices to be found */

diff --git a/src/mainboard/msi/ms9282/mainboard.c b/src/mainboard/msi/ms9282/mainboard.c
index bbb1024bf7e9b29359c41b405995487bee75b365..99f7e224d1676c896e1056d6b1189178132911a1 100644 (file)
--- a/src/mainboard/msi/ms9282/mainboard.c
+++ b/src/mainboard/msi/ms9282/mainboard.c
@@ -34,7 +34,7 @@ static void verb_setup(void)
        // cim_verb_data_size = sizeof(mainboard_cim_verb_data);
 }
 
        // cim_verb_data_size = sizeof(mainboard_cim_verb_data);
 }
 

-static void mainboard_enable(device_t dev) 
+static void mainboard_enable(device_t dev)

 {
        verb_setup();
 }
 {
        verb_setup();
 }

diff --git a/src/mainboard/msi/ms9652_fam10/mainboard.c b/src/mainboard/msi/ms9652_fam10/mainboard.c
index af793c7f9c7312d03e4e2368b6a75fe1d01b4dc8..255b22d74f88b0e2589a4602a788cba2696384db 100644 (file)
--- a/src/mainboard/msi/ms9652_fam10/mainboard.c
+++ b/src/mainboard/msi/ms9652_fam10/mainboard.c
@@ -34,7 +34,7 @@ static void verb_setup(void)
        // cim_verb_data_size = sizeof(mainboard_cim_verb_data);
 }
 
        // cim_verb_data_size = sizeof(mainboard_cim_verb_data);
 }
 

-static void mainboard_enable(device_t dev) 
+static void mainboard_enable(device_t dev)

 {
        verb_setup();
 }
 {
        verb_setup();
 }

diff --git a/src/mainboard/nvidia/l1_2pvv/hda_verb.h b/src/mainboard/nvidia/l1_2pvv/hda_verb.h
index 0b7aac8566f7407179d69ed0f35be6899c89707c..054a3699bce1cb9bde1421d8d7797b11ab2fefe4 100644 (file)
--- a/src/mainboard/nvidia/l1_2pvv/hda_verb.h
+++ b/src/mainboard/nvidia/l1_2pvv/hda_verb.h
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
 /*
  * This file is part of the coreboot project.

- * 
+ *

  * Copyright (C) 2004 Tyan Computer
  * Copyright (C) 2006-2007 AMD
  * Copyright (C) 2007-2009 coresystems GmbH
  * Copyright (C) 2004 Tyan Computer
  * Copyright (C) 2006-2007 AMD
  * Copyright (C) 2007-2009 coresystems GmbH

diff --git a/src/mainboard/nvidia/l1_2pvv/mainboard.c b/src/mainboard/nvidia/l1_2pvv/mainboard.c
index 4c6f0c0290b72c9cac31c20e1b1b6208b652574a..b425c3d80fbb00d03e8efd0bc322bf7fb60c9745 100644 (file)
--- a/src/mainboard/nvidia/l1_2pvv/mainboard.c
+++ b/src/mainboard/nvidia/l1_2pvv/mainboard.c
@@ -33,7 +33,7 @@ static void verb_setup(void)
        cim_verb_data_size = sizeof(mainboard_cim_verb_data);
 }
 
        cim_verb_data_size = sizeof(mainboard_cim_verb_data);
 }
 

-static void mainboard_enable(device_t dev) 
+static void mainboard_enable(device_t dev)

 {
        verb_setup();
 }
 {
        verb_setup();
 }

diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c
index fd731f9e7971933e0c7202103efd2501d933972f..b79372aee7f7f7dbb4ad9b0f87e91b299752ea32 100644 (file)
--- a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c
+++ b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c
@@ -128,13 +128,13 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 {
        struct resource *res;
        resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; // default
 {
        struct resource *res;
        resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; // default

-       
+

        device_t dev = dev_find_slot(0,PCI_DEVFN(0,0));
        // we report mmconf base
        res = probe_resource(dev, 0x1C);
        if( res )
                mmconf_base = res->base;
        device_t dev = dev_find_slot(0,PCI_DEVFN(0,0));
        // we report mmconf base
        res = probe_resource(dev, 0x1C);
        if( res )
                mmconf_base = res->base;

-               
+

        current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); // Fix me: should i reserve 255 busses ?
 
        return current;
        current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); // Fix me: should i reserve 255 busses ?
 
        return current;


@@ -180,7 +180,7 @@ unsigned long write_acpi_tables(unsigned long start)
 {
        unsigned long current;
        int i;
 {
        unsigned long current;
        int i;

-       
+

        acpi_rsdp_t *rsdp;
        acpi_rsdt_t *rsdt;
        acpi_srat_t *srat;
        acpi_rsdp_t *rsdp;
        acpi_rsdt_t *rsdt;
        acpi_srat_t *srat;


@@ -192,7 +192,7 @@ unsigned long write_acpi_tables(unsigned long start)
        acpi_facs_t *facs;
        acpi_header_t *dsdt;
        acpi_header_t *ssdt;
        acpi_facs_t *facs;
        acpi_header_t *dsdt;
        acpi_header_t *ssdt;

-       
+

        get_bus_conf();         /* it will get sblk, pci1234, hcdn, and sbdn */
 
        /* Align ACPI tables to 16byte */
        get_bus_conf();         /* it will get sblk, pci1234, hcdn, and sbdn */
 
        /* Align ACPI tables to 16byte */


@@ -204,14 +204,14 @@ unsigned long write_acpi_tables(unsigned long start)
        /* We need at least an RSDP and an RSDT Table */
        rsdp = (acpi_rsdp_t *) current;
        current += sizeof(acpi_rsdp_t);
        /* We need at least an RSDP and an RSDT Table */
        rsdp = (acpi_rsdp_t *) current;
        current += sizeof(acpi_rsdp_t);

-       ALIGN_CURRENT;  
+       ALIGN_CURRENT;

        rsdt = (acpi_rsdt_t *) current;
        current += sizeof(acpi_rsdt_t);
        ALIGN_CURRENT;
        xsdt = (acpi_xsdt_t *) current;
        current += sizeof(acpi_xsdt_t);
        ALIGN_CURRENT;
        rsdt = (acpi_rsdt_t *) current;
        current += sizeof(acpi_rsdt_t);
        ALIGN_CURRENT;
        xsdt = (acpi_xsdt_t *) current;
        current += sizeof(acpi_xsdt_t);
        ALIGN_CURRENT;

-       
+

        /* clear all table memory */
        memset((void *)start, 0, current - start);
 
        /* clear all table memory */
        memset((void *)start, 0, current - start);
 


@@ -234,7 +234,7 @@ unsigned long write_acpi_tables(unsigned long start)
        acpi_create_my_hpet(hpet);
        current += sizeof(acpi_hpet_t);
        acpi_add_table(rsdp, hpet);
        acpi_create_my_hpet(hpet);
        current += sizeof(acpi_hpet_t);
        acpi_add_table(rsdp, hpet);

-       
+

        /* If we want to use HPET Timers Linux wants an MADT */
        printk(BIOS_DEBUG, "ACPI:    * MADT\n");
        madt = (acpi_madt_t *) current;
        /* If we want to use HPET Timers Linux wants an MADT */
        printk(BIOS_DEBUG, "ACPI:    * MADT\n");
        madt = (acpi_madt_t *) current;


@@ -247,15 +247,15 @@ unsigned long write_acpi_tables(unsigned long start)
        mcfg = (acpi_mcfg_t *) current;
        acpi_create_mcfg(mcfg);
        current += mcfg->header.length;
        mcfg = (acpi_mcfg_t *) current;
        acpi_create_mcfg(mcfg);
        current += mcfg->header.length;

-       acpi_add_table(rsdp, mcfg);     
-       
+       acpi_add_table(rsdp, mcfg);
+

        /* SSDT */
        printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
        ssdt = (acpi_header_t *)current;
        acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
        current += ssdt->length;
        /* SSDT */
        printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
        ssdt = (acpi_header_t *)current;
        acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
        current += ssdt->length;

-       acpi_add_table(rsdp, ssdt);     
-       
+       acpi_add_table(rsdp, ssdt);
+

        /* DSDT */
        printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
        dsdt = (acpi_header_t *)current;
        /* DSDT */
        printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
        dsdt = (acpi_header_t *)current;


@@ -267,7 +267,7 @@ unsigned long write_acpi_tables(unsigned long start)
        for (i=0; i < dsdt->length; i++) {
                if (*(u32*)(((u32)dsdt) + i) == 0xBADEAFFE) {
                        printk(BIOS_DEBUG, "ACPI: Patching up globals in DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
        for (i=0; i < dsdt->length; i++) {
                if (*(u32*)(((u32)dsdt) + i) == 0xBADEAFFE) {
                        printk(BIOS_DEBUG, "ACPI: Patching up globals in DSDT at offset 0x%04x -> 0x%08lx\n", i, current);

-                       *(u32*)(((u32)dsdt) + i) = current; 
+                       *(u32*)(((u32)dsdt) + i) = current;

                        break;
                }
        }
                        break;
                }
        }


@@ -277,8 +277,8 @@ unsigned long write_acpi_tables(unsigned long start)
        current += GLOBAL_VARS_SIZE;
        /* We patched up the DSDT, so we need to recalculate the checksum */
        dsdt->checksum = 0;
        current += GLOBAL_VARS_SIZE;
        /* We patched up the DSDT, so we need to recalculate the checksum */
        dsdt->checksum = 0;

-       dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);     
-       printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n", dsdt, dsdt->length);     
+       dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+       printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n", dsdt, dsdt->length);

 
        /* FADT */
        printk(BIOS_DEBUG, "ACPI:    * FADT\n");
 
        /* FADT */
        printk(BIOS_DEBUG, "ACPI:    * FADT\n");

diff --git a/src/mainboard/siemens/sitemp_g1p1/int15_func.c b/src/mainboard/siemens/sitemp_g1p1/int15_func.c
index 0d2da370ff2c60582822c1af7a1d1fe08f51201c..c6531913ae6c8ac695973fe099a4fb8470ba6a38 100644 (file)
--- a/src/mainboard/siemens/sitemp_g1p1/int15_func.c
+++ b/src/mainboard/siemens/sitemp_g1p1/int15_func.c
@@ -20,7 +20,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

- 
+

 #include <stdint.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include <stdint.h>
 #include <stdlib.h>
 #include <console/console.h>


@@ -80,7 +80,7 @@ int sbios_INT15_handler(struct eregs *regs)
                        regs->eax &= ~(0xff);
                        regs->ebx &= ~(0xff);
                        printk(BIOS_DEBUG, "Integrated System Information = %x:%x\n", regs->edx, regs->edi);
                        regs->eax &= ~(0xff);
                        regs->ebx &= ~(0xff);
                        printk(BIOS_DEBUG, "Integrated System Information = %x:%x\n", regs->edx, regs->edi);

-                       vgainfo_addr = (regs->edx * 16) + regs->edi; 
+                       vgainfo_addr = (regs->edx * 16) + regs->edi;

                        res = 0;
                        break;
                case 0x89:
                        res = 0;
                        break;
                case 0x89:

diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c
index 2b726f9b17f865a7cf9adad4ec40746cee22f2e8..60a2ee21887065545117e37cd16d9c12963fc5d6 100644 (file)
--- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c
@@ -4,7 +4,7 @@
  * Copyright (C) 2008 Advanced Micro Devices, Inc.
  * Copyright (C) 2010 Siemens AG, Inc.
  * (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.)
  * Copyright (C) 2008 Advanced Micro Devices, Inc.
  * Copyright (C) 2010 Siemens AG, Inc.
  * (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.)

- * 
+ *

  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.


@@ -18,7 +18,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

- 
+

 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>


@@ -172,7 +172,7 @@ static u32 adt7475_address = ADT7475_ADDRESS;
 
 #define adt7475_write_byte(reg, val) \
        do_smbus_write_byte(smbus_io_base, adt7475_address, reg, val)
 
 #define adt7475_write_byte(reg, val) \
        do_smbus_write_byte(smbus_io_base, adt7475_address, reg, val)

-       
+

 #define TWOS_COMPL 1
 
 struct __table__{
 #define TWOS_COMPL 1
 
 struct __table__{


@@ -284,9 +284,9 @@ static void int15_install(void)
 /* ############################################################################################# */
 
  /**
 /* ############################################################################################# */
 
  /**

- * @brief 
+ * @brief

  *
  *

- * @param 
+ * @param

  */
 
 static u8 calc_trange(u8 t_min, u8 t_max) {
  */
 
 static u8 calc_trange(u8 t_min, u8 t_max) {


@@ -294,7 +294,7 @@ static u8 calc_trange(u8 t_min, u8 t_max) {
        u8 prev;
        int i;
        int diff = t_max - t_min;
        u8 prev;
        int i;
        int diff = t_max - t_min;

-       
+

        // walk through the trange table
        for(i = 0, prev = 0; i < sizeof(trange)/sizeof(int); i++) {
                if( trange[i] < diff ) {
        // walk through the trange table
        for(i = 0, prev = 0; i < sizeof(trange)/sizeof(int); i++) {
                if( trange[i] < diff ) {


@@ -304,7 +304,7 @@ static u8 calc_trange(u8 t_min, u8 t_max) {
                if( diff == trange[i] ) return i;
                if( (diff - trange[prev]) < (trange[i] - diff) ) break; // return with last val index
                return i;
                if( diff == trange[i] ) return i;
                if( (diff - trange[prev]) < (trange[i] - diff) ) break; // return with last val index
                return i;

-       }               
+       }

        return prev;
 }
 
        return prev;
 }
 


@@ -319,7 +319,7 @@ static void cable_detect(void)
        u8 byte;
        struct device *sm_dev;
        struct device *ide_dev;
        u8 byte;
        struct device *sm_dev;
        struct device *ide_dev;

-       
+

        /* SMBus Module and ACPI Block (Device 20, Function 0) on SB600 */
        printk(BIOS_DEBUG, "%s.\n", __func__);
        sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
        /* SMBus Module and ACPI Block (Device 20, Function 0) on SB600 */
        printk(BIOS_DEBUG, "%s.\n", __func__);
        sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));


@@ -327,7 +327,7 @@ static void cable_detect(void)
        byte = pci_read_config8(sm_dev, 0xA9);
        byte |= (1 << 5);       /* Set Gpio9 as input */
        pci_write_config8(sm_dev, 0xA9, byte);
        byte = pci_read_config8(sm_dev, 0xA9);
        byte |= (1 << 5);       /* Set Gpio9 as input */
        pci_write_config8(sm_dev, 0xA9, byte);

-       
+

        /* IDE Controller (Device 20, Function 1) on SB600 */
        ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
 
        /* IDE Controller (Device 20, Function 1) on SB600 */
        ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
 


@@ -347,14 +347,14 @@ static void cable_detect(void)
 /**
  * @brief Detect the ADT7475 device
  *
 /**
  * @brief Detect the ADT7475 device
  *

- * @param 
+ * @param

  */
  */

- 
+

 static const char * adt7475_detect( void ) {
 
         int vendid, devid, devid2;
         const char *name = NULL;
 static const char * adt7475_detect( void ) {
 
         int vendid, devid, devid2;
         const char *name = NULL;

-               
+

         vendid = adt7475_read_byte(REG_VENDID);
         devid2 = adt7475_read_byte(REG_DEVID2);
         if (vendid != 0x41 ||           /* Analog Devices */
         vendid = adt7475_read_byte(REG_VENDID);
         devid2 = adt7475_read_byte(REG_DEVID2);
         if (vendid != 0x41 ||           /* Analog Devices */


@@ -371,7 +371,7 @@ static const char * adt7475_detect( void ) {
                 name = "adt7476";
         else if ((devid2 & 0xfc) == 0x6c)
                 name = "adt7490";
                 name = "adt7476";
         else if ((devid2 & 0xfc) == 0x6c)
                 name = "adt7490";

- 
+

         return name;
 }
 
         return name;
 }
 


@@ -396,7 +396,7 @@ const struct fan_control case_fan_control_defaults = {
 static void pm_init( void )
 {
        u16 word;
 static void pm_init( void )
 {
        u16 word;

-       u8 byte; 
+       u8 byte;

        device_t sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 
        /* set SB600 GPIO 64 to GPIO with pull-up */
        device_t sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 
        /* set SB600 GPIO 64 to GPIO with pull-up */


@@ -423,7 +423,7 @@ static void pm_init( void )
        byte = pm_ioread(0x3c);
        byte &= 0xf3;
        pm_iowrite(0x3c, byte);
        byte = pm_ioread(0x3c);
        byte &= 0xf3;
        pm_iowrite(0x3c, byte);

-       
+

        /* set GPM5 to not wake from s5 */
        byte = pm_ioread(0x77);
        byte &= ~(1 << 5);
        /* set GPM5 to not wake from s5 */
        byte = pm_ioread(0x77);
        byte &= ~(1 << 5);


@@ -433,7 +433,7 @@ static void pm_init( void )
  /**
  * @brief Setup thermal config on SINA Mainboard
  *
  /**
  * @brief Setup thermal config on SINA Mainboard
  *

- * @param 
+ * @param

  */
 
 static void set_thermal_config(void)
  */
 
 static void set_thermal_config(void)


@@ -443,17 +443,17 @@ static void set_thermal_config(void)
        device_t sm_dev;
        struct fan_control cpu_fan_control, case_fan_control;
        const char *name = NULL;
        device_t sm_dev;
        struct fan_control cpu_fan_control, case_fan_control;
        const char *name = NULL;

-       
-               
+
+

        sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
        smbus_io_base = pci_read_config32(sm_dev, 0x10) & ~(0xf); // get BAR0-Address which holds the SMBUS_IO_BASE
        sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
        smbus_io_base = pci_read_config32(sm_dev, 0x10) & ~(0xf); // get BAR0-Address which holds the SMBUS_IO_BASE

-       
+

        if( (name = adt7475_detect()) == NULL ) {
                printk(BIOS_NOTICE, "Couldn't detect an ADT7473/75/76/90 part at %x:%x\n", smbus_io_base, adt7475_address);
                return;
        }
        printk(BIOS_DEBUG, "Found %s part at %x:%x\n", name, smbus_io_base, adt7475_address);
        if( (name = adt7475_detect()) == NULL ) {
                printk(BIOS_NOTICE, "Couldn't detect an ADT7473/75/76/90 part at %x:%x\n", smbus_io_base, adt7475_address);
                return;
        }
        printk(BIOS_DEBUG, "Found %s part at %x:%x\n", name, smbus_io_base, adt7475_address);

-       
+

        cpu_fan_control = cpu_fan_control_defaults;
        case_fan_control = case_fan_control_defaults;
 
        cpu_fan_control = cpu_fan_control_defaults;
        case_fan_control = case_fan_control_defaults;
 


@@ -463,7 +463,7 @@ static void set_thermal_config(void)
                // get all the options needed
                if( get_option(&byte, "cpu_fan_control") == 0 )
                        cpu_fan_control.enable = byte ? 1 : 0;
                // get all the options needed
                if( get_option(&byte, "cpu_fan_control") == 0 )
                        cpu_fan_control.enable = byte ? 1 : 0;

-                       
+

                get_option(&cpu_fan_control.polarity, "cpu_fan_polarity");
                get_option(&cpu_fan_control.t_min, "cpu_t_min");
                get_option(&cpu_fan_control.t_max, "cpu_t_max");
                get_option(&cpu_fan_control.polarity, "cpu_fan_polarity");
                get_option(&cpu_fan_control.t_min, "cpu_t_min");
                get_option(&cpu_fan_control.t_max, "cpu_t_max");


@@ -471,13 +471,13 @@ static void set_thermal_config(void)
                get_option(&cpu_fan_control.pwm_max, "cpu_dutycycle_max");
 
                if( get_option(&byte, "chassis_fan_control") == 0)
                get_option(&cpu_fan_control.pwm_max, "cpu_dutycycle_max");
 
                if( get_option(&byte, "chassis_fan_control") == 0)

-                       case_fan_control.enable = byte ? 1 : 0;         
-               get_option(&case_fan_control.polarity, "chassis_fan_polarity"); 
+                       case_fan_control.enable = byte ? 1 : 0;
+               get_option(&case_fan_control.polarity, "chassis_fan_polarity");

                get_option(&case_fan_control.t_min, "chassis_t_min");
                get_option(&case_fan_control.t_max, "chassis_t_max");
                get_option(&case_fan_control.pwm_min, "chassis_dutycycle_min");
                get_option(&case_fan_control.pwm_max, "chassis_dutycycle_max");
                get_option(&case_fan_control.t_min, "chassis_t_min");
                get_option(&case_fan_control.t_max, "chassis_t_max");
                get_option(&case_fan_control.pwm_min, "chassis_dutycycle_min");
                get_option(&case_fan_control.pwm_max, "chassis_dutycycle_max");

-       
+

        }
 
        printk(BIOS_DEBUG, "cpu_fan_control:%s", cpu_fan_control.enable ? "enable" : "disable");
        }
 
        printk(BIOS_DEBUG, "cpu_fan_control:%s", cpu_fan_control.enable ? "enable" : "disable");


@@ -485,50 +485,50 @@ static void set_thermal_config(void)
 
        printk(BIOS_DEBUG, " cpu_t_min:%s", TEMPERATURE_INFO(cpu_fan_control.t_min));
        cpu_fan_control.t_min = TEMPERATURE(cpu_fan_control.t_min, cpu_fan_control_defaults.t_min);
 
        printk(BIOS_DEBUG, " cpu_t_min:%s", TEMPERATURE_INFO(cpu_fan_control.t_min));
        cpu_fan_control.t_min = TEMPERATURE(cpu_fan_control.t_min, cpu_fan_control_defaults.t_min);

-       
+

        printk(BIOS_DEBUG, " cpu_t_max:%s", TEMPERATURE_INFO(cpu_fan_control.t_max));
        cpu_fan_control.t_max = TEMPERATURE(cpu_fan_control.t_max, cpu_fan_control_defaults.t_max);
        printk(BIOS_DEBUG, " cpu_t_max:%s", TEMPERATURE_INFO(cpu_fan_control.t_max));
        cpu_fan_control.t_max = TEMPERATURE(cpu_fan_control.t_max, cpu_fan_control_defaults.t_max);

-       
+

        printk(BIOS_DEBUG, " cpu_pwm_min:%s", DUTYCYCLE_INFO(cpu_fan_control.pwm_min));
        cpu_fan_control.pwm_min = DUTYCYCLE(cpu_fan_control.pwm_min, cpu_fan_control_defaults.pwm_min);
        printk(BIOS_DEBUG, " cpu_pwm_min:%s", DUTYCYCLE_INFO(cpu_fan_control.pwm_min));
        cpu_fan_control.pwm_min = DUTYCYCLE(cpu_fan_control.pwm_min, cpu_fan_control_defaults.pwm_min);

-       
+

        printk(BIOS_DEBUG, " cpu_pwm_max:%s", DUTYCYCLE_INFO(cpu_fan_control.pwm_max));
        cpu_fan_control.pwm_max = DUTYCYCLE(cpu_fan_control.pwm_max, cpu_fan_control_defaults.pwm_max);
        printk(BIOS_DEBUG, " cpu_pwm_max:%s", DUTYCYCLE_INFO(cpu_fan_control.pwm_max));
        cpu_fan_control.pwm_max = DUTYCYCLE(cpu_fan_control.pwm_max, cpu_fan_control_defaults.pwm_max);

-       
+

        cpu_fan_control.t_range = calc_trange(cpu_fan_control.t_min, cpu_fan_control.t_max);
        printk(BIOS_DEBUG, " cpu_t_range:0x%02x\n", cpu_fan_control.t_range);
        cpu_fan_control.t_range <<= 4;
        cpu_fan_control.t_range |= (4 << 0); // 35.3Hz
        cpu_fan_control.t_range = calc_trange(cpu_fan_control.t_min, cpu_fan_control.t_max);
        printk(BIOS_DEBUG, " cpu_t_range:0x%02x\n", cpu_fan_control.t_range);
        cpu_fan_control.t_range <<= 4;
        cpu_fan_control.t_range |= (4 << 0); // 35.3Hz

-       
+

        printk(BIOS_DEBUG, "chassis_fan_control:%s", case_fan_control.enable ? "enable" : "disable");
        printk(BIOS_DEBUG, " chassis_fan_polarity:%s", case_fan_control.polarity ? "low" : "high");
 
        printk(BIOS_DEBUG, " chassis_t_min:%s", TEMPERATURE_INFO(case_fan_control.t_min));
        case_fan_control.t_min = TEMPERATURE(case_fan_control.t_min, case_fan_control_defaults.t_min);
        printk(BIOS_DEBUG, "chassis_fan_control:%s", case_fan_control.enable ? "enable" : "disable");
        printk(BIOS_DEBUG, " chassis_fan_polarity:%s", case_fan_control.polarity ? "low" : "high");
 
        printk(BIOS_DEBUG, " chassis_t_min:%s", TEMPERATURE_INFO(case_fan_control.t_min));
        case_fan_control.t_min = TEMPERATURE(case_fan_control.t_min, case_fan_control_defaults.t_min);

-       
+

        printk(BIOS_DEBUG, " chassis_t_max:%s", TEMPERATURE_INFO(case_fan_control.t_max));
        case_fan_control.t_max = TEMPERATURE(case_fan_control.t_max, case_fan_control_defaults.t_max);
        printk(BIOS_DEBUG, " chassis_t_max:%s", TEMPERATURE_INFO(case_fan_control.t_max));
        case_fan_control.t_max = TEMPERATURE(case_fan_control.t_max, case_fan_control_defaults.t_max);

-       
+

        printk(BIOS_DEBUG, " chassis_pwm_min:%s", DUTYCYCLE_INFO(case_fan_control.pwm_min));
        case_fan_control.pwm_min = DUTYCYCLE(case_fan_control.pwm_min, case_fan_control_defaults.pwm_min);
        printk(BIOS_DEBUG, " chassis_pwm_min:%s", DUTYCYCLE_INFO(case_fan_control.pwm_min));
        case_fan_control.pwm_min = DUTYCYCLE(case_fan_control.pwm_min, case_fan_control_defaults.pwm_min);

-       
+

        printk(BIOS_DEBUG, " chassis_pwm_max:%s", DUTYCYCLE_INFO(case_fan_control.pwm_max));
        case_fan_control.pwm_max = DUTYCYCLE(case_fan_control.pwm_max, case_fan_control_defaults.pwm_max);
        printk(BIOS_DEBUG, " chassis_pwm_max:%s", DUTYCYCLE_INFO(case_fan_control.pwm_max));
        case_fan_control.pwm_max = DUTYCYCLE(case_fan_control.pwm_max, case_fan_control_defaults.pwm_max);

-       
+

        case_fan_control.t_range = calc_trange(case_fan_control.t_min, case_fan_control.t_max);
        printk(BIOS_DEBUG, " case_t_range:0x%02x\n", case_fan_control.t_range);
        case_fan_control.t_range <<= 4;
        case_fan_control.t_range |= (4 << 0); // 35.3Hz
        case_fan_control.t_range = calc_trange(case_fan_control.t_min, case_fan_control.t_max);
        printk(BIOS_DEBUG, " case_t_range:0x%02x\n", case_fan_control.t_range);
        case_fan_control.t_range <<= 4;
        case_fan_control.t_range |= (4 << 0); // 35.3Hz

-       
+

        cpu_pwm_conf = (((cpu_fan_control.polarity & 0x1) << 4) | 0x2); // bit 4 control polarity of PWMx output
        case_pwm_conf = (((case_fan_control.polarity & 0x1) << 4) | 0x2); // bit 4 control polarity of PWMx output
        cpu_pwm_conf = (((cpu_fan_control.polarity & 0x1) << 4) | 0x2); // bit 4 control polarity of PWMx output
        case_pwm_conf = (((case_fan_control.polarity & 0x1) << 4) | 0x2); // bit 4 control polarity of PWMx output

-       cpu_pwm_conf |= cpu_fan_control.enable ? (0 << 5) : (7 << 5);  // manual control 
+       cpu_pwm_conf |= cpu_fan_control.enable ? (0 << 5) : (7 << 5);  // manual control

        case_pwm_conf |= case_fan_control.enable ? (1 << 5) : (7 << 5); // local temp
        case_pwm_conf |= case_fan_control.enable ? (1 << 5) : (7 << 5); // local temp

-       
+

        /* set adt7475 */
 
        adt7475_write_byte(REG_CONFIG1, 0x04);  // clear register, bit 2 is read only
        /* set adt7475 */
 
        adt7475_write_byte(REG_CONFIG1, 0x04);  // clear register, bit 2 is read only

-       
+

        /* Config Register 6:  */
        adt7475_write_byte(REG_CONFIG6, 0x00);
        /* Config Register 7 */
        /* Config Register 6:  */
        adt7475_write_byte(REG_CONFIG6, 0x00);
        /* Config Register 7 */


@@ -536,14 +536,14 @@ static void set_thermal_config(void)
 
        /* Config Register 5: */
        /* set Offset 64 format, enable THERM on Remote 1& Local */
 
        /* Config Register 5: */
        /* set Offset 64 format, enable THERM on Remote 1& Local */

-       adt7475_write_byte(REG_CONFIG5, TWOS_COMPL ? 0x61 : 0x60); 
+       adt7475_write_byte(REG_CONFIG5, TWOS_COMPL ? 0x61 : 0x60);

        /* No offset for remote 1 */
        adt7475_write_byte(TEMP_OFFSET_REG(0), 0x00);
        /* No offset for local */
        adt7475_write_byte(TEMP_OFFSET_REG(1), 0x00);
        /* No offset for remote 2 */
        adt7475_write_byte(TEMP_OFFSET_REG(2), 0x00);
        /* No offset for remote 1 */
        adt7475_write_byte(TEMP_OFFSET_REG(0), 0x00);
        /* No offset for local */
        adt7475_write_byte(TEMP_OFFSET_REG(1), 0x00);
        /* No offset for remote 2 */
        adt7475_write_byte(TEMP_OFFSET_REG(2), 0x00);

-       
+

        /* remote 1 low temp limit */
        adt7475_write_byte(TEMP_MIN_REG(0), 0x00);
        /* remote 1 High temp limit    (90C) */
        /* remote 1 low temp limit */
        adt7475_write_byte(TEMP_MIN_REG(0), 0x00);
        /* remote 1 High temp limit    (90C) */


@@ -558,7 +558,7 @@ static void set_thermal_config(void)
        adt7475_write_byte(TEMP_THERM_REG(0), 0x9f);
        /* local therm temp limit    (95C) */
        adt7475_write_byte(TEMP_THERM_REG(1), 0x9f);
        adt7475_write_byte(TEMP_THERM_REG(0), 0x9f);
        /* local therm temp limit    (95C) */
        adt7475_write_byte(TEMP_THERM_REG(1), 0x9f);

-       
+

        /* PWM 1 configuration register    CPU fan controlled by CPU Thermal Diode */
        adt7475_write_byte(PWM_CONFIG_REG(0), cpu_pwm_conf);
        /* PWM 3 configuration register    Case fan controlled by ADTxxxx temp */
        /* PWM 1 configuration register    CPU fan controlled by CPU Thermal Diode */
        adt7475_write_byte(PWM_CONFIG_REG(0), cpu_pwm_conf);
        /* PWM 3 configuration register    Case fan controlled by ADTxxxx temp */


@@ -576,7 +576,7 @@ static void set_thermal_config(void)
        } else {
                adt7475_write_byte(PWM_REG(0), cpu_fan_control.pwm_max);
        }
        } else {
                adt7475_write_byte(PWM_REG(0), cpu_fan_control.pwm_max);
        }

-       
+

        if( case_fan_control.enable ) {
                /* PWM 2 minimum duty cycle     (37%) */
                adt7475_write_byte(PWM_MIN_REG(2), case_fan_control.pwm_min);
        if( case_fan_control.enable ) {
                /* PWM 2 minimum duty cycle     (37%) */
                adt7475_write_byte(PWM_MIN_REG(2), case_fan_control.pwm_min);


@@ -597,10 +597,10 @@ static void set_thermal_config(void)
        adt7475_write_byte(0x7d, 0x09);
        /* Interrupt Mask Register 2 - Mask SMB alert for Therm Conditions, Fan 3 fault, SmbAlert Fan for Therm Timer event */
        adt7475_write_byte(0x75, 0x2e);
        adt7475_write_byte(0x7d, 0x09);
        /* Interrupt Mask Register 2 - Mask SMB alert for Therm Conditions, Fan 3 fault, SmbAlert Fan for Therm Timer event */
        adt7475_write_byte(0x75, 0x2e);

-       
+

        /* Config Register 1 Set Start bit */
        adt7475_write_byte(0x40, 0x05);
        /* Config Register 1 Set Start bit */
        adt7475_write_byte(0x40, 0x05);

-       
+

        /* Read status register to clear any old errors */
        byte2 = adt7475_read_byte(0x42);
        byte = adt7475_read_byte(0x41);
        /* Read status register to clear any old errors */
        byte2 = adt7475_read_byte(0x42);
        byte = adt7475_read_byte(0x41);


@@ -611,20 +611,20 @@ static void set_thermal_config(void)
 }
 
  /**
 }
 
  /**

- * @brief 
+ * @brief

  *
  *

- * @param 
+ * @param

  */
 
 static void patch_mmio_nonposted( void )
 {
  */
 
 static void patch_mmio_nonposted( void )
 {

-       unsigned reg, index;            
+       unsigned reg, index;

        resource_t rbase, rend;
        u32 base, limit;
        struct resource *resource;
        device_t dev;
        device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18,1));
        resource_t rbase, rend;
        u32 base, limit;
        struct resource *resource;
        device_t dev;
        device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18,1));

-       
+

        printk(BIOS_DEBUG,"%s ...\n", __func__);
 
        dev = dev_find_slot(1, PCI_DEVFN(5,0));
        printk(BIOS_DEBUG,"%s ...\n", __func__);
 
        dev = dev_find_slot(1, PCI_DEVFN(5,0));


@@ -637,7 +637,7 @@ static void patch_mmio_nonposted( void )
                rbase = (resource->base >> 8) & ~(0xff);
                /* Get the limit (rounded up) */
                rend  = (resource_end(resource) >> 8) & ~(0xff);
                rbase = (resource->base >> 8) & ~(0xff);
                /* Get the limit (rounded up) */
                rend  = (resource_end(resource) >> 8) & ~(0xff);

-       
+

                printk(BIOS_DEBUG,"%s %x base = %0llx limit = %0llx\n", dev_path(dev), index, rbase, rend);
 
                for( reg = 0xb8; reg >= 0x80; reg -= 8 ) {
                printk(BIOS_DEBUG,"%s %x base = %0llx limit = %0llx\n", dev_path(dev), index, rbase, rend);
 
                for( reg = 0xb8; reg >= 0x80; reg -= 8 ) {


@@ -645,9 +645,9 @@ static void patch_mmio_nonposted( void )
                        limit = pci_read_config32(k8_f1,reg+4);
                        printk(BIOS_DEBUG," %02x[%08x] %02x[%08x]", reg, base, reg+4, limit);
                        if( ((base & ~(0xff)) == rbase) && ((limit & ~(0xff)) == rend) ) {
                        limit = pci_read_config32(k8_f1,reg+4);
                        printk(BIOS_DEBUG," %02x[%08x] %02x[%08x]", reg, base, reg+4, limit);
                        if( ((base & ~(0xff)) == rbase) && ((limit & ~(0xff)) == rend) ) {

-                               limit |= (1 << 7); 
+                               limit |= (1 << 7);

                                printk(BIOS_DEBUG, "\nPatching %s %x <- %08x", dev_path(k8_f1), reg, limit);
                                printk(BIOS_DEBUG, "\nPatching %s %x <- %08x", dev_path(k8_f1), reg, limit);

-                               pci_write_config32(k8_f1, reg+4, limit); 
+                               pci_write_config32(k8_f1, reg+4, limit);

                                break;
                        }
                }
                                break;
                        }
                }


@@ -656,22 +656,22 @@ static void patch_mmio_nonposted( void )
 }
 
  /**
 }
 
  /**

- * @brief 
+ * @brief

  *
  *

- * @param 
+ * @param

  */
  */

- 
+

 static void wait_pepp( void ) {
 
        int boot_delay = 0;
 static void wait_pepp( void ) {
 
        int boot_delay = 0;

-       
+

        if( get_option(&boot_delay, "boot_delay") < 0)
                boot_delay = 5;
        if( get_option(&boot_delay, "boot_delay") < 0)
                boot_delay = 5;

-               
+

        printk(BIOS_DEBUG, "boot_delay = %d sec\n", boot_delay);
        if ( boot_delay > 0 ) {
                init_timer();
        printk(BIOS_DEBUG, "boot_delay = %d sec\n", boot_delay);
        if ( boot_delay > 0 ) {
                init_timer();

-               // wait for PEPP-Board 
+               // wait for PEPP-Board

                printk(BIOS_INFO, "Give PEPP-Board %d sec(s) time to coming up ", boot_delay);
                while ( boot_delay ) {
                        lapic_write(LAPIC_TMICT, 0xffffffff);
                printk(BIOS_INFO, "Give PEPP-Board %d sec(s) time to coming up ", boot_delay);
                while ( boot_delay ) {
                        lapic_write(LAPIC_TMICT, 0xffffffff);


@@ -684,9 +684,9 @@ static void wait_pepp( void ) {
 }
 
  /**
 }
 
  /**

- * @brief 
+ * @brief

  *
  *

- * @param 
+ * @param

  */
 
 struct {
  */
 
 struct {


@@ -700,13 +700,13 @@ struct {
        {0, PCI_DEVFN(5,0)},{0, PCI_DEVFN(5,2)},
        {255,0},
 };
        {0, PCI_DEVFN(5,0)},{0, PCI_DEVFN(5,2)},
        {255,0},
 };

- 
+

 
 static void update_subsystemid( device_t dev ) {
 
        int i;
        struct mainboard_config *mb = dev->chip_info;
 
 static void update_subsystemid( device_t dev ) {
 
        int i;
        struct mainboard_config *mb = dev->chip_info;

-       
+

        dev->subsystem_vendor = 0x110a;
        if( mb->plx_present ){
                dev->subsystem_device = 0x4076; // U1P1 = 0x4076, U1P0 = 0x4077
        dev->subsystem_vendor = 0x110a;
        if( mb->plx_present ){
                dev->subsystem_device = 0x4076; // U1P1 = 0x4076, U1P0 = 0x4077


@@ -725,9 +725,9 @@ static void update_subsystemid( device_t dev ) {
 }
 
  /**
 }
 
  /**

- * @brief 
+ * @brief

  *
  *

- * @param 
+ * @param

  */
 
 static void detect_hw_variant( device_t dev ) {
  */
 
 static void detect_hw_variant( device_t dev ) {


@@ -736,7 +736,7 @@ static void detect_hw_variant( device_t dev ) {
        struct southbridge_amd_rs690_config *cfg;
        u32 lc_state, id = 0;
        struct mainboard_config *mb = dev->chip_info;
        struct southbridge_amd_rs690_config *cfg;
        u32 lc_state, id = 0;
        struct mainboard_config *mb = dev->chip_info;

-       
+

        printk(BIOS_INFO, "Scan for PLX device ...\n");
        nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
        if (!nb_dev) {
        printk(BIOS_INFO, "Scan for PLX device ...\n");
        nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
        if (!nb_dev) {


@@ -769,19 +769,19 @@ static void detect_hw_variant( device_t dev ) {
                struct device dummy;
                u32 pci_primary_bus, buses;
                u16 secondary, subordinate;
                struct device dummy;
                u32 pci_primary_bus, buses;
                u16 secondary, subordinate;

-               
-               printk(BIOS_DEBUG, "Scan for PLX bridge behind %s[%x]\n", dev_path(dev2), pci_read_config32(dev2, PCI_VENDOR_ID));              
+
+               printk(BIOS_DEBUG, "Scan for PLX bridge behind %s[%x]\n", dev_path(dev2), pci_read_config32(dev2, PCI_VENDOR_ID));

                // save the existing primary/secondary/subordinate bus number configuration.
                secondary = dev2->bus->secondary;
                subordinate = dev2->bus->subordinate;
                buses = pci_primary_bus = pci_read_config32(dev2, PCI_PRIMARY_BUS);
 
                // Configure the bus numbers for this bridge
                // save the existing primary/secondary/subordinate bus number configuration.
                secondary = dev2->bus->secondary;
                subordinate = dev2->bus->subordinate;
                buses = pci_primary_bus = pci_read_config32(dev2, PCI_PRIMARY_BUS);
 
                // Configure the bus numbers for this bridge

-               // bus number 1 is for internal gfx device, so we start with busnumber 2 
+               // bus number 1 is for internal gfx device, so we start with busnumber 2

 
                buses &= 0xff000000;
                buses |= ((2 << 8) | (0xff << 16));
 
                buses &= 0xff000000;
                buses |= ((2 << 8) | (0xff << 16));

-               // setup the buses in device 2          
+               // setup the buses in device 2

                pci_write_config32(dev2,PCI_PRIMARY_BUS, buses);
 
                // fake a device descriptor for a device behind device 2
                pci_write_config32(dev2,PCI_PRIMARY_BUS, buses);
 
                // fake a device descriptor for a device behind device 2


@@ -795,7 +795,7 @@ static void detect_hw_variant( device_t dev ) {
                /* Have we found something?
                 * Some broken boards return 0 if a slot is empty, but
                 * the expected answer is 0xffffffff
                /* Have we found something?
                 * Some broken boards return 0 if a slot is empty, but
                 * the expected answer is 0xffffffff

-                */     
+                */

                if ((id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000)) {
                        printk(BIOS_DEBUG, "%s, bad id 0x%x\n", dev_path(&dummy), id);
                } else {
                if ((id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000)) {
                        printk(BIOS_DEBUG, "%s, bad id 0x%x\n", dev_path(&dummy), id);
                } else {


@@ -810,8 +810,8 @@ static void detect_hw_variant( device_t dev ) {
        default:
                break;
        }
        default:
                break;
        }

-       
-       mb->plx_present = 0;    
+
+       mb->plx_present = 0;

        if( id == PLX_VIDDID ){
                printk(BIOS_INFO, "found PLX device\n");
                mb->plx_present = 1;
        if( id == PLX_VIDDID ){
                printk(BIOS_INFO, "found PLX device\n");
                mb->plx_present = 1;


@@ -822,7 +822,7 @@ static void detect_hw_variant( device_t dev ) {
                        cfg->gfx_link_width = 4;
                }
                return;
                        cfg->gfx_link_width = 4;
                }
                return;

-       } 
+       }

 }
 
 static void smm_lock( void )
 }
 
 static void smm_lock( void )


@@ -841,16 +841,16 @@ static void smm_lock( void )
  *
  * @param the root device
  */
  *
  * @param the root device
  */

- 
+

 static void init(device_t dev)
 {
 #if CONFIG_PCI_OPTION_ROM_RUN_YABEL == 0
        INT15_function_extensions int15_func;
 #endif
 static void init(device_t dev)
 {
 #if CONFIG_PCI_OPTION_ROM_RUN_YABEL == 0
        INT15_function_extensions int15_func;
 #endif

-       
+

        printk(BIOS_DEBUG, "%s %s[%x/%x] %s\n",
                dev->chip_ops->name, dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__);
        printk(BIOS_DEBUG, "%s %s[%x/%x] %s\n",
                dev->chip_ops->name, dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__);

-       
+

 #if CONFIG_PCI_OPTION_ROM_RUN_YABEL == 0
        if(     get_option(&int15_func.regs.func00_LCD_panel_id, "lcd_panel_id") < 0 )
                int15_func.regs.func00_LCD_panel_id = PANEL_TABLE_ID_NO;
 #if CONFIG_PCI_OPTION_ROM_RUN_YABEL == 0
        if(     get_option(&int15_func.regs.func00_LCD_panel_id, "lcd_panel_id") < 0 )
                int15_func.regs.func00_LCD_panel_id = PANEL_TABLE_ID_NO;


@@ -870,7 +870,7 @@ static void init(device_t dev)
 *************************************************/
 static void enable_dev(device_t dev)
 {
 *************************************************/
 static void enable_dev(device_t dev)
 {

-       
+

        printk(BIOS_INFO, "%s %s[%x/%x] %s\n",
                dev->chip_ops->name, dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__);
 #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
        printk(BIOS_INFO, "%s %s[%x/%x] %s\n",
                dev->chip_ops->name, dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__);
 #if CONFIG_PCI_OPTION_ROM_RUN_YABEL


@@ -880,19 +880,19 @@ static void enable_dev(device_t dev)
 
        detect_hw_variant(dev);
        update_subsystemid(dev);
 
        detect_hw_variant(dev);
        update_subsystemid(dev);

-       
+

 #if (CONFIG_GFXUMA == 1)
        {
        msr_t msr, msr2;
 #if (CONFIG_GFXUMA == 1)
        {
        msr_t msr, msr2;

-       
+

        /* TOP_MEM: the top of DRAM below 4G */
        msr = rdmsr(TOP_MEM);
        printk(BIOS_DEBUG, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
                    __func__, msr.lo, msr.hi);
        /* TOP_MEM: the top of DRAM below 4G */
        msr = rdmsr(TOP_MEM);
        printk(BIOS_DEBUG, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
                    __func__, msr.lo, msr.hi);

-       
+

        /* TOP_MEM2: the top of DRAM above 4G */
        msr2 = rdmsr(TOP_MEM2);
        /* TOP_MEM2: the top of DRAM above 4G */
        msr2 = rdmsr(TOP_MEM2);

-       
+

        printk(BIOS_DEBUG, "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
                    __func__, msr2.lo, msr2.hi);
 
        printk(BIOS_DEBUG, "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
                    __func__, msr2.lo, msr2.hi);
 


@@ -915,7 +915,7 @@ static void enable_dev(device_t dev)
        }
 
        uma_memory_base = msr.lo - uma_memory_size;     /* TOP_MEM1 */
        }
 
        uma_memory_base = msr.lo - uma_memory_size;     /* TOP_MEM1 */

-       
+

        printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
                    __func__, uma_memory_size, uma_memory_base);
 
        printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
                    __func__, uma_memory_size, uma_memory_base);
 


@@ -927,20 +927,20 @@ static void enable_dev(device_t dev)
 #endif
 
        wait_pepp();
 #endif
 
        wait_pepp();

-       dev->ops->init = init;  // rest of mainboard init later   
+       dev->ops->init = init;  // rest of mainboard init later

 }
 
  /**
 }
 
  /**

- * @brief 
+ * @brief

  *
  *

- * @param 
+ * @param

  */
 
 int add_mainboard_resources(struct lb_memory *mem)
 {
        device_t dev;
        struct resource *res;
  */
 
 int add_mainboard_resources(struct lb_memory *mem)
 {
        device_t dev;
        struct resource *res;

-       
+

        dev = dev_find_slot(0, PCI_DEVFN(0,0));
        res = probe_resource(dev, 0x1C);
        if( res ) {
        dev = dev_find_slot(0, PCI_DEVFN(0,0));
        res = probe_resource(dev, 0x1C);
        if( res ) {

diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c
index 9e4a6db028696345c9f59aaa5bcc25467d4e72e8..ba2c1e4c1c3d4ae39ac031a50676b22b7aced494 100644 (file)
--- a/src/mainboard/siemens/sitemp_g1p1/mptable.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c
@@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v)
 {
        struct mp_config_table *mc;
        int isa_bus;
 {
        struct mp_config_table *mc;
        int isa_bus;

-       
+

         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
        mptable_init(mc, LAPIC_ADDR);
        smp_write_processors(mc);
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
        mptable_init(mc, LAPIC_ADDR);
        smp_write_processors(mc);

diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c
index 09aa1d7f459b4c77e3ea7b7381342cafe40650b0..b570d4581db1477cfdeeea875b8c594bcc172253 100644 (file)
--- a/src/mainboard/siemens/sitemp_g1p1/romstage.c
+++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c
@@ -18,7 +18,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

- 
+

 #define RC0 (6<<8)
 #define RC1 (7<<8)
 
 #define RC0 (6<<8)
 #define RC1 (7<<8)
 


@@ -177,7 +177,7 @@ static inline void check_cmos( void ) {
                        outb(0x0a,0x72);
                        i = inb(0x73);
                        i &= ~(1 << 4);
                        outb(0x0a,0x72);
                        i = inb(0x73);
                        i &= ~(1 << 4);

-                       outb(i,0x73);                                   
+                       outb(i,0x73);

 
                        for (i = 14; i < 128; i++) {
 #if DUMP_CMOS_RAM
 
                        for (i = 14; i < 128; i++) {
 #if DUMP_CMOS_RAM


@@ -198,7 +198,7 @@ static inline void check_cmos( void ) {
                        /* Now reboot to run with default cmos. */
                        outb(0x06, 0xcf9);
                        for (;;) asm("hlt"); /* Wait for reset! */
                        /* Now reboot to run with default cmos. */
                        outb(0x06, 0xcf9);
                        for (;;) asm("hlt"); /* Wait for reset! */

-               } 
+               }

        }
 
        // update altcentury
        }
 
        // update altcentury


@@ -221,7 +221,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        msr_t msr;
        struct cpuid_result cpuid1;
        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
        msr_t msr;
        struct cpuid_result cpuid1;
        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);

-                       
+

        if (!cpu_init_detectedx && boot_cpu()) {
                /* Nothing special needs to be done to find bus 0 */
                /* Allow the HT devices to be found */
        if (!cpu_init_detectedx && boot_cpu()) {
                /* Nothing special needs to be done to find bus 0 */
                /* Allow the HT devices to be found */


@@ -237,19 +237,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        enable_rs690_dev8(); // enable CFG access to Dev8, which is the SB P2P Bridge
        sb600_lpc_init();
 
        enable_rs690_dev8(); // enable CFG access to Dev8, which is the SB P2P Bridge
        sb600_lpc_init();

-#if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 0)     
-       check_cmos();  // rebooting in case of corrupted cmos !!!!!     
-#endif 
+#if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 0)
+       check_cmos();  // rebooting in case of corrupted cmos !!!!!
+#endif

        /* it8712f_enable_serial does not use its 1st parameter. */
        it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
        /* it8712f_enable_serial does not use its 1st parameter. */
        it8712f_enable_serial(0, CONFIG_TTYS0_BASE);

-       it8712f_kill_watchdog(); 
+       it8712f_kill_watchdog();

 
        console_init();
 #if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 1)
 
        console_init();
 #if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 1)

-       check_cmos();  // rebooting in case of corrupted cmos !!!!!             
+       check_cmos();  // rebooting in case of corrupted cmos !!!!!

 #endif
        post_code(0x03);
 #endif
        post_code(0x03);

-       
+

        /* Halt if there was a built in self test failure */
        report_bist_failure(bist);
        __DEBUG__("bsp_apicid=0x%x\n", bsp_apicid);
        /* Halt if there was a built in self test failure */
        report_bist_failure(bist);
        __DEBUG__("bsp_apicid=0x%x\n", bsp_apicid);


@@ -270,9 +270,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* run _early_setup before soft-reset. */
        rs690_early_setup();
        sb600_early_setup();
        /* run _early_setup before soft-reset. */
        rs690_early_setup();
        sb600_early_setup();

-       
+

        post_code(0x04);
        post_code(0x04);

-       
+

        /* Check to see if processor is capable of changing FIDVID  */
        /* otherwise it will throw a GP# when reading FIDVID_STATUS */
        cpuid1 = cpuid(0x80000007);
        /* Check to see if processor is capable of changing FIDVID  */
        /* otherwise it will throw a GP# when reading FIDVID_STATUS */
        cpuid1 = cpuid(0x80000007);


@@ -293,16 +293,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        } else {
                __DEBUG__("Changing FIDVID not supported\n");
        }
        } else {
                __DEBUG__("Changing FIDVID not supported\n");
        }

-       
+

        post_code(0x05);
        post_code(0x05);

-       
+

        needs_reset = optimize_link_coherent_ht();
        needs_reset |= optimize_link_incoherent_ht(sysinfo);
        rs690_htinit();
        __DEBUG__("needs_reset=0x%x\n", needs_reset);
        needs_reset = optimize_link_coherent_ht();
        needs_reset |= optimize_link_incoherent_ht(sysinfo);
        rs690_htinit();
        __DEBUG__("needs_reset=0x%x\n", needs_reset);

-       
+

        post_code(0x06);
        post_code(0x06);

-       
+

        if (needs_reset) {
                __INFO__("ht reset -\n");
                soft_reset();
        if (needs_reset) {
                __INFO__("ht reset -\n");
                soft_reset();


@@ -314,19 +314,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        __DEBUG__("sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
                     sysinfo->nodes, sysinfo->ctrl, spd_addr);
        fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
        __DEBUG__("sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
                     sysinfo->nodes, sysinfo->ctrl, spd_addr);
        fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);

-       
+

        post_code(0x07);
        post_code(0x07);

-       
+

        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);

-       
+

        post_code(0x08);
        post_code(0x08);

-       
+

        rs690_before_pci_init(); // does nothing
        sb600_before_pci_init();
        rs690_before_pci_init(); // does nothing
        sb600_before_pci_init();

-       
-#if CONFIG_USE_OPTION_TABLE    
+
+#if CONFIG_USE_OPTION_TABLE

        if( read_option(cmos_defaults_loaded, 0) )
        if( read_option(cmos_defaults_loaded, 0) )

-               __WARNING__("WARNING: CMOS DEFAULTS LOADED. PLEASE CHECK CMOS OPTION \"cmos_default_loaded\" !\n"); 
+               __WARNING__("WARNING: CMOS DEFAULTS LOADED. PLEASE CHECK CMOS OPTION \"cmos_default_loaded\" !\n");

 #endif
 
        post_cache_as_ram();
 #endif
 
        post_cache_as_ram();

diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.h b/src/mainboard/supermicro/h8qgi/BiosCallOuts.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/supermicro/h8qgi/OptionsIds.h b/src/mainboard/supermicro/h8qgi/OptionsIds.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.h b/src/mainboard/supermicro/h8qgi/agesawrapper.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/supermicro/h8qgi/chip.h b/src/mainboard/supermicro/h8qgi/chip.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/supermicro/h8qgi/dimmSpd.c b/src/mainboard/supermicro/h8qgi/dimmSpd.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/supermicro/h8qgi/fadt.c b/src/mainboard/supermicro/h8qgi/fadt.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/supermicro/h8qgi/irq_tables.c b/src/mainboard/supermicro/h8qgi/irq_tables.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/supermicro/h8qgi/platform_oem.c b/src/mainboard/supermicro/h8qgi/platform_oem.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/supermicro/h8qgi/platform_oem.h b/src/mainboard/supermicro/h8qgi/platform_oem.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c
index d80e2d59350030653998574319b5508b2fad0111..12fc4469ab22301476e6d46dde2198d9034fef7f 100644 (file)
--- a/src/mainboard/wyse/s50/romstage.c
+++ b/src/mainboard/wyse/s50/romstage.c
@@ -58,7 +58,7 @@ void main(unsigned long bist)
        SystemPreInit();
 
        cs5536_early_setup();
        SystemPreInit();
 
        cs5536_early_setup();

-       
+

        /* cs5536_disable_internal_uart  disable them. Set them up now... */
        cs5536_setup_onchipuart(1);
 
        /* cs5536_disable_internal_uart  disable them. Set them up now... */
        cs5536_setup_onchipuart(1);
 

diff --git a/src/northbridge/amd/agesa/family10/amdfam10.h b/src/northbridge/amd/agesa/family10/amdfam10.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/northbridge/amd/agesa/family10/bootblock.c b/src/northbridge/amd/agesa/family10/bootblock.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/northbridge/amd/agesa/family10/chip.h b/src/northbridge/amd/agesa/family10/chip.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/northbridge/amd/agesa/family10/northbridge.h b/src/northbridge/amd/agesa/family10/northbridge.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/northbridge/amd/agesa/family10/reset_test.h b/src/northbridge/amd/agesa/family10/reset_test.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/northbridge/amd/agesa/family10/root_complex/chip.h b/src/northbridge/amd/agesa/family10/root_complex/chip.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/northbridge/amd/agesa/family12/bootblock.c b/src/northbridge/amd/agesa/family12/bootblock.c
old mode 100755 (executable)
new mode 100644 (file)
index eead31d..f6ae8be
--- a/src/northbridge/amd/agesa/family12/bootblock.c
+++ b/src/northbridge/amd/agesa/family12/bootblock.c
@@ -20,7 +20,7 @@
  * ***************************************************************************
  *
  */
  * ***************************************************************************
  *
  */

- 
+

 #include <arch/io.h>
 #include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <arch/romcc_io.h>
 #include <device/pci_def.h>

diff --git a/src/northbridge/amd/agesa/family12/chip.h b/src/northbridge/amd/agesa/family12/chip.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
old mode 100755 (executable)
new mode 100644 (file)
index 55109b5..2c039d2
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -311,7 +311,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
         }
 
 #if 0
         }
 
 #if 0

-        // We need to double check if there is speical set on base reg and limit reg 
+        // We need to double check if there is speical set on base reg and limit reg

             // are not continous instead of hole, it will find out it's hole_startk
         if(mem_hole.node_id==-1) {
             resource_t limitk_pri = 0;
             // are not continous instead of hole, it will find out it's hole_startk
         if(mem_hole.node_id==-1) {
             resource_t limitk_pri = 0;


@@ -332,7 +332,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
             }
         }
 #endif
             }
         }
 #endif

-        
+

         return mem_hole;
 }
 #endif
         return mem_hole;
 }
 #endif


@@ -471,7 +471,7 @@ static void set_resources(device_t dev)
     struct resource *res;
 
     printk(BIOS_DEBUG, "\nFam12h - northbridge.c - set_resources - Start.\n");
     struct resource *res;
 
     printk(BIOS_DEBUG, "\nFam12h - northbridge.c - set_resources - Start.\n");

- 
+

     /* Find the nodeid */
     nodeid = amdfam12_nodeid(dev);
 
     /* Find the nodeid */
     nodeid = amdfam12_nodeid(dev);
 


@@ -782,7 +782,7 @@ static void domain_enable_resources(device_t dev)
   /* Must be called after PCI enumeration and resource allocation */
 //  printk(BIOS_DEBUG, "\nFam12h - northbridge.c - domain_enable_resources - agesawrapper_amdinitmid - Start.\n");
   printk(BIOS_DEBUG, "\nFam12h - northbridge.c - domain_enable_resources - Start.\n");
   /* Must be called after PCI enumeration and resource allocation */
 //  printk(BIOS_DEBUG, "\nFam12h - northbridge.c - domain_enable_resources - agesawrapper_amdinitmid - Start.\n");
   printk(BIOS_DEBUG, "\nFam12h - northbridge.c - domain_enable_resources - Start.\n");

-//  val = agesawrapper_amdinitmid (); 
+//  val = agesawrapper_amdinitmid ();

 //  if(val) {
 //    printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val);
 //  }
 //  if(val) {
 //    printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val);
 //  }


@@ -819,7 +819,7 @@ static void cpu_bus_set_resources(device_t dev)
     pci_dev_set_resources(dev);
     printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_set_resources - End.\n");
 }
     pci_dev_set_resources(dev);
     printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_set_resources - End.\n");
 }

- 
+

 static void cpu_bus_init(device_t dev)
 {
     u32 val;
 static void cpu_bus_init(device_t dev)
 {
     u32 val;


@@ -830,20 +830,20 @@ static void cpu_bus_init(device_t dev)
 #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
     /* Must be called after PCI enumeration and resource allocation */
     printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_init - sb_After_Pci_Init - Start.\n");
 #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
     /* Must be called after PCI enumeration and resource allocation */
     printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_init - sb_After_Pci_Init - Start.\n");

-    sb_After_Pci_Init (); 
+    sb_After_Pci_Init ();

     printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_init - sb_After_Pci_Init - End.\n");
 #endif // #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
 
 #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
     /* Must be called after PCI enumeration and resource allocation */
     printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_init - sb_Mid_Post_Init - Start.\n");
     printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_init - sb_After_Pci_Init - End.\n");
 #endif // #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
 
 #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
     /* Must be called after PCI enumeration and resource allocation */
     printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_init - sb_Mid_Post_Init - Start.\n");

-    sb_Mid_Post_Init (); 
+    sb_Mid_Post_Init ();

     printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_init - sb_Mid_Post_Init - End.\n");
 #endif // #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
 
     /* Must be called after PCI enumeration and resource allocation */
     printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_init - agesawrapper_amdinitmid - Start.\n");
     printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_init - sb_Mid_Post_Init - End.\n");
 #endif // #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
 
     /* Must be called after PCI enumeration and resource allocation */
     printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_init - agesawrapper_amdinitmid - Start.\n");

-    val = agesawrapper_amdinitmid (); 
+    val = agesawrapper_amdinitmid ();

     if(val) {
         printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val);
     }
     if(val) {
         printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val);
     }

diff --git a/src/northbridge/amd/agesa/family12/northbridge.h b/src/northbridge/amd/agesa/family12/northbridge.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/northbridge/amd/agesa/family12/root_complex/chip.h b/src/northbridge/amd/agesa/family12/root_complex/chip.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/northbridge/amd/agesa/family14/bootblock.c b/src/northbridge/amd/agesa/family14/bootblock.c
index eead31d26b71efdeb2c810aac2a502f4cf7874c3..f6ae8be8b947d4a805af22e39733af8d1a6cc999 100644 (file)
--- a/src/northbridge/amd/agesa/family14/bootblock.c
+++ b/src/northbridge/amd/agesa/family14/bootblock.c
@@ -20,7 +20,7 @@
  * ***************************************************************************
  *
  */
  * ***************************************************************************
  *
  */

- 
+

 #include <arch/io.h>
 #include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <arch/romcc_io.h>
 #include <device/pci_def.h>

diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index b410bb96d6fcaeec74619048070e3cb16e86c359..99518065defbabd35801c78a39f765c97c644f98 100644 (file)
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -958,7 +958,7 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
 //           byte 1 - fid_max
 //           byte 2 - nb_cof_vid_update
 //           byte 3 - apic id
 //           byte 1 - fid_max
 //           byte 2 - nb_cof_vid_update
 //           byte 3 - apic id

-   
+

 #define LAPIC_MSG_REG 0x380
 #define F10_APSTATE_STARTED 0x13  // start of AP execution
 #define F10_APSTATE_STOPPED 0x14  // allow AP to stop
 #define LAPIC_MSG_REG 0x380
 #define F10_APSTATE_STARTED 0x13  // start of AP execution
 #define F10_APSTATE_STOPPED 0x14  // allow AP to stop

diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h
index 566e1fbbb0c17ea56c493f39ba4ac2d1903d1a4a..ccee1fdff03c7e468d219af9a82f3e64fb0aa854 100644 (file)
--- a/src/northbridge/amd/amdht/AsPsDefs.h
+++ b/src/northbridge/amd/amdht/AsPsDefs.h
@@ -292,8 +292,8 @@
 #define CUR_PSTATE_MSR 0xc0010063
 #define TSC_FREQ_SEL_SHIFT 24
 
 #define CUR_PSTATE_MSR 0xc0010063
 #define TSC_FREQ_SEL_SHIFT 24
 

-#define TSC_FREQ_SEL_MASK (1 << TSC_FREQ_SEL_SHIFT) 
- 
+#define TSC_FREQ_SEL_MASK (1 << TSC_FREQ_SEL_SHIFT)
+

 #define  WAIT_PSTATE_TIMEOUT 80000000  /* 0.1 s , unit : 1.25 ns */
 
 #endif
 #define  WAIT_PSTATE_TIMEOUT 80000000  /* 0.1 s , unit : 1.25 ns */
 
 #endif

diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 8b50eed79030b5431f196d9d436cfc9205175bc8..a262686f871609d5643c479c92775f1730a33e90 100644 (file)
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -673,7 +673,7 @@ static void setup_uniprocessor(void)
 }
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 }
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 2

-static int optimize_connection_group(const u8 *opt_conn, int num) 
+static int optimize_connection_group(const u8 *opt_conn, int num)

 {
        int needs_reset = 0;
        int i;
 {
        int needs_reset = 0;
        int i;


@@ -1709,7 +1709,7 @@ static int apply_cpu_errata_fixes(unsigned nodes)
                }
 #endif
 
                }
 #endif
 

-               
+

 #if CONFIG_K8_REV_F_SUPPORT == 0
                /* I can't touch this msr on early buggy cpus, and cannot apply either 169 or 131 */
                if (!is_cpu_pre_b3())
 #if CONFIG_K8_REV_F_SUPPORT == 0
                /* I can't touch this msr on early buggy cpus, and cannot apply either 169 or 131 */
                if (!is_cpu_pre_b3())

diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
index 4533818ef8484bfce7505b7b6b2b925dcf9c638b..7ba2b90406b8462b32030f2842fbadf29d4eaf9b 100644 (file)
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -48,7 +48,7 @@ static void mcf3_read_resources(device_t dev)
        }
 
        iommu = 1;
        }
 
        iommu = 1;

-       if( get_option(&iommu, "iommu") < 0 ) 
+       if( get_option(&iommu, "iommu") < 0 )

        {
                iommu = CONFIG_IOMMU;
        }
        {
                iommu = CONFIG_IOMMU;
        }

diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index a62036621f0094c3a80eaab57c5510b10ea55821..319293b7ed61e9f138efeb6e261d57040e8ab19e 100644 (file)
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -1815,7 +1815,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
 #endif
 #endif
        ];
 #endif
 #endif
        ];

-       
+

        if (bios_cycle_time > min_cycle_time) {
                min_cycle_time = bios_cycle_time;
        }
        if (bios_cycle_time > min_cycle_time) {
                min_cycle_time = bios_cycle_time;
        }

diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h
index d2bef3868ef1878eeb99d80e2dcf4a63cb0dd383..ae1537f24ca2bbf48dde42b0b9b2fcefc6d4d2d3 100644 (file)
--- a/src/northbridge/amd/amdmct/amddefs.h
+++ b/src/northbridge/amd/amdmct/amddefs.h
@@ -140,7 +140,7 @@
 #define BU_CFG2                0xC001102A
 
 /*
 #define BU_CFG2                0xC001102A
 
 /*

- * Processor package types 
+ * Processor package types

  */
 #define AMD_PKGTYPE_FrX_1207 0
 #define AMD_PKGTYPE_AM3_2r2 1
  */
 #define AMD_PKGTYPE_FrX_1207 0
 #define AMD_PKGTYPE_AM3_2r2 1

diff --git a/src/northbridge/intel/i82830/smihandler.c b/src/northbridge/intel/i82830/smihandler.c
index f7c6b5af25dfe49208ff94a9a59205d52cb86df7..37b138a6da5ee787e9330ad8ea38e1f741bfa28f 100644 (file)
--- a/src/northbridge/intel/i82830/smihandler.c
+++ b/src/northbridge/intel/i82830/smihandler.c
@@ -196,7 +196,7 @@ static void mbi_call(u8 subf, banner_id_t *banner_id)
                        }
 
                        mbi_header = (mbi_header_t *)&mbi[i];
                        }
 
                        mbi_header = (mbi_header_t *)&mbi[i];

-                       len = ALIGN((mbi_header->size * 16) + sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16); 
+                       len = ALIGN((mbi_header->size * 16) + sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16);

 
                        if (obj_header->objnum == count) {
 #ifdef DEBUG_SMI_I82830
 
                        if (obj_header->objnum == count) {
 #ifdef DEBUG_SMI_I82830

diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index 85ba1be4f01a69cd82842df3650f4fa6cb398c4b..23c3cb14d16557db0206aa709c260412219fc8a3 100644 (file)
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -831,12 +831,12 @@ static void spd_set_dram_throttle_control(void)
         */
        dtc_reg |= (3 << 28);
 
         */
        dtc_reg |= (3 << 28);
 

-       /* Read Counter Based Power Throttle Control (RCTC): 
+       /* Read Counter Based Power Throttle Control (RCTC):

         *   0 = 85%
         */
        dtc_reg |= (0 << 24);
 
         *   0 = 85%
         */
        dtc_reg |= (0 << 24);
 

-       /* Write Counter Based Power Throttle Control (WCTC): 
+       /* Write Counter Based Power Throttle Control (WCTC):

         *   0 = 85%
         */
        dtc_reg |= (0 << 20);
         *   0 = 85%
         */
        dtc_reg |= (0 << 20);


@@ -879,7 +879,7 @@ static void spd_update(u8 reg, u32 new_value)
        u32 value2 = pci_read_config32(NORTHBRIDGE_MMC, reg);
        PRINTK_DEBUG("update reg %02x, old: %08x, new: %08x, read back: %08x\n", reg, value1, new_value, value2);
 #endif
        u32 value2 = pci_read_config32(NORTHBRIDGE_MMC, reg);
        PRINTK_DEBUG("update reg %02x, old: %08x, new: %08x, read back: %08x\n", reg, value1, new_value, value2);
 #endif

-}      
+}

 
 /* if ram still doesn't work do this function */
 static void spd_set_undocumented_registers(void)
 
 /* if ram still doesn't work do this function */
 static void spd_set_undocumented_registers(void)


@@ -967,7 +967,7 @@ static void sdram_set_spd_registers(void)
        if (dimm_mask == 0) {
                print_debug("No usable memory for this controller\n");
        } else {
        if (dimm_mask == 0) {
                print_debug("No usable memory for this controller\n");
        } else {

-               PRINTK_DEBUG("DIMM MASK: %02x\n", dimm_mask);   
+               PRINTK_DEBUG("DIMM MASK: %02x\n", dimm_mask);

 
                spd_set_row_attributes(dimm_mask);
                spd_set_dram_controller_mode(dimm_mask);
 
                spd_set_row_attributes(dimm_mask);
                spd_set_dram_controller_mode(dimm_mask);

diff --git a/src/northbridge/via/cx700/northbridge.h b/src/northbridge/via/cx700/northbridge.h
index 4ae9ce593777f2ccde2b0ffebc816665263a48c0..c651bfe5f2aee395c5a62bb261ef9f15de42c96a 100644 (file)
--- a/src/northbridge/via/cx700/northbridge.h
+++ b/src/northbridge/via/cx700/northbridge.h
@@ -21,6 +21,6 @@
 #define NORTHBRIDGE_VIA_CX700_H
 
 extern unsigned int cx700_scan_root_bus(device_t root, unsigned int max);
 #define NORTHBRIDGE_VIA_CX700_H
 
 extern unsigned int cx700_scan_root_bus(device_t root, unsigned int max);

-extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, 
+extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx,

                u32 esi, u32 edi) __attribute__((regparm(0)));
 #endif                         /* NORTHBRIDGE_VIA_CX700_H */
                u32 esi, u32 edi) __attribute__((regparm(0)));
 #endif                         /* NORTHBRIDGE_VIA_CX700_H */

diff --git a/src/northbridge/via/vt8623/northbridge.h b/src/northbridge/via/vt8623/northbridge.h
index 9c0828741c40d82cdbe0101e73d65fdec6603de2..176a5904901bc73f4a58abc8da37d2ae7b6df856 100644 (file)
--- a/src/northbridge/via/vt8623/northbridge.h
+++ b/src/northbridge/via/vt8623/northbridge.h
@@ -2,7 +2,7 @@
 #define NORTHBRIDGE_VIA_VT8623_H
 
 unsigned int vt8623_scan_root_bus(device_t root, unsigned int max);
 #define NORTHBRIDGE_VIA_VT8623_H
 
 unsigned int vt8623_scan_root_bus(device_t root, unsigned int max);

-extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, 
+extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx,

                u32 esi, u32 edi) __attribute__((regparm(0)));
 
 #endif /* NORTHBRIDGE_VIA_VT8623_H */
                u32 esi, u32 edi) __attribute__((regparm(0)));
 
 #endif /* NORTHBRIDGE_VIA_VT8623_H */

diff --git a/src/northbridge/via/vx800/northbridge.h b/src/northbridge/via/vx800/northbridge.h
index 05f75d264961f736e0830536325882614d0fd820..4b51bb7c111f26b74d2bafc1e66e8b143f9c755e 100644 (file)
--- a/src/northbridge/via/vx800/northbridge.h
+++ b/src/northbridge/via/vx800/northbridge.h
@@ -21,7 +21,7 @@
 #define NORTHBRIDGE_VIA_VX800_H
 
 extern unsigned int vx800_scan_root_bus(device_t root, unsigned int max);
 #define NORTHBRIDGE_VIA_VX800_H
 
 extern unsigned int vx800_scan_root_bus(device_t root, unsigned int max);

-extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, 
+extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx,

                u32 esi, u32 edi) __attribute__((regparm(0)));
 
 #endif                         /* NORTHBRIDGE_VIA_VX800_H */
                u32 esi, u32 edi) __attribute__((regparm(0)));
 
 #endif                         /* NORTHBRIDGE_VIA_VX800_H */

diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
index d7317a23a20747db39d6b2175989fe1f38383a19..db5343dff0b9ee89474758696eb5ed0a999c8680 100644 (file)
--- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
+++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
@@ -20,7 +20,7 @@
  * ***************************************************************************
  *
  */
  * ***************************************************************************
  *
  */

- 
+

 #ifndef  _AMD_SBPLATFORM_H_
 #define  _AMD_SBPLATFORM_H_
 
 #ifndef  _AMD_SBPLATFORM_H_
 #define  _AMD_SBPLATFORM_H_
 


@@ -112,7 +112,7 @@ typedef union _PCI_ADDR {
  */
 #define SB_CIMx_PARAMETER  0x02
 
  */
 #define SB_CIMx_PARAMETER  0x02
 

-// Generic 
+// Generic

 #define cimSpreadSpectrumDefault        TRUE
 #define cimSpreadSpectrumTypeDefault   0x00      // Normal
 #define cimHpetTimerDefault             TRUE
 #define cimSpreadSpectrumDefault        TRUE
 #define cimSpreadSpectrumTypeDefault   0x00      // Normal
 #define cimHpetTimerDefault             TRUE


@@ -121,7 +121,7 @@ typedef union _PCI_ADDR {
 #define cimSpiFastReadEnableDefault     0x01      // Enable
 #define cimSpiFastReadSpeedDefault      0x01      // 33 MHz
 #define cimSioHwmPortEnableDefault      FALSE
 #define cimSpiFastReadEnableDefault     0x01      // Enable
 #define cimSpiFastReadSpeedDefault      0x01      // 33 MHz
 #define cimSioHwmPortEnableDefault      FALSE

-// GPP/AB Controller 
+// GPP/AB Controller

 #define cimNbSbGen2Default              TRUE
 #define cimAlinkPhyPllPowerDownDefault  TRUE
 #define cimResetCpuOnSyncFloodDefault   TRUE
 #define cimNbSbGen2Default              TRUE
 #define cimAlinkPhyPllPowerDownDefault  TRUE
 #define cimResetCpuOnSyncFloodDefault   TRUE


@@ -129,13 +129,13 @@ typedef union _PCI_ADDR {
 #define cimGppMemWrImproveDefault       TRUE
 #define cimGppPortAspmDefault           FALSE
 #define cimGppLaneReversalDefault       FALSE
 #define cimGppMemWrImproveDefault       TRUE
 #define cimGppPortAspmDefault           FALSE
 #define cimGppLaneReversalDefault       FALSE

-#define cimGppPhyPllPowerDownDefault    TRUE 
+#define cimGppPhyPllPowerDownDefault    TRUE

 // USB Controller
 #define cimUsbPhyPowerDownDefault       FALSE
 // GEC Controller
 #define cimSBGecDebugBusDefault         FALSE
 #define cimSBGecPwrDefault              0x03
 // USB Controller
 #define cimUsbPhyPowerDownDefault       FALSE
 // GEC Controller
 #define cimSBGecDebugBusDefault         FALSE
 #define cimSBGecPwrDefault              0x03

-// Sata Controller 
+// Sata Controller

 #define cimSataSetMaxGen2Default        0x00
 #define cimSATARefClkSelDefault         0x10
 #define cimSATARefDivSelDefault         0x80
 #define cimSataSetMaxGen2Default        0x00
 #define cimSATARefClkSelDefault         0x10
 #define cimSATARefDivSelDefault         0x80


@@ -143,11 +143,11 @@ typedef union _PCI_ADDR {
 #define cimSataPortMultCapDefault       TRUE
 #define cimSataPscCapDefault            0x00      // Enable
 #define cimSataSscCapDefault            0x00      // Enable
 #define cimSataPortMultCapDefault       TRUE
 #define cimSataPscCapDefault            0x00      // Enable
 #define cimSataSscCapDefault            0x00      // Enable

-#define cimSataFisBasedSwitchingDefault FALSE 
+#define cimSataFisBasedSwitchingDefault FALSE

 #define cimSataCccSupportDefault        FALSE
 #define cimSataClkAutoOffDefault        FALSE
 #define cimNativepciesupportDefault     FALSE
 #define cimSataCccSupportDefault        FALSE
 #define cimSataClkAutoOffDefault        FALSE
 #define cimNativepciesupportDefault     FALSE

-// Fusion Related 
+// Fusion Related

 #define cimAcDcMsgDefault               FALSE
 #define cimTimerTickTrackDefault        FALSE
 #define cimClockInterruptTagDefault     FALSE
 #define cimAcDcMsgDefault               FALSE
 #define cimTimerTickTrackDefault        FALSE
 #define cimClockInterruptTagDefault     FALSE

diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index 593bd6bfc748bf76c018fe56e269be698b0d0e7d..0a339b02f740b52e143c145e8739a677a46ee78e 100644 (file)
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -39,8 +39,8 @@ static void enable_rom(void)
        pci_io_write_config32(dev, 0x44, dword);
 
        /* SB800 LPC Bridge 0:20:3:48h.
        pci_io_write_config32(dev, 0x44, dword);
 
        /* SB800 LPC Bridge 0:20:3:48h.

-        * BIT0: Port Enable for SuperIO 0x2E-0x2F 
-        * BIT1: Port Enable for SuperIO 0x4E-0x4F 
+        * BIT0: Port Enable for SuperIO 0x2E-0x2F
+        * BIT1: Port Enable for SuperIO 0x4E-0x4F

         * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
         * BIT6: Port Enable for RTC IO 0x70-0x73
         * BIT21: Port Enable for Port 0x80
         * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
         * BIT6: Port Enable for RTC IO 0x70-0x73
         * BIT21: Port Enable for Port 0x80

diff --git a/src/southbridge/amd/cimx/sb900/Amd.h b/src/southbridge/amd/cimx/sb900/Amd.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/cimx/sb900/AmdSbLib.h b/src/southbridge/amd/cimx/sb900/AmdSbLib.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/cimx/sb900/SbEarly.h b/src/southbridge/amd/cimx/sb900/SbEarly.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c
old mode 100755 (executable)
new mode 100644 (file)
index e04cec0..e84743b
--- a/src/southbridge/amd/cimx/sb900/bootblock.c
+++ b/src/southbridge/amd/cimx/sb900/bootblock.c
@@ -73,8 +73,8 @@ static void sb900_enable_rom(void)
   pci_io_write_config32(dev, 0x44, dword);
 
   /* SB900 LPC Bridge 0:20:3:48h.
   pci_io_write_config32(dev, 0x44, dword);
 
   /* SB900 LPC Bridge 0:20:3:48h.

-   * BIT0: Port Enable for SuperIO 0x2E-0x2F 
-   * BIT1: Port Enable for SuperIO 0x4E-0x4F 
+   * BIT0: Port Enable for SuperIO 0x2E-0x2F
+   * BIT1: Port Enable for SuperIO 0x4E-0x4F

    * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
    * BIT6: Port Enable for RTC IO 0x70-0x73
    * BIT21: Port Enable for Port 0x80
    * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
    * BIT6: Port Enable for RTC IO 0x70-0x73
    * BIT21: Port Enable for Port 0x80


@@ -86,7 +86,7 @@ static void sb900_enable_rom(void)
   /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
   /* Set the 4MB enable bits */
   word = pci_io_read_config16(dev, 0x6c);
   /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
   /* Set the 4MB enable bits */
   word = pci_io_read_config16(dev, 0x6c);

-  word = 0xFFC0; 
+  word = 0xFFC0;

   pci_io_write_config16(dev, 0x6c, word);
 }
 
   pci_io_write_config16(dev, 0x6c, word);
 }
 

diff --git a/src/southbridge/amd/cimx/sb900/cbtypes.h b/src/southbridge/amd/cimx/sb900/cbtypes.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/cimx/sb900/chip.h b/src/southbridge/amd/cimx/sb900/chip.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/cimx/sb900/chip_name.c b/src/southbridge/amd/cimx/sb900/chip_name.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
old mode 100755 (executable)
new mode 100644 (file)
index bd4fd4f..1176ca5
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -142,7 +142,7 @@ void sb_Late_Post(void)
        //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
        // VerifyImage() will fail, LocateImage() take minitues to find the image.
        sbLatePost(&sb_early_cfg);
        //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
        // VerifyImage() will fail, LocateImage() take minitues to find the image.
        sbLatePost(&sb_early_cfg);

-       
+

        //Set ACPI SCI IRQ to 0x9.
        data = CONFIG_ACPI_SCI_IRQ;
        outb(0x10, 0xC00);
        //Set ACPI SCI IRQ to 0x9.
        data = CONFIG_ACPI_SCI_IRQ;
        outb(0x10, 0xC00);

diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/cimx/sb900/lpc.h b/src/southbridge/amd/cimx/sb900/lpc.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/cimx/sb900/smbus.c b/src/southbridge/amd/cimx/sb900/smbus.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/cimx/sb900/smbus.h b/src/southbridge/amd/cimx/sb900/smbus.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/rs690/ht.c b/src/southbridge/amd/rs690/ht.c
index dba28e789aadc7ff424d707a1c997fa5d6e70db3..5d816e59f4f1e1fa4c06baa8cf995f39b873ec72 100644 (file)
--- a/src/southbridge/amd/rs690/ht.c
+++ b/src/southbridge/amd/rs690/ht.c
@@ -28,25 +28,25 @@
 static void ht_dev_set_resources(device_t dev)
 {
 #if CONFIG_EXT_CONF_SUPPORT == 1
 static void ht_dev_set_resources(device_t dev)
 {
 #if CONFIG_EXT_CONF_SUPPORT == 1

-       unsigned reg;           
+       unsigned reg;

        device_t k8_f1;
        resource_t rbase, rend;
        u32 base, limit;
        struct resource *resource;
        device_t k8_f1;
        resource_t rbase, rend;
        u32 base, limit;
        struct resource *resource;

-       
+

        printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__);
        printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__);

-       
+

        resource = probe_resource(dev, 0x1C);
        if (resource) {
        resource = probe_resource(dev, 0x1C);
        if (resource) {

-               set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 0 << 3); // make bar3 visible  
+               set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 0 << 3); // make bar3 visible

                set_nbcfg_enable_bits(dev, 0x7C, 1 << 30, 1 << 30);     /* Enables writes to the BAR3 register. */
                set_nbcfg_enable_bits(dev, 0x7C, 1 << 30, 1 << 30);     /* Enables writes to the BAR3 register. */

-               set_nbcfg_enable_bits(dev, 0x84, 7 << 16, 0 << 16); // program bus range: 255 busses 
+               set_nbcfg_enable_bits(dev, 0x84, 7 << 16, 0 << 16); // program bus range: 255 busses

                pci_write_config32(dev, 0x1C, resource->base);
                /* Enable MMCONFIG decoding. */
                set_htiu_enable_bits(dev, 0x32, 1 << 28, 1 << 28);      /* PCIEMiscInit */
                set_nbcfg_enable_bits(dev, 0x7C, 1 << 30, 0 << 30);     /* Disable writes to the BAR3 register. */
                set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); // hide bar 3
                pci_write_config32(dev, 0x1C, resource->base);
                /* Enable MMCONFIG decoding. */
                set_htiu_enable_bits(dev, 0x32, 1 << 28, 1 << 28);      /* PCIEMiscInit */
                set_nbcfg_enable_bits(dev, 0x7C, 1 << 30, 0 << 30);     /* Disable writes to the BAR3 register. */
                set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); // hide bar 3

-               
+

                // setup resource nonposted in k8 mmio
                /* Get the base address */
                rbase = resource->base;
                // setup resource nonposted in k8 mmio
                /* Get the base address */
                rbase = resource->base;


@@ -74,9 +74,9 @@ static void ht_dev_set_resources(device_t dev)
                        limit &= 0x00000048;
                        limit |= ((rend >> 8) & 0xffffff00);
                        limit |= (sblk << 4);
                        limit &= 0x00000048;
                        limit |= ((rend >> 8) & 0xffffff00);
                        limit |= (sblk << 4);

-                       limit |= (1 << 7); 
+                       limit |= (1 << 7);

                        printk(BIOS_INFO, "%s <- index %x base %04x limit %04x\n", dev_path(k8_f1), reg, base, limit);
                        printk(BIOS_INFO, "%s <- index %x base %04x limit %04x\n", dev_path(k8_f1), reg, base, limit);

-                       pci_write_config32(k8_f1, reg+4, limit); 
+                       pci_write_config32(k8_f1, reg+4, limit);

                        pci_write_config32(k8_f1, reg, base);
                }
        }
                        pci_write_config32(k8_f1, reg, base);
                }
        }


@@ -88,13 +88,13 @@ static void ht_dev_read_resources(device_t dev)
 {
 #if CONFIG_EXT_CONF_SUPPORT == 1
        struct resource *res;
 {
 #if CONFIG_EXT_CONF_SUPPORT == 1
        struct resource *res;

-       
-       printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__);  
-       set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); // hide bar 3 
+
+       printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__);
+       set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); // hide bar 3

 #endif
 
        pci_dev_read_resources(dev);
 #endif
 
        pci_dev_read_resources(dev);

-       
+

 #if CONFIG_EXT_CONF_SUPPORT == 1
        /* Add an MMCONFIG resource. */
        res = new_resource(dev, 0x1C);
 #if CONFIG_EXT_CONF_SUPPORT == 1
        /* Add an MMCONFIG resource. */
        res = new_resource(dev, 0x1C);


@@ -104,9 +104,9 @@ static void ht_dev_read_resources(device_t dev)
        res->gran = log2(res->size);
        res->limit = 0xffffffffffffffffULL;     /* 64bit */
        res->flags = IORESOURCE_FIXED | IORESOURCE_MEM | IORESOURCE_PCI64 | IORESOURCE_ASSIGNED;
        res->gran = log2(res->size);
        res->limit = 0xffffffffffffffffULL;     /* 64bit */
        res->flags = IORESOURCE_FIXED | IORESOURCE_MEM | IORESOURCE_PCI64 | IORESOURCE_ASSIGNED;

-       
+

        compact_resources(dev);
        compact_resources(dev);

-#endif 
+#endif

 }
 
 /* for UMA internal graphics */
 }
 
 /* for UMA internal graphics */

diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c
index 4bd870bbf2ee5516cb0c3b5bbc5772a9f418278b..40a72627e0a34c9daa387f79e891ed95bc45b956 100644 (file)
--- a/src/southbridge/amd/rs780/cmn.c
+++ b/src/southbridge/amd/rs780/cmn.c
@@ -381,7 +381,7 @@ u32 extractbits(u32 source, int lsb, int msb)
 int cpuidFamily(void)
 {
        u32 baseFamily, extendedFamily, fms;
 int cpuidFamily(void)
 {
        u32 baseFamily, extendedFamily, fms;

-       
+

        fms = cpuid_eax (1);
        baseFamily = extractbits (fms, 8, 11);
        extendedFamily = extractbits (fms, 20, 27);
        fms = cpuid_eax (1);
        baseFamily = extractbits (fms, 8, 11);
        extendedFamily = extractbits (fms, 20, 27);

diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c
index 3c06d441ceb5de44b75f1f67a5448734d9ed4bb2..65a5e2bd2f21557eabc6bdf8a3c3149ef7114752 100644 (file)
--- a/src/southbridge/amd/rs780/gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
@@ -511,7 +511,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
                        vgainfo.ucUMAChannelNumber = 2;
                }
        }
                        vgainfo.ucUMAChannelNumber = 2;
                }
        }

-      
+

        // processor type
        if (is_family0Fh())
                vgainfo.ulCPUCapInfo = 3;
        // processor type
        if (is_family0Fh())
                vgainfo.ulCPUCapInfo = 3;


@@ -539,9 +539,9 @@ static void internal_gfx_pci_dev_init(struct device *dev)
 
        /* HT width. */
        value = pci_read_config8(nb_dev, 0xcb);
 
        /* HT width. */
        value = pci_read_config8(nb_dev, 0xcb);

-       vgainfo.usMinDownStreamHTLinkWidth = 
-       vgainfo.usMaxDownStreamHTLinkWidth = 
-       vgainfo.usMinUpStreamHTLinkWidth = 
+       vgainfo.usMinDownStreamHTLinkWidth =
+       vgainfo.usMaxDownStreamHTLinkWidth =
+       vgainfo.usMinUpStreamHTLinkWidth =

        vgainfo.usMaxUpStreamHTLinkWidth =
        vgainfo.usMinHTLinkWidth =
        vgainfo.usMaxHTLinkWidth = ht_width_lookup [extractbits(value, 0, 2)];
        vgainfo.usMaxUpStreamHTLinkWidth =
        vgainfo.usMinHTLinkWidth =
        vgainfo.usMaxHTLinkWidth = ht_width_lookup [extractbits(value, 0, 2)];

diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
index cf6d2dfb1a34153468a6a127628ef3ec2504a5c9..717aeab2c6cef3244f26bf8ba5b6bd152b275bc1 100644 (file)
--- a/src/southbridge/amd/rs780/rs780.c
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -223,7 +223,7 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
 #if (CONFIG_GFXUMA == 1)
        extern uint64_t uma_memory_size;
        // bits 7-9: aperture size
 #if (CONFIG_GFXUMA == 1)
        extern uint64_t uma_memory_size;
        // bits 7-9: aperture size

-       // 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g 
+       // 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g

        if (uma_memory_size == 0x02000000) romstrap2 |= 3 << 7;
        if (uma_memory_size == 0x04000000) romstrap2 |= 2 << 7;
        if (uma_memory_size == 0x08000000) romstrap2 |= 0 << 7;
        if (uma_memory_size == 0x02000000) romstrap2 |= 3 << 7;
        if (uma_memory_size == 0x04000000) romstrap2 |= 2 << 7;
        if (uma_memory_size == 0x08000000) romstrap2 |= 0 << 7;

diff --git a/src/southbridge/amd/sb600/sata.c b/src/southbridge/amd/sb600/sata.c
index 7eda2e854c3c3447ba5779ba1976e25da19f7459..121e3d7cbf477f7b0f44c7560b8ef7b0ae2804a2 100644 (file)
--- a/src/southbridge/amd/sb600/sata.c
+++ b/src/southbridge/amd/sb600/sata.c
@@ -123,8 +123,8 @@ static void sata_init(struct device *dev)
                // no cmos option
                i = CONFIG_SATA_MODE;
        }
                // no cmos option
                i = CONFIG_SATA_MODE;
        }

-       printk(BIOS_INFO, "%s: setting sata mode = %s\n", __func__, (i == SATA_MODE_IDE)?"ide":"ahci" );        
-       
+       printk(BIOS_INFO, "%s: setting sata mode = %s\n", __func__, (i == SATA_MODE_IDE)?"ide":"ahci" );
+

        dword = pci_read_config32(dev, 0x8);
        dword &= 0xff0000ff;
        if (i == SATA_MODE_IDE)
        dword = pci_read_config32(dev, 0x8);
        dword &= 0xff0000ff;
        if (i == SATA_MODE_IDE)

diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/sb700/ide.c b/src/southbridge/amd/sb700/ide.c
index 4652ca2539ec6ff9cbe9cf24e1d5f15ce0e4825f..5f415fb9f2b09917e8b145a90373ac4f63f468d6 100644 (file)
--- a/src/southbridge/amd/sb700/ide.c
+++ b/src/southbridge/amd/sb700/ide.c
@@ -51,8 +51,8 @@ static void ide_init(struct device *dev)
 
        /* set ide as primary, if you want to boot from IDE, you'd better set it
         * in $vendor/$mainboard/devicetree.cb */
 
        /* set ide as primary, if you want to boot from IDE, you'd better set it
         * in $vendor/$mainboard/devicetree.cb */

-        
-       
+
+

        if (conf->boot_switch_sata_ide == 1) {
                struct device *sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
                byte = pci_read_config8(sm_dev, 0xAD);
        if (conf->boot_switch_sata_ide == 1) {
                struct device *sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
                byte = pci_read_config8(sm_dev, 0xAD);

diff --git a/src/southbridge/amd/sb700/pmio.c b/src/southbridge/amd/sb700/pmio.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/sb700/pmio.h b/src/southbridge/amd/sb700/pmio.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/sb700/smbus.c b/src/southbridge/amd/sb700/smbus.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/sb700/smbus.h b/src/southbridge/amd/sb700/smbus.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/amd/sr5650/sr5650.h b/src/southbridge/amd/sr5650/sr5650.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/southbridge/ti/pcixx12/chip.h b/src/southbridge/ti/pcixx12/chip.h
index 68612499c55c4af71893c229cc34afe6487711ca..42dc79cd1a48d7de28084bf876df10b0be99e3f5 100644 (file)
--- a/src/southbridge/ti/pcixx12/chip.h
+++ b/src/southbridge/ti/pcixx12/chip.h
@@ -24,7 +24,7 @@ extern struct chip_operations southbridge_ti_pcixx12_ops;
 
 struct southbridge_ti_pcixx12_config {
        int dummy;
 
 struct southbridge_ti_pcixx12_config {
        int dummy;

-       
+

 };
 
 #endif /* _SOUTHBRIDGE_TI_PCIXX12 */
 };
 
 #endif /* _SOUTHBRIDGE_TI_PCIXX12 */

diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c
index 701b93d5f1e0eda5c61848146163601139f96688..1b21b321661c125fc8072d8beeffbaf729d25505 100644 (file)
--- a/src/southbridge/via/k8t890/bridge.c
+++ b/src/southbridge/via/k8t890/bridge.c
@@ -27,7 +27,7 @@ static void bridge_enable(struct device *dev)
 {
        u8 tmp;
        print_debug("B188 device dump\n");
 {
        u8 tmp;
        print_debug("B188 device dump\n");

-       
+

        /* VIA recommends this, sorry no known info. */
 
        writeback(dev, 0x40, 0x91);
        /* VIA recommends this, sorry no known info. */
 
        writeback(dev, 0x40, 0x91);

diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c
index a2a5fe9edce2987d9a0a63414f358ad92a83a19a..42676b177048842bcced77c47b78ce0597bf12d3 100644 (file)
--- a/src/southbridge/via/k8t890/ctrl.c
+++ b/src/southbridge/via/k8t890/ctrl.c
@@ -34,7 +34,7 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb)
        u8 regm, regm3;
 
        device_t devfun3;
        u8 regm, regm3;
 
        device_t devfun3;

-       
+

        devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
                                           PCI_DEVICE_ID_VIA_K8T800_DRAM, 0);
 
        devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
                                           PCI_DEVICE_ID_VIA_K8T800_DRAM, 0);
 


@@ -45,7 +45,7 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb)
        if (!devfun3)
                devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
                                           PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
        if (!devfun3)
                devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
                                           PCI_DEVICE_ID_VIA_K8T890CE_3, 0);

-               
+

        if (!devfun3)
                devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
                                           PCI_DEVICE_ID_VIA_K8T890CF_3, 0);
        if (!devfun3)
                devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
                                           PCI_DEVICE_ID_VIA_K8T890CF_3, 0);


@@ -53,12 +53,12 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb)
        if (!devfun3)
                devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
                                           PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
        if (!devfun3)
                devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
                                           PCI_DEVICE_ID_VIA_K8M890CE_3, 0);

-       
+

        if(!devfun3)
                die("\n vt8237r_cfg: Unable to find K8x8xx bridge via PCI scan. Stopping.\n");
 
        pci_write_config8(dev, 0x70, 0xc2);
        if(!devfun3)
                die("\n vt8237r_cfg: Unable to find K8x8xx bridge via PCI scan. Stopping.\n");
 
        pci_write_config8(dev, 0x70, 0xc2);

-       
+

        /* PCI Control */
        pci_write_config8(dev, 0x72, 0xee);
        pci_write_config8(dev, 0x73, 0x01);
        /* PCI Control */
        pci_write_config8(dev, 0x72, 0xee);
        pci_write_config8(dev, 0x73, 0x01);


@@ -157,7 +157,7 @@ static void vt8237r_vlink_init(struct device *dev)
        pci_write_config8(dev, 0x48, 0xa3);
 }
 
        pci_write_config8(dev, 0x48, 0xa3);
 }
 

-static void ctrl_init(struct device *dev) 
+static void ctrl_init(struct device *dev)

 {
 
        print_debug("K8x8xx: Initializing V-Link to VT8237R sb: ");
 {
 
        print_debug("K8x8xx: Initializing V-Link to VT8237R sb: ");

diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c
index dd65b508ca409974c4c41df0e186461580ddaef0..9b43a5e57f23118c10b3b5bf5adeb5d2e8a759a2 100644 (file)
--- a/src/southbridge/via/k8t890/dram.c
+++ b/src/southbridge/via/k8t890/dram.c
@@ -65,7 +65,7 @@ static void dram_enable(struct device *dev)
 
        /* The Address Next to the Last Valid DRAM Address */
        pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg);
 
        /* The Address Next to the Last Valid DRAM Address */
        pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg);

-       
+

        print_debug(" VIA_X_3 device dump:\n");
        dump_south(dev);
 
        print_debug(" VIA_X_3 device dump:\n");
        dump_south(dev);
 

diff --git a/src/southbridge/via/k8t890/error.c b/src/southbridge/via/k8t890/error.c
index a5f86bf4e9c79268ba8221d78429e38625a26f47..f2cab10db054b7a36d64aa1fec30c170f845d667 100644 (file)
--- a/src/southbridge/via/k8t890/error.c
+++ b/src/southbridge/via/k8t890/error.c
@@ -36,7 +36,7 @@ static void error_enable(struct device *dev)
 
        print_debug("Done\n");
        /* TODO: enable AGP errors reporting on K8M890 */
 
        print_debug("Done\n");
        /* TODO: enable AGP errors reporting on K8M890 */

-       
+

        print_debug(" VIA_X_1 device dump:\n");
        dump_south(dev);
 }
        print_debug(" VIA_X_1 device dump:\n");
        dump_south(dev);
 }

diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h
index 7f30f3b7a3b238b8ce04fb6ba5398589bf7403b4..a0fb57ab3c16a130239e6b2134fb188e669dba26 100644 (file)
--- a/src/southbridge/via/k8t890/k8x8xx.h
+++ b/src/southbridge/via/k8t890/k8x8xx.h
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
 /*
  * This file is part of the coreboot project.

- * 
+ *

  * Copyright (C) 2011  Alexandru Gagniuc <mr.nuke.me@gmail.com>
  *
  * This program is free software: you can redistribute it and/or modify
  * Copyright (C) 2011  Alexandru Gagniuc <mr.nuke.me@gmail.com>
  *
  * This program is free software: you can redistribute it and/or modify


@@ -12,7 +12,7 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.

- * 
+ *

  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA

diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 3e2f215751024c49ba910b34956b69f9a4621c17..e59951702f00094fb5c5b5ba8820438e35991d02 100644 (file)
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -297,7 +297,7 @@ static void vt8237r_init(struct device *dev)
         */
        pci_write_config8(dev, 0x48, 0x0c);
 #else
         */
        pci_write_config8(dev, 0x48, 0x0c);
 #else

-       
+

   #if CONFIG_SOUTHBRIDGE_VIA_K8T800
        /* It seems that when we pair with the K8T800, we need to disable
         * the A2 mask
   #if CONFIG_SOUTHBRIDGE_VIA_K8T800
        /* It seems that when we pair with the K8T800, we need to disable
         * the A2 mask


@@ -310,7 +310,7 @@ static void vt8237r_init(struct device *dev)
         */
        pci_write_config8(dev, 0x48, 0x8c);
   #endif
         */
        pci_write_config8(dev, 0x48, 0x8c);
   #endif

-       
+

 #endif
 
        southbridge_init_common(dev);
 #endif
 
        southbridge_init_common(dev);


@@ -327,7 +327,7 @@ static void vt8237r_init(struct device *dev)
 
        printk(BIOS_SPEW, "Leaving %s.\n", __func__);
        printk(BIOS_SPEW, "And taking a dump:\n");
 
        printk(BIOS_SPEW, "Leaving %s.\n", __func__);
        printk(BIOS_SPEW, "And taking a dump:\n");

-       dump_south(dev);        
+       dump_south(dev);

 }
 
 static void vt8237a_init(struct device *dev)
 }
 
 static void vt8237a_init(struct device *dev)

diff --git a/src/superio/fintek/f71805f/chip.h b/src/superio/fintek/f71805f/chip.h
index 6e9c6c92419bcafd0164793397d617bd7b01938f..60eb684a32b276c0444389827ebaec24484031b0 100644 (file)
--- a/src/superio/fintek/f71805f/chip.h
+++ b/src/superio/fintek/f71805f/chip.h
@@ -29,7 +29,7 @@
 extern struct chip_operations superio_fintek_f71805f_ops;
 
 struct superio_fintek_f71805f_config {
 extern struct chip_operations superio_fintek_f71805f_ops;
 
 struct superio_fintek_f71805f_config {

-       
+

 };
 
 #endif
 };
 
 #endif

diff --git a/src/superio/fintek/f71859/chip.h b/src/superio/fintek/f71859/chip.h
old mode 100755 (executable)
new mode 100644 (file)
index 8400862..157ed26
--- a/src/superio/fintek/f71859/chip.h
+++ b/src/superio/fintek/f71859/chip.h
@@ -27,7 +27,7 @@
 extern struct chip_operations superio_fintek_f71859_ops;
 
 struct superio_fintek_f71859_config {
 extern struct chip_operations superio_fintek_f71859_ops;
 
 struct superio_fintek_f71859_config {

-       
+

 };
 
 #endif
 };
 
 #endif

diff --git a/src/superio/fintek/f71859/early_serial.c b/src/superio/fintek/f71859/early_serial.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/superio/fintek/f71859/f71859.h b/src/superio/fintek/f71859/f71859.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/superio/fintek/f71859/superio.c b/src/superio/fintek/f71859/superio.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/superio/fintek/f71863fg/chip.h b/src/superio/fintek/f71863fg/chip.h
index ce9fd480b22e6f5805213f02c3b4a6720672309d..ade7498e351353ae03a4e4699201809eeed37eee 100644 (file)
--- a/src/superio/fintek/f71863fg/chip.h
+++ b/src/superio/fintek/f71863fg/chip.h
@@ -28,7 +28,7 @@
 extern struct chip_operations superio_fintek_f71863fg_ops;
 
 struct superio_fintek_f71863fg_config {
 extern struct chip_operations superio_fintek_f71863fg_ops;
 
 struct superio_fintek_f71863fg_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/fintek/f71872/chip.h b/src/superio/fintek/f71872/chip.h
index 58ee4217ca0cb41401cb17988513ad1204632e17..bd41dd679df5b2d6782bfbc06ce8d52bbf335634 100644 (file)
--- a/src/superio/fintek/f71872/chip.h
+++ b/src/superio/fintek/f71872/chip.h
@@ -27,7 +27,7 @@
 extern struct chip_operations superio_fintek_f71872_ops;
 
 struct superio_fintek_f71872_config {
 extern struct chip_operations superio_fintek_f71872_ops;
 
 struct superio_fintek_f71872_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/fintek/f71889/chip.h b/src/superio/fintek/f71889/chip.h
index c7752164cbe7519ad2e7b3e7791c99f30cf4f466..65ae8700abbd8a620179c13d3ad306b79050d319 100644 (file)
--- a/src/superio/fintek/f71889/chip.h
+++ b/src/superio/fintek/f71889/chip.h
@@ -28,7 +28,7 @@
 extern struct chip_operations superio_fintek_f71889_ops;
 
 struct superio_fintek_f71889_config {
 extern struct chip_operations superio_fintek_f71889_ops;
 
 struct superio_fintek_f71889_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/fintek/f81865f/chip.h b/src/superio/fintek/f81865f/chip.h
index 6ff30012ca10ff164bb22cfaa5affc409b589fa5..711e2d0a58c72da3a65b3b8b5c9e8a9b1c5bcfa6 100644 (file)
--- a/src/superio/fintek/f81865f/chip.h
+++ b/src/superio/fintek/f81865f/chip.h
@@ -29,7 +29,7 @@
 extern struct chip_operations superio_fintek_f81865f_ops;
 
 struct superio_fintek_f81865f_config {
 extern struct chip_operations superio_fintek_f81865f_ops;
 
 struct superio_fintek_f81865f_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/ite/it8661f/chip.h b/src/superio/ite/it8661f/chip.h
index 744316e0e43574c588100ba5389512fcec13f6e3..64b2cf873f77fc855247ecfb14a49f2518543736 100644 (file)
--- a/src/superio/ite/it8661f/chip.h
+++ b/src/superio/ite/it8661f/chip.h
@@ -29,7 +29,7 @@
 extern struct chip_operations superio_ite_it8661f_ops;
 
 struct superio_ite_it8661f_config {
 extern struct chip_operations superio_ite_it8661f_ops;
 
 struct superio_ite_it8661f_config {

-       
+

 };
 
 #endif
 };
 
 #endif

diff --git a/src/superio/ite/it8671f/chip.h b/src/superio/ite/it8671f/chip.h
index 3dd2d81a5b2d81faa78cf0943b73e7f6168776d2..7fa7e26f578b20d15042be40901d2f6facd06e34 100644 (file)
--- a/src/superio/ite/it8671f/chip.h
+++ b/src/superio/ite/it8671f/chip.h
@@ -28,7 +28,7 @@
 extern struct chip_operations superio_ite_it8671f_ops;
 
 struct superio_ite_it8671f_config {
 extern struct chip_operations superio_ite_it8671f_ops;
 
 struct superio_ite_it8671f_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/ite/it8673f/chip.h b/src/superio/ite/it8673f/chip.h
index 431098e4337b1a756b6699aa9b147f4513f34cbe..126180a19fe45c606ecb2fac5695687098b12b20 100644 (file)
--- a/src/superio/ite/it8673f/chip.h
+++ b/src/superio/ite/it8673f/chip.h
@@ -28,7 +28,7 @@
 extern struct chip_operations superio_ite_it8673f_ops;
 
 struct superio_ite_it8673f_config {
 extern struct chip_operations superio_ite_it8673f_ops;
 
 struct superio_ite_it8673f_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/ite/it8705f/chip.h b/src/superio/ite/it8705f/chip.h
index be4a8d7b6d5a11a262afc4e6aaf371ae875fe81f..df620a8906cc34a8cb7ff0d47a49354df95fdf05 100644 (file)
--- a/src/superio/ite/it8705f/chip.h
+++ b/src/superio/ite/it8705f/chip.h
@@ -29,7 +29,7 @@
 extern struct chip_operations superio_ite_it8705f_ops;
 
 struct superio_ite_it8705f_config {
 extern struct chip_operations superio_ite_it8705f_ops;
 
 struct superio_ite_it8705f_config {

-       
+

 };
 
 #endif
 };
 
 #endif

diff --git a/src/superio/ite/it8712f/chip.h b/src/superio/ite/it8712f/chip.h
index 76401099dff6a1d5ffd7f269d3247b1e7bace00c..18630066db43e155c9b11c5f2c53e70de1e594c0 100644 (file)
--- a/src/superio/ite/it8712f/chip.h
+++ b/src/superio/ite/it8712f/chip.h
@@ -28,7 +28,7 @@
 extern struct chip_operations superio_ite_it8712f_ops;
 
 struct superio_ite_it8712f_config {
 extern struct chip_operations superio_ite_it8712f_ops;
 
 struct superio_ite_it8712f_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/ite/it8716f/chip.h b/src/superio/ite/it8716f/chip.h
index 0c2f387a3e7a6608862db0f1c98643b57ed73e2f..16b69ce2614c10702ed6d716bae7cfa645d67c1f 100644 (file)
--- a/src/superio/ite/it8716f/chip.h
+++ b/src/superio/ite/it8716f/chip.h
@@ -28,7 +28,7 @@
 extern struct chip_operations superio_ite_it8716f_ops;
 
 struct superio_ite_it8716f_config {
 extern struct chip_operations superio_ite_it8716f_ops;
 
 struct superio_ite_it8716f_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/ite/it8718f/chip.h b/src/superio/ite/it8718f/chip.h
index 78044aa1d792a1f44d61b97866b39f3ee1bbdd55..43f7152fbb84e62ed2c6cc5951317ab341b1f644 100644 (file)
--- a/src/superio/ite/it8718f/chip.h
+++ b/src/superio/ite/it8718f/chip.h
@@ -28,7 +28,7 @@
 extern struct chip_operations superio_ite_it8718f_ops;
 
 struct superio_ite_it8718f_config {
 extern struct chip_operations superio_ite_it8718f_ops;
 
 struct superio_ite_it8718f_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/nsc/pc8374/chip.h b/src/superio/nsc/pc8374/chip.h
index ec0a57a61797e9cdd106e3e57feadb2617a75a3e..4ae78f8ac0ab593e917294d6c7ef7fc49a88052b 100644 (file)
--- a/src/superio/nsc/pc8374/chip.h
+++ b/src/superio/nsc/pc8374/chip.h
@@ -29,7 +29,7 @@ extern struct chip_operations superio_nsc_pc8374_ops;
 #include <uart8250.h>
 
 struct superio_nsc_pc8374_config {
 #include <uart8250.h>
 
 struct superio_nsc_pc8374_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/nsc/pc87309/chip.h b/src/superio/nsc/pc87309/chip.h
index 8a612245bd6719662683313cf8eb17df5025a159..b9f5a7a9f9a4ca3abb6b6eaf466f3f7cad7fc425 100644 (file)
--- a/src/superio/nsc/pc87309/chip.h
+++ b/src/superio/nsc/pc87309/chip.h
@@ -27,7 +27,7 @@
 extern struct chip_operations superio_nsc_pc87309_ops;
 
 struct superio_nsc_pc87309_config {
 extern struct chip_operations superio_nsc_pc87309_ops;
 
 struct superio_nsc_pc87309_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/nsc/pc87351/chip.h b/src/superio/nsc/pc87351/chip.h
index cb835c7963043ff494d8bcc546f1380745b3729f..46b56afb719f89cea46d9e5676d0913fb16e1941 100644 (file)
--- a/src/superio/nsc/pc87351/chip.h
+++ b/src/superio/nsc/pc87351/chip.h
@@ -29,7 +29,7 @@ extern struct chip_operations superio_nsc_pc87351_ops;
 #include <uart8250.h>
 
 struct superio_nsc_pc87351_config {
 #include <uart8250.h>
 
 struct superio_nsc_pc87351_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/nsc/pc87360/chip.h b/src/superio/nsc/pc87360/chip.h
index 712176dd8afe8338d038d013b87d3bcead468f2b..0cc6a89ee710c8e03004cf2e9713bccbb78f6edf 100644 (file)
--- a/src/superio/nsc/pc87360/chip.h
+++ b/src/superio/nsc/pc87360/chip.h
@@ -29,7 +29,7 @@ extern struct chip_operations superio_nsc_pc87360_ops;
 #include <uart8250.h>
 
 struct superio_nsc_pc87360_config {
 #include <uart8250.h>
 
 struct superio_nsc_pc87360_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/nsc/pc87366/chip.h b/src/superio/nsc/pc87366/chip.h
index 75ce691ac0f440b2e6d7bea360f7916aa1bdc16e..6f656d4a65e51474d464d6a147a96f3d629746ab 100644 (file)
--- a/src/superio/nsc/pc87366/chip.h
+++ b/src/superio/nsc/pc87366/chip.h
@@ -28,7 +28,7 @@ extern struct chip_operations superio_nsc_pc87366_ops;
 #include <uart8250.h>
 
 struct superio_nsc_pc87366_config {
 #include <uart8250.h>
 
 struct superio_nsc_pc87366_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/nsc/pc87382/chip.h b/src/superio/nsc/pc87382/chip.h
index 18d570ad1e49f160300568ed66d917ecb01a3774..8cc049f52f3d338a4b1bdc3fb4812daf2b3a2f32 100644 (file)
--- a/src/superio/nsc/pc87382/chip.h
+++ b/src/superio/nsc/pc87382/chip.h
@@ -25,7 +25,7 @@
 extern struct chip_operations superio_nsc_pc87382_ops;
 
 struct superio_nsc_pc87382_config {
 extern struct chip_operations superio_nsc_pc87382_ops;
 
 struct superio_nsc_pc87382_config {

-       
+

 };
 
 #endif
 };
 
 #endif

diff --git a/src/superio/nsc/pc87384/chip.h b/src/superio/nsc/pc87384/chip.h
index d0064789623a1ddb10db08766e7599c6f7c0f247..ef202fc68bbbd8eba661ae9f4b91dca60c45cc89 100644 (file)
--- a/src/superio/nsc/pc87384/chip.h
+++ b/src/superio/nsc/pc87384/chip.h
@@ -25,7 +25,7 @@
 extern struct chip_operations superio_nsc_pc87384_ops;
 
 struct superio_nsc_pc87384_config {
 extern struct chip_operations superio_nsc_pc87384_ops;
 
 struct superio_nsc_pc87384_config {

-       
+

 };
 
 #endif
 };
 
 #endif

diff --git a/src/superio/nsc/pc87392/chip.h b/src/superio/nsc/pc87392/chip.h
index 1241cb2f44a86e23c352fcd878d277869c7fa2e2..8b5fc52bfe3ff59631abfb8f5855080f640faed7 100644 (file)
--- a/src/superio/nsc/pc87392/chip.h
+++ b/src/superio/nsc/pc87392/chip.h
@@ -26,7 +26,7 @@ extern struct chip_operations superio_nsc_pc87392_ops;
 #include <uart8250.h>
 
 struct superio_nsc_pc87392_config {
 #include <uart8250.h>
 
 struct superio_nsc_pc87392_config {

-       
+

 };
 
 #endif
 };
 
 #endif

diff --git a/src/superio/nsc/pc87417/chip.h b/src/superio/nsc/pc87417/chip.h
index a66bb40a97c757540b4adf45048fb21dd5bf8564..ec3c381c92dbdd11d2fe123b76dc590f96b33e5a 100644 (file)
--- a/src/superio/nsc/pc87417/chip.h
+++ b/src/superio/nsc/pc87417/chip.h
@@ -29,7 +29,7 @@ extern struct chip_operations superio_nsc_pc87417_ops;
 #include <uart8250.h>
 
 struct superio_nsc_pc87417_config {
 #include <uart8250.h>
 
 struct superio_nsc_pc87417_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/nsc/pc87427/chip.h b/src/superio/nsc/pc87427/chip.h
index d044fe09ff73304587b875fedc0a179e333b0c51..610dbdf8f72fd1e524b2e981a00d6f51c8f8ff98 100644 (file)
--- a/src/superio/nsc/pc87427/chip.h
+++ b/src/superio/nsc/pc87427/chip.h
@@ -28,7 +28,7 @@ extern struct chip_operations superio_nsc_pc87427_ops;
 #include <uart8250.h>
 
 struct superio_nsc_pc87427_config {
 #include <uart8250.h>
 
 struct superio_nsc_pc87427_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/nsc/pc97307/chip.h b/src/superio/nsc/pc97307/chip.h
index 838d36b9e2131a95a65d56158a302e2bea160206..cc43323f7925cf5eb3843a9babcdfa29e707d9c7 100644 (file)
--- a/src/superio/nsc/pc97307/chip.h
+++ b/src/superio/nsc/pc97307/chip.h
@@ -34,7 +34,7 @@ extern struct chip_operations superio_nsc_pc97307_ops;
 #include <uart8250.h>
 
 struct superio_nsc_pc97307_config {
 #include <uart8250.h>
 
 struct superio_nsc_pc97307_config {

-       
+

        struct pc_keyboard keyboard;
 };
 #endif
        struct pc_keyboard keyboard;
 };
 #endif

diff --git a/src/superio/nsc/pc97317/chip.h b/src/superio/nsc/pc97317/chip.h
index 6c415f6aee0eba0090c2bcb55c712419975c6184..4eb0c19cd9c130bc9aa96246403453071f4bddb3 100644 (file)
--- a/src/superio/nsc/pc97317/chip.h
+++ b/src/superio/nsc/pc97317/chip.h
@@ -34,7 +34,7 @@ extern struct chip_operations superio_nsc_pc97317_ops;
 #include <uart8250.h>
 
 struct superio_nsc_pc97317_config {
 #include <uart8250.h>
 
 struct superio_nsc_pc97317_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/nuvoton/wpcm450/chip.h b/src/superio/nuvoton/wpcm450/chip.h
index 2afc2de5975a907c55e265c9feef2d7942f2be16..c921120501a2c2617031a8c4e4da862e5bc19158 100644 (file)
--- a/src/superio/nuvoton/wpcm450/chip.h
+++ b/src/superio/nuvoton/wpcm450/chip.h
@@ -28,7 +28,7 @@ extern struct chip_operations superio_nuvoton_wpcm450_ops;
 #include <uart8250.h>
 
 struct superio_nuvoton_wpcm450_config {
 #include <uart8250.h>
 
 struct superio_nuvoton_wpcm450_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/nuvoton/wpcm450/early_init.c b/src/superio/nuvoton/wpcm450/early_init.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/superio/nuvoton/wpcm450/wpcm450.h b/src/superio/nuvoton/wpcm450/wpcm450.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/src/superio/smsc/fdc37m60x/chip.h b/src/superio/smsc/fdc37m60x/chip.h
index 2a1186fe0eea3ef687e3964781141961efd8bcd8..450ef75fbe98bf31c164af4b6e85a66e0c85f91f 100644 (file)
--- a/src/superio/smsc/fdc37m60x/chip.h
+++ b/src/superio/smsc/fdc37m60x/chip.h
@@ -28,7 +28,7 @@
 extern struct chip_operations superio_smsc_fdc37m60x_ops;
 
 struct superio_smsc_fdc37m60x_config {
 extern struct chip_operations superio_smsc_fdc37m60x_ops;
 
 struct superio_smsc_fdc37m60x_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/smsc/fdc37n972/chip.h b/src/superio/smsc/fdc37n972/chip.h
index abaf76515347b41dcf6acf45589fad5d12ddb317..858cf532c194d150cd444da05984da8c3adf3a43 100644 (file)
--- a/src/superio/smsc/fdc37n972/chip.h
+++ b/src/superio/smsc/fdc37n972/chip.h
@@ -27,7 +27,7 @@
 extern struct chip_operations superio_smsc_fdc37n972_ops;
 
 struct superio_smsc_fdc37n972_config {
 extern struct chip_operations superio_smsc_fdc37n972_ops;
 
 struct superio_smsc_fdc37n972_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/smsc/kbc1100/chip.h b/src/superio/smsc/kbc1100/chip.h
index 020224f6505150219a333a770b3b7802f6c9a530..40aff0bf7d03512fe03a6172593e7174e8deaf31 100644 (file)
--- a/src/superio/smsc/kbc1100/chip.h
+++ b/src/superio/smsc/kbc1100/chip.h
@@ -27,7 +27,7 @@ struct chip_operations;
 extern struct chip_operations superio_smsc_kbc1100_ops;
 
 struct superio_smsc_kbc1100_config {
 extern struct chip_operations superio_smsc_kbc1100_ops;
 
 struct superio_smsc_kbc1100_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/smsc/kbc1100/kbc1100_early_init.c b/src/superio/smsc/kbc1100/kbc1100_early_init.c
index 4247a96318d1d72a7ca2d7e7640f00a46ce9248c..84aa4e05104d479d7b9d12c008df807242cad77c 100644 (file)
--- a/src/superio/smsc/kbc1100/kbc1100_early_init.c
+++ b/src/superio/smsc/kbc1100/kbc1100_early_init.c
@@ -40,11 +40,11 @@ static inline void kbc1100_early_init(unsigned port)
   dev = PNP_DEV (port, KBC1100_KBC);
 
   pnp_enter_conf_state(dev);
   dev = PNP_DEV (port, KBC1100_KBC);
 
   pnp_enter_conf_state(dev);

-  
+

   /* Serial IRQ enabled */
   outb(0x25, port);
   outb(0x04, port + 1);
   /* Serial IRQ enabled */
   outb(0x25, port);
   outb(0x04, port + 1);

-  
+

   /* Enable SMSC UART 0 */
   dev = PNP_DEV (port, SMSCSUPERIO_SP1);
   pnp_set_logical_device(dev);
   /* Enable SMSC UART 0 */
   dev = PNP_DEV (port, SMSCSUPERIO_SP1);
   pnp_set_logical_device(dev);


@@ -70,6 +70,6 @@ static inline void kbc1100_early_init(unsigned port)
   pnp_exit_conf_state(dev);
 
   /* disable the 1s timer */
   pnp_exit_conf_state(dev);
 
   /* disable the 1s timer */

-  outb(0xE7, 0x64);  
+  outb(0xE7, 0x64);

 }
 
 }
 

diff --git a/src/superio/smsc/kbc1100/superio.c b/src/superio/smsc/kbc1100/superio.c
index bd330bac4aa9e97b8d587e01d966b6e35716abd2..c4fde9596084ba02cfd4b19219b13e5a2b3c43e8 100644 (file)
--- a/src/superio/smsc/kbc1100/superio.c
+++ b/src/superio/smsc/kbc1100/superio.c
@@ -97,14 +97,14 @@ static void kbc1100_init(device_t dev)
   struct superio_smsc_kbc1100_config *conf = dev->chip_info;
   struct resource *res0, *res1;
 
   struct superio_smsc_kbc1100_config *conf = dev->chip_info;
   struct resource *res0, *res1;
 

-  
-   
+
+

   if (!dev->enabled) {
     return;
   }
 
   switch(dev->path.pnp.device) {
   if (!dev->enabled) {
     return;
   }
 
   switch(dev->path.pnp.device) {

-  
+

   case KBC1100_KBC:
     res0 = find_resource(dev, PNP_IDX_IO0);
     res1 = find_resource(dev, PNP_IDX_IO1);
   case KBC1100_KBC:
     res0 = find_resource(dev, PNP_IDX_IO0);
     res1 = find_resource(dev, PNP_IDX_IO1);

diff --git a/src/superio/smsc/lpc47b272/chip.h b/src/superio/smsc/lpc47b272/chip.h
index 031cd20f55e1c3e9f709514cd2ecc1164b892246..754d63d9677a3f28c5e8512e6b7a896420c32801 100644 (file)
--- a/src/superio/smsc/lpc47b272/chip.h
+++ b/src/superio/smsc/lpc47b272/chip.h
@@ -28,7 +28,7 @@ extern struct chip_operations superio_smsc_lpc47b272_ops;
 #include <uart8250.h>
 
 struct superio_smsc_lpc47b272_config {
 #include <uart8250.h>
 
 struct superio_smsc_lpc47b272_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/smsc/lpc47b397/chip.h b/src/superio/smsc/lpc47b397/chip.h
index 3f3c719bf45fdaecb764690216334d556bcea563..48fc6e475d15f65f271fc4c4d36945101bb5ee02 100644 (file)
--- a/src/superio/smsc/lpc47b397/chip.h
+++ b/src/superio/smsc/lpc47b397/chip.h
@@ -30,7 +30,7 @@ extern struct chip_operations superio_smsc_lpc47b397_ops;
 #include <uart8250.h>
 
 struct superio_smsc_lpc47b397_config {
 #include <uart8250.h>
 
 struct superio_smsc_lpc47b397_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/smsc/lpc47m10x/chip.h b/src/superio/smsc/lpc47m10x/chip.h
index 79b72dae43a4dcc380c2e3c8a3c6a2327f31de36..6d6ee97603fe945747f65dabdd4a130edeb452cd 100644 (file)
--- a/src/superio/smsc/lpc47m10x/chip.h
+++ b/src/superio/smsc/lpc47m10x/chip.h
@@ -32,7 +32,7 @@ extern struct chip_operations superio_smsc_lpc47m10x_ops;
 #include <uart8250.h>
 
 struct superio_smsc_lpc47m10x_config {
 #include <uart8250.h>
 
 struct superio_smsc_lpc47m10x_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/smsc/lpc47m15x/chip.h b/src/superio/smsc/lpc47m15x/chip.h
index 27031f21b2a5effebf67fabca216a030fbba4bcb..57aba06dd81663bdf9e65517761b0a56492e98fb 100644 (file)
--- a/src/superio/smsc/lpc47m15x/chip.h
+++ b/src/superio/smsc/lpc47m15x/chip.h
@@ -27,7 +27,7 @@ extern struct chip_operations superio_smsc_lpc47m15x_ops;
 #include <uart8250.h>
 
 struct superio_smsc_lpc47m15x_config {
 #include <uart8250.h>
 
 struct superio_smsc_lpc47m15x_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/smsc/lpc47n217/chip.h b/src/superio/smsc/lpc47n217/chip.h
index c29031a85cc5730d51dd66c5f2a5b279fd3e8293..89a778c22c542f1f7dcc3a1783064dadf344c9ed 100644 (file)
--- a/src/superio/smsc/lpc47n217/chip.h
+++ b/src/superio/smsc/lpc47n217/chip.h
@@ -27,7 +27,7 @@ extern struct chip_operations superio_smsc_lpc47n217_ops;
 #include <uart8250.h>
 
 struct superio_smsc_lpc47n217_config {
 #include <uart8250.h>
 
 struct superio_smsc_lpc47n217_config {

-       
+

 };
 
 #endif
 };
 
 #endif

diff --git a/src/superio/smsc/lpc47n227/chip.h b/src/superio/smsc/lpc47n227/chip.h
index fa0269971ccfc6b3e30e20ea8af0e202cfef9e29..8b3a2c9dfcb3d9da9ee69a829205d03a5c64c86f 100644 (file)
--- a/src/superio/smsc/lpc47n227/chip.h
+++ b/src/superio/smsc/lpc47n227/chip.h
@@ -27,7 +27,7 @@
 extern struct chip_operations superio_smsc_lpc47n227_ops;
 
 struct superio_smsc_lpc47n227_config {
 extern struct chip_operations superio_smsc_lpc47n227_ops;
 
 struct superio_smsc_lpc47n227_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/smsc/lpc47n227/superio.c b/src/superio/smsc/lpc47n227/superio.c
index c7ffd69624863ed0b846f3a807745ad4f595fd2f..a241eb6d362f1bdc554da45fe60ce5fe2df022a7 100644 (file)
--- a/src/superio/smsc/lpc47n227/superio.c
+++ b/src/superio/smsc/lpc47n227/superio.c
@@ -85,7 +85,7 @@ static void enable_dev(device_t dev)
  *
  * NOTE: Cannot use pnp_set_resources() here because it assumes chip
  * support for logical devices, which the LPC47N227 doesn't have.
  *
  * NOTE: Cannot use pnp_set_resources() here because it assumes chip
  * support for logical devices, which the LPC47N227 doesn't have.

- * 
+ *

  * @param dev Pointer to structure describing a Super I/O device.
  */
 void lpc47n227_pnp_set_resources(device_t dev)
  * @param dev Pointer to structure describing a Super I/O device.
  */
 void lpc47n227_pnp_set_resources(device_t dev)

diff --git a/src/superio/smsc/sio10n268/chip.h b/src/superio/smsc/sio10n268/chip.h
index 32703bb394b088db3b9668d1e7608455f1dc9c0d..cd6e87bedee715bcb8113702832038e4f5a13438 100644 (file)
--- a/src/superio/smsc/sio10n268/chip.h
+++ b/src/superio/smsc/sio10n268/chip.h
@@ -27,7 +27,7 @@
 extern struct chip_operations superio_smsc_sio10n268_ops;
 
 struct superio_smsc_sio10n268_config {
 extern struct chip_operations superio_smsc_sio10n268_ops;
 
 struct superio_smsc_sio10n268_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/smsc/smscsuperio/chip.h b/src/superio/smsc/smscsuperio/chip.h
index ffe4b21ce309fdda1dd1cb6ba333a5f022d1b9c3..86f93be58d5e1836db63e75d9d7c5d59b6977047 100644 (file)
--- a/src/superio/smsc/smscsuperio/chip.h
+++ b/src/superio/smsc/smscsuperio/chip.h
@@ -28,7 +28,7 @@
 extern struct chip_operations superio_smsc_smscsuperio_ops;
 
 struct superio_smsc_smscsuperio_config {
 extern struct chip_operations superio_smsc_smscsuperio_ops;
 
 struct superio_smsc_smscsuperio_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/via/vt1211/chip.h b/src/superio/via/vt1211/chip.h
index 2154996a44ca87abf80254ca4a92d11a39818b90..3fcd6ae1b19f56f3c8896ff5f754908b45642d56 100644 (file)
--- a/src/superio/via/vt1211/chip.h
+++ b/src/superio/via/vt1211/chip.h
@@ -26,7 +26,7 @@
 extern struct chip_operations superio_via_vt1211_ops;
 
 struct superio_via_vt1211_config {
 extern struct chip_operations superio_via_vt1211_ops;
 
 struct superio_via_vt1211_config {

-       
+

 };
 
 #endif
 };
 
 #endif

diff --git a/src/superio/winbond/w83627dhg/chip.h b/src/superio/winbond/w83627dhg/chip.h
index 51c56e892bb99b1d80a4ac1332637c7247b9ffbb..b516aacad03faf55ab2e2697ccf4326d20c40dc4 100644 (file)
--- a/src/superio/winbond/w83627dhg/chip.h
+++ b/src/superio/winbond/w83627dhg/chip.h
@@ -27,7 +27,7 @@
 extern struct chip_operations superio_winbond_w83627dhg_ops;
 
 struct superio_winbond_w83627dhg_config {
 extern struct chip_operations superio_winbond_w83627dhg_ops;
 
 struct superio_winbond_w83627dhg_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/winbond/w83627ehg/chip.h b/src/superio/winbond/w83627ehg/chip.h
index f3fe8ce9e2aa68dc1856fdd58b1b689c7fbe6aad..a16135dc0e20d061c1be5c335525a5362f88785f 100644 (file)
--- a/src/superio/winbond/w83627ehg/chip.h
+++ b/src/superio/winbond/w83627ehg/chip.h
@@ -28,7 +28,7 @@
 extern struct chip_operations superio_winbond_w83627ehg_ops;
 
 struct superio_winbond_w83627ehg_config {
 extern struct chip_operations superio_winbond_w83627ehg_ops;
 
 struct superio_winbond_w83627ehg_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/winbond/w83627hf/chip.h b/src/superio/winbond/w83627hf/chip.h
index 14793ddbfe8e5634a441a6b70eb32e4498c0c1d8..64d9920464ca319fb445922525466c579adbaf9f 100644 (file)
--- a/src/superio/winbond/w83627hf/chip.h
+++ b/src/superio/winbond/w83627hf/chip.h
@@ -29,7 +29,7 @@
 extern struct chip_operations superio_winbond_w83627hf_ops;
 
 struct superio_winbond_w83627hf_config {
 extern struct chip_operations superio_winbond_w83627hf_ops;
 
 struct superio_winbond_w83627hf_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/winbond/w83627thg/chip.h b/src/superio/winbond/w83627thg/chip.h
index 8da6954b906e5e5188cb684e6b4cca3b9e4d164b..ce064856656f446c2bd83d3d1148c3c93456ee4c 100644 (file)
--- a/src/superio/winbond/w83627thg/chip.h
+++ b/src/superio/winbond/w83627thg/chip.h
@@ -29,7 +29,7 @@
 extern struct chip_operations superio_winbond_w83627thg_ops;
 
 struct superio_winbond_w83627thg_config {
 extern struct chip_operations superio_winbond_w83627thg_ops;
 
 struct superio_winbond_w83627thg_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/winbond/w83627uhg/chip.h b/src/superio/winbond/w83627uhg/chip.h
index ffabfa5fed6c1c913fa843de22deeb0af98bbc8d..2802382ab9c340bfa5a89a1733592dc3bebf4f9e 100644 (file)
--- a/src/superio/winbond/w83627uhg/chip.h
+++ b/src/superio/winbond/w83627uhg/chip.h
@@ -27,7 +27,7 @@
 extern struct chip_operations superio_winbond_w83627uhg_ops;
 
 struct superio_winbond_w83627uhg_config {
 extern struct chip_operations superio_winbond_w83627uhg_ops;
 
 struct superio_winbond_w83627uhg_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/winbond/w83697hf/chip.h b/src/superio/winbond/w83697hf/chip.h
index dd54a525ca5c592bbafb8a7e49c9f4127397721e..1a1cbcc038c07b253ec79a36906d055d5749f81b 100644 (file)
--- a/src/superio/winbond/w83697hf/chip.h
+++ b/src/superio/winbond/w83697hf/chip.h
@@ -26,7 +26,7 @@
 extern struct chip_operations superio_winbond_w83697hf_ops;
 
 struct superio_winbond_w83697hf_config {
 extern struct chip_operations superio_winbond_w83697hf_ops;
 
 struct superio_winbond_w83697hf_config {

-       
+

 };
 
 #endif
 };
 
 #endif

diff --git a/src/superio/winbond/w83977f/chip.h b/src/superio/winbond/w83977f/chip.h
index 1c126971dea364128286efe28079df2127414dcb..aacb00918c312aece7ad484ffda63cb84441542d 100644 (file)
--- a/src/superio/winbond/w83977f/chip.h
+++ b/src/superio/winbond/w83977f/chip.h
@@ -27,7 +27,7 @@
 extern struct chip_operations superio_winbond_w83977f_ops;
 
 struct superio_winbond_w83977f_config {
 extern struct chip_operations superio_winbond_w83977f_ops;
 
 struct superio_winbond_w83977f_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/src/superio/winbond/w83977tf/chip.h b/src/superio/winbond/w83977tf/chip.h
index cc24fc0e6239f9273df6f18f664d86556bcf7384..80c4afd856b70cf7d971140632d046b08ab13c21 100644 (file)
--- a/src/superio/winbond/w83977tf/chip.h
+++ b/src/superio/winbond/w83977tf/chip.h
@@ -29,7 +29,7 @@
 extern struct chip_operations superio_winbond_w83977tf_ops;
 
 struct superio_winbond_w83977tf_config {
 extern struct chip_operations superio_winbond_w83977tf_ops;
 
 struct superio_winbond_w83977tf_config {

-       
+

        struct pc_keyboard keyboard;
 };
 
        struct pc_keyboard keyboard;
 };
 

diff --git a/util/cbfstool/cbfs-mkstage.c b/util/cbfstool/cbfs-mkstage.c
index c9163ef6cf585237c0a6b346914a64f386de5a37..6b80a37dc521a821a84d1382e34f6080d1fa214d 100644 (file)
--- a/util/cbfstool/cbfs-mkstage.c
+++ b/util/cbfstool/cbfs-mkstage.c
@@ -36,7 +36,7 @@ unsigned int idemp(unsigned int x)
        return x;
 }
 
        return x;
 }
 

-/* This is a wrapper around the swab32() macro to make it 
+/* This is a wrapper around the swab32() macro to make it

  * usable for the current implementation of parse_elf_to_stage()
  */
 static unsigned int swap32(unsigned int x)
  * usable for the current implementation of parse_elf_to_stage()
  */
 static unsigned int swap32(unsigned int x)

diff --git a/util/ectool/ec.c b/util/ectool/ec.c
index 5bff0c2655aa4340c298eae8b4ccad925b832913..0f5b891d54efa77fbb7d34c274f8f13f37e0f0f0 100644 (file)
--- a/util/ectool/ec.c
+++ b/util/ectool/ec.c
@@ -126,7 +126,7 @@ int ec_ext_write(uint16_t addr, uint8_t data)
        send_ec_data(addr & 0xff);
        send_ec_command(WX_EC);
        send_ec_data(addr >> 8);
        send_ec_data(addr & 0xff);
        send_ec_command(WX_EC);
        send_ec_data(addr >> 8);

-    
+

        return send_ec_data(data);
 }
 
        return send_ec_data(data);
 }
 

diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index 204c4492dcbdd4624534974217ecdf5bea6aca7a..eb91b2c4329c50c489424c6af7812ff8ade6342b 100644 (file)
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -311,7 +311,7 @@ void inject_region(char *filename, char *image, int size, int region_type,
                exit(EXIT_FAILURE);
        frba_t *frba =
            (frba_t *) (image + (((fdb->flmap0 >> 16) & 0xff) << 4));
                exit(EXIT_FAILURE);
        frba_t *frba =
            (frba_t *) (image + (((fdb->flmap0 >> 16) & 0xff) << 4));

-       
+

        region_t region = get_region(frba, region_type);
        if (region.size <= 0xfff) {
                fprintf(stderr, "Region %s is disabled in target. Not injecting.\n",
        region_t region = get_region(frba, region_type);
        if (region.size <= 0xfff) {
                fprintf(stderr, "Region %s is disabled in target. Not injecting.\n",

diff --git a/util/nvramtool/accessors/cmos-hw-unix.c b/util/nvramtool/accessors/cmos-hw-unix.c
index 6d42cb57ee2914fc5f9e78895fd0b626d04fe7da..9a39a0c6861cc451a30a38eda4386b7d35013799 100644 (file)
--- a/util/nvramtool/accessors/cmos-hw-unix.c
+++ b/util/nvramtool/accessors/cmos-hw-unix.c
@@ -18,7 +18,7 @@
 #include <DirectHW/DirectHW.h>
 #endif
 #if defined(__NetBSD__)
 #include <DirectHW/DirectHW.h>
 #endif
 #if defined(__NetBSD__)

-#if defined(__i386__) || defined(__x86_64__) 
+#if defined(__i386__) || defined(__x86_64__)

 #include <machine/sysarch.h>
 
 static inline void outb(uint8_t value, uint16_t port)
 #include <machine/sysarch.h>
 
 static inline void outb(uint8_t value, uint16_t port)

diff --git a/util/nvramtool/cli/nvramtool.c b/util/nvramtool/cli/nvramtool.c
index bc929da698671b541a7ff3a881b3d5ed03ee4094..11a1a702afcf1a754330c9153efcd5e9986ee3bc 100644 (file)
--- a/util/nvramtool/cli/nvramtool.c
+++ b/util/nvramtool/cli/nvramtool.c
@@ -140,13 +140,13 @@ int main(int argc, char *argv[])
                        fprintf(stderr, "Couldn't stat '%s'\n", nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].param);
                        exit(1);
                }
                        fprintf(stderr, "Couldn't stat '%s'\n", nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].param);
                        exit(1);
                }

-               
+

                if (fd_stat.st_size < 128) {
                        lseek(fd, 127, SEEK_SET);
                        write(fd, "\0", 1);
                        fsync(fd);
                }
                if (fd_stat.st_size < 128) {
                        lseek(fd, 127, SEEK_SET);
                        write(fd, "\0", 1);
                        fsync(fd);
                }

-               
+

                cmos_default = mmap(NULL, 128, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
                if (cmos_default == MAP_FAILED) {
                        fprintf(stderr, "Couldn't map '%s'\n", nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].param);
                cmos_default = mmap(NULL, 128, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
                if (cmos_default == MAP_FAILED) {
                        fprintf(stderr, "Couldn't map '%s'\n", nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].param);

diff --git a/util/sconfig/main.c b/util/sconfig/main.c
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h
old mode 100755 (executable)
new mode 100644 (file)

diff --git a/util/superiotool/amd.c b/util/superiotool/amd.c
index 1c035234b2a0ebe75ae950ec15d697697f2f9fc4..5041ba87c05055ca4e13103e396c813e41e1c47b 100644 (file)
--- a/util/superiotool/amd.c
+++ b/util/superiotool/amd.c
@@ -90,7 +90,7 @@ uint16_t detect_ec(void)
                return 0;
 
        ec_port = pci_read_word(dev, 0xa4);
                return 0;
 
        ec_port = pci_read_word(dev, 0xa4);

-       
+

        if (!(ec_port & 0x1))
                return 0;
 
        if (!(ec_port & 0x1))
                return 0;
 

diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c
index 72bcad95466274242527c467cb521bd5e7e780b5..6a1a75c0c52a4bfa6fb37add9b760ad02538b538 100644 (file)
--- a/util/superiotool/nuvoton.c
+++ b/util/superiotool/nuvoton.c
@@ -257,7 +257,7 @@ void probe_idregs_nuvoton(uint16_t port)
                chip_found = 1;
                dump_superio("Nuvoton", reg_table, port, chip_id, LDN_SEL);
                return;
                chip_found = 1;
                dump_superio("Nuvoton", reg_table, port, chip_id, LDN_SEL);
                return;

-       } 
+       }

 
        if (verbose)
                printf(NOTFOUND "chip_id=0x%04x\n", chip_id);
 
        if (verbose)
                printf(NOTFOUND "chip_id=0x%04x\n", chip_id);