2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Google Inc
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <arch/romcc_io.h>
24 #include <device/pci_def.h>
27 PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_BUS, \
28 CONFIG_OXFORD_OXPCIE_BRIDGE_DEVICE, \
29 CONFIG_OXFORD_OXPCIE_BRIDGE_FUNCTION)
31 #define OXPCIE_DEVICE \
32 PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0)
34 void oxford_init(void)
38 /* First we reset the secondary bus */
39 reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL);
40 reg16 |= (1 << 6); /* SRESET */
41 pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16);
43 /* Assume we don't have to wait here forever */
45 /* Read back and clear reset bit. */
46 reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL);
47 reg16 &= ~(1 << 6); /* SRESET */
48 pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16);
50 /* Set up subordinate bus number */
51 pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS, 0x00);
52 pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS, 0x00);
53 pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS,
54 CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE);
55 pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS,
56 CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE);
58 /* Memory window for the OXPCIe952 card */
59 // XXX is the calculation of base and limit corect?
60 pci_write_config32(PCIE_BRIDGE, PCI_MEMORY_BASE,
61 ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS & 0xffff0000) |
62 ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS >> 16) & 0xff00)));
64 /* Enable memory access through bridge */
65 reg16 = pci_read_config16(PCIE_BRIDGE, PCI_COMMAND);
66 reg16 |= PCI_COMMAND_MEMORY;
67 pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16);
69 // FIXME Add a timeout or this will hang forever if
70 // no device is in the slot.
72 while ((id == 0) || (id == 0xffffffff))
73 id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID);
75 /* Setup base address on device */
76 pci_write_config32(OXPCIE_DEVICE, PCI_BASE_ADDRESS_0,
77 CONFIG_OXFORD_OXPCIE_BASE_ADDRESS);
79 /* Enable memory on device */
80 reg16 = pci_read_config16(OXPCIE_DEVICE, PCI_COMMAND);
81 reg16 |= PCI_COMMAND_MEMORY;
82 pci_write_config16(OXPCIE_DEVICE, PCI_COMMAND, reg16);
84 /* Now the UART initialization */
85 u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000;
87 uart8250_mem_init(uart0_base, (4000000 / CONFIG_TTYS0_BAUD));