2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 /*----------------------------------------------------------------------------------------
21 * M O D U L E S U S E D
22 *----------------------------------------------------------------------------------------
27 #include "agesawrapper.h"
28 #include "BiosCallOuts.h"
29 #include "cpuRegisters.h"
30 #include "cpuCacheInit.h"
31 #include "cpuApicUtilities.h"
32 #include "cpuEarlyInit.h"
33 #include "cpuLateInit.h"
34 #include "Dispatcher.h"
35 #include "cpuCacheInit.h"
37 #include "PlatformGnbPcieComplex.h"
41 #define FILECODE UNASSIGNED_FILE_FILECODE
43 /*----------------------------------------------------------------------------------------
44 * D E F I N I T I O N S A N D M A C R O S
45 *----------------------------------------------------------------------------------------
48 /* ACPI table pointers returned by AmdInitLate */
49 VOID *DmiTable = NULL;
50 VOID *AcpiPstate = NULL;
51 VOID *AcpiSrat = NULL;
52 VOID *AcpiSlit = NULL;
54 VOID *AcpiWheaMce = NULL;
55 VOID *AcpiWheaCmc = NULL;
56 VOID *AcpiAlib = NULL;
59 /*----------------------------------------------------------------------------------------
60 * T Y P E D E F S A N D S T R U C T U R E S
61 *----------------------------------------------------------------------------------------
64 /*----------------------------------------------------------------------------------------
65 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
66 *----------------------------------------------------------------------------------------
69 /*----------------------------------------------------------------------------------------
70 * E X P O R T E D F U N C T I O N S
71 *----------------------------------------------------------------------------------------
74 /*---------------------------------------------------------------------------------------
75 * L O C A L F U N C T I O N S
76 *---------------------------------------------------------------------------------------
96 ClearAllSmiEnableInPmio (
102 /* Read SB Power Management Area */
109 WriteIo8 (SB_PM_INDEX_PORT, IndexValue);
110 *DataValue = ReadIo8 (SB_PM_DATA_PORT);
114 /* Write ATI SB Power Management Area */
121 WriteIo8 (SB_PM_INDEX_PORT, IndexValue);
122 WriteIo8 (SB_PM_DATA_PORT, DataValue);
126 /* Clear any SMI status or wake status left over from boot. */
136 /* Read the ACPI registers */
137 Pm1Sts = ReadIo16 (PmBase + R_SB_ACPI_PM1_STATUS);
138 Pm1Cnt = ReadIo32 (PmBase + R_SB_ACPI_PM1_STATUS);
139 Gpe0Sts = ReadIo32 (PmBase + R_SB_ACPI_EVENT_STATUS);
141 /* Clear any SMI or wake state from the boot */
142 Pm1Sts &= B_PWR_BTN_STATUS + B_WAKEUP_STATUS;
143 Pm1Cnt &= ~(B_SCI_EN);
146 WriteIo16 (PmBase + R_SB_ACPI_PM1_STATUS, Pm1Sts);
147 WriteIo32 (PmBase + R_SB_ACPI_PM_CONTROL, Pm1Cnt);
148 WriteIo32 (PmBase + R_SB_ACPI_EVENT_STATUS, Gpe0Sts);
151 /* Clear all SMI enable bit in PMIO register */
153 ClearAllSmiEnableInPmio (
162 /* Get SB900 MMIO Base (AcpiMmioAddr) */
163 ReadAmdSbPmr (SB_PMIOA_REG24 + 3, &Data8);
165 ReadAmdSbPmr (SB_PMIOA_REG24 + 2, &Data8);
167 AcpiMmioAddr = (UINT32)Data16 << 16;
168 SmiMmioAddr = AcpiMmioAddr + SMI_BASE;
170 Mmio32 (SmiMmioAddr, 0xA0) = 0x0;
171 Mmio32 (SmiMmioAddr, 0xA4) = 0x0;
172 Mmio32 (SmiMmioAddr, 0xA8) = 0x0;
173 Mmio32 (SmiMmioAddr, 0xAC) = 0x0;
174 Mmio32 (SmiMmioAddr, 0xB0) = 0x0;
175 Mmio32 (SmiMmioAddr, 0xB4) = 0x0;
176 Mmio32 (SmiMmioAddr, 0xB8) = 0x0;
177 Mmio32 (SmiMmioAddr, 0xBC) = 0x0;
178 Mmio32 (SmiMmioAddr, 0xC0) = 0x0;
179 Mmio32 (SmiMmioAddr, 0xC4) = 0x0;
183 agesawrapper_amdinitcpuio (
191 AMD_CONFIG_PARAMS StdHeader;
193 /* Enable MMIO on AMD CPU Address Map Controller */
195 /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
196 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
197 PciData = 0x00000B00;
198 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
199 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
200 PciData = 0x00000A03;
201 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
203 /* Set TOM-DFFFFFFF to Node0 Link0. */
204 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
205 PciData = 0x00DFFF00;
206 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
207 LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
208 MsrReg = (MsrReg >> 8) | 3;
209 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
210 PciData = (UINT32)MsrReg;
211 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
212 /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
213 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC);
214 PciData = 0x00FFFF00 | 0x80;
215 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
216 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8);
217 PciData = (PCIE_BASE_ADDRESS >> 8) | 03;
218 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
219 /* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */
220 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
221 //- PciData = 0x0000F000;
222 PciData = 0x00FFF000;
223 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
224 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
225 PciData = 0x00000013;
226 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
227 Status = AGESA_SUCCESS;
228 return (UINT32)Status;
232 agesawrapper_amdinitmmio (
240 AMD_CONFIG_PARAMS StdHeader;
243 Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
244 Address MSR register.
246 MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1;
247 LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
250 Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
252 LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
253 MsrReg = MsrReg | 0x0000400000000000ull;
254 LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
256 /* Set Ontario Link Data */
257 //- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
258 //- PciData = 0x01308002;
259 //- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
260 //- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
261 //- PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
262 //- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
264 /* Enable Non-Post Memory in CPU */
265 PciData = ((CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x3FF80);
266 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x018, 0x01, 0xA4);
267 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
269 PciData = ((CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x03);
270 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x018, 0x01, 0xA0);
271 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
273 /* Enable memory access */
274 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x04);
275 LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader);
278 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x04);
279 LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);
281 /* Set ROM cache onto WP to decrease post time */
282 MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull;
283 LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
284 MsrReg = (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800ull;
285 LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
287 /* Clear all pending SMI. On S3 clear power button enable so it wll not generate an SMI */
288 //- ClearSBSmiAndWake (SB_ACPI_BASE_ADDRESS);
289 //- ClearAllSmiEnableInPmio ();
291 Status = AGESA_SUCCESS;
292 return (UINT32)Status;
296 agesawrapper_amdinitreset (
301 AMD_INTERFACE_PARAMS AmdParamStruct;
302 AMD_RESET_PARAMS AmdResetParams;
304 LibAmdMemFill (&AmdParamStruct,
306 sizeof (AMD_INTERFACE_PARAMS),
307 &(AmdParamStruct.StdHeader));
310 LibAmdMemFill (&AmdResetParams,
312 sizeof (AMD_RESET_PARAMS),
313 &(AmdResetParams.StdHeader));
315 AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
316 AmdParamStruct.AllocationMethod = ByHost;
317 AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
318 AmdParamStruct.NewStructPtr = &AmdResetParams;
319 AmdParamStruct.StdHeader.AltImageBasePtr = 0;
320 AmdParamStruct.StdHeader.CalloutPtr = NULL;
321 AmdParamStruct.StdHeader.Func = 0;
322 AmdParamStruct.StdHeader.ImageBasePtr = 0;
323 AmdCreateStruct (&AmdParamStruct);
324 AmdResetParams.HtConfig.Depth = 0;
326 status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
327 if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
328 AmdReleaseStruct (&AmdParamStruct);
329 return (UINT32)status;
333 agesawrapper_amdinitearly (
338 AMD_INTERFACE_PARAMS AmdParamStruct;
339 AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
341 LibAmdMemFill (&AmdParamStruct,
343 sizeof (AMD_INTERFACE_PARAMS),
344 &(AmdParamStruct.StdHeader));
346 AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
347 AmdParamStruct.AllocationMethod = PreMemHeap;
348 AmdParamStruct.StdHeader.AltImageBasePtr = 0;
349 AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
350 AmdParamStruct.StdHeader.Func = 0;
351 AmdParamStruct.StdHeader.ImageBasePtr = 0;
352 AmdCreateStruct (&AmdParamStruct);
354 AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
355 OemCustomizeInitEarly (AmdEarlyParamsPtr);
357 status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
358 if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
359 AmdReleaseStruct (&AmdParamStruct);
361 return (UINT32)status;
365 agesawrapper_amdinitpost (
372 AMD_INTERFACE_PARAMS AmdParamStruct;
373 BIOS_HEAP_MANAGER *BiosManagerPtr;
375 LibAmdMemFill (&AmdParamStruct,
377 sizeof (AMD_INTERFACE_PARAMS),
378 &(AmdParamStruct.StdHeader));
380 AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
381 AmdParamStruct.AllocationMethod = PreMemHeap;
382 AmdParamStruct.StdHeader.AltImageBasePtr = 0;
383 AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
384 AmdParamStruct.StdHeader.Func = 0;
385 AmdParamStruct.StdHeader.ImageBasePtr = 0;
387 AmdCreateStruct (&AmdParamStruct);
388 status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
389 if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
390 AmdReleaseStruct (&AmdParamStruct);
392 /* Initialize heap space */
393 BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
395 HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
396 for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
398 *HeadPtr = 0x00000000;
401 BiosManagerPtr->StartOfAllocatedNodes = 0;
402 BiosManagerPtr->StartOfFreedNodes = 0;
404 return (UINT32)status;
408 agesawrapper_amdinitenv (
413 AMD_INTERFACE_PARAMS AmdParamStruct;
415 LibAmdMemFill (&AmdParamStruct,
417 sizeof (AMD_INTERFACE_PARAMS),
418 &(AmdParamStruct.StdHeader));
420 AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
421 AmdParamStruct.AllocationMethod = PostMemDram;
422 AmdParamStruct.StdHeader.AltImageBasePtr = 0;
423 AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
424 AmdParamStruct.StdHeader.Func = 0;
425 AmdParamStruct.StdHeader.ImageBasePtr = 0;
426 AmdCreateStruct (&AmdParamStruct);
427 status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
428 if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
429 AmdReleaseStruct (&AmdParamStruct);
431 return (UINT32)status;
435 agesawrapper_getlateinitptr (
463 agesawrapper_amdinitmid (
468 AMD_INTERFACE_PARAMS AmdParamStruct;
470 /* Enable MMIO on AMD CPU Address Map Controller */
471 agesawrapper_amdinitcpuio ();
473 LibAmdMemFill (&AmdParamStruct,
475 sizeof (AMD_INTERFACE_PARAMS),
476 &(AmdParamStruct.StdHeader));
478 AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
479 AmdParamStruct.AllocationMethod = PostMemDram;
480 AmdParamStruct.StdHeader.AltImageBasePtr = 0;
481 AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
482 AmdParamStruct.StdHeader.Func = 0;
483 AmdParamStruct.StdHeader.ImageBasePtr = 0;
485 AmdCreateStruct (&AmdParamStruct);
487 status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
488 if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
489 AmdReleaseStruct (&AmdParamStruct);
491 return (UINT32)status;
495 agesawrapper_amdinitlate (
500 AMD_LATE_PARAMS AmdLateParams;
502 LibAmdMemFill (&AmdLateParams,
504 sizeof (AMD_LATE_PARAMS),
505 &(AmdLateParams.StdHeader));
507 AmdLateParams.StdHeader.AltImageBasePtr = 0;
508 AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
509 AmdLateParams.StdHeader.Func = 0;
510 AmdLateParams.StdHeader.ImageBasePtr = 0;
512 Status = AmdInitLate (&AmdLateParams);
513 if (Status != AGESA_SUCCESS) {
514 agesawrapper_amdreadeventlog();
515 ASSERT(Status == AGESA_SUCCESS);
518 DmiTable = AmdLateParams.DmiTable;
519 AcpiPstate = AmdLateParams.AcpiPState;
520 AcpiSrat = AmdLateParams.AcpiSrat;
521 AcpiSlit = AmdLateParams.AcpiSlit;
523 AcpiWheaMce = AmdLateParams.AcpiWheaMce;
524 AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
525 AcpiAlib = AmdLateParams.AcpiAlib;
527 return (UINT32)Status;
531 agesawrapper_amdlaterunaptask (
537 AP_EXE_PARAMS ApExeParams;
539 LibAmdMemFill (&ApExeParams,
541 sizeof (AP_EXE_PARAMS),
542 &(ApExeParams.StdHeader));
544 ApExeParams.StdHeader.AltImageBasePtr = 0;
545 ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
546 ApExeParams.StdHeader.Func = 0;
547 ApExeParams.StdHeader.ImageBasePtr = 0;
549 Status = AmdLateRunApTask (&ApExeParams);
550 if (Status != AGESA_SUCCESS) {
551 agesawrapper_amdreadeventlog();
552 ASSERT(Status == AGESA_SUCCESS);
555 return (UINT32)Status;
559 agesawrapper_amdreadeventlog (
564 EVENT_PARAMS AmdEventParams;
566 LibAmdMemFill (&AmdEventParams,
568 sizeof (EVENT_PARAMS),
569 &(AmdEventParams.StdHeader));
571 AmdEventParams.StdHeader.AltImageBasePtr = 0;
572 AmdEventParams.StdHeader.CalloutPtr = NULL;
573 AmdEventParams.StdHeader.Func = 0;
574 AmdEventParams.StdHeader.ImageBasePtr = 0;
575 Status = AmdReadEventLog (&AmdEventParams);
576 while (AmdEventParams.EventClass != 0) {
577 printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
578 printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
579 printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
580 Status = AmdReadEventLog (&AmdEventParams);
583 return (UINT32)Status;