src/drivers/ati/ragexl/xlinit.c

   1 /*
   2  *  ATI Rage XL Initialization. Support for Xpert98 and Victoria
   3  *  PCI cards.
   4  *
   5  *  Copyright (C) 2002 MontaVista Software Inc.
   6  *  Author: MontaVista Software, Inc.
   7  *              stevel@mvista.com or source@mvista.com
   8  *  Copyright (C) 2004 Tyan Computer.
   9  *  Auther: Yinghai Lu   yhlu@tyan.com
  10  *         move to coreboot
  11  * This code is distributed without warranty under the GPL v2 (see COPYING) *
  12  */
  13 #include <delay.h>
  14 #include <stdlib.h>
  15 #include <string.h>
  16 #include <arch/io.h>
  17
  18 #include <console/console.h>
  19 #include <device/device.h>
  20 #include <device/pci.h>
  21 #include <device/pci_ids.h>
  22 #include <device/pci_ops.h>
  23
  24 // FIXME BTEXT console within coreboot has been obsoleted
  25 // and will go away. The BTEXT code in this file should be
  26 // fixed to export a framebuffer console through the coreboot
  27 // table (and possibly make it available for bootsplash use)
  28 // Hence do only remove this if you fix the code.
  29 #define CONFIG_CONSOLE_BTEXT 0
  30
  31 #if CONFIG_CONSOLE_BTEXT==1
  32
  33 #define PLL_CRTC_DECODE 0
  34 #define SUPPORT_8_BPP_ABOVE 0
  35
  36 #include "fb.h"
  37 #include "fbcon.h"
  38
  39 struct aty_cmap_regs {
  40         u8 windex;
  41         u8 lut;
  42         u8 mask;
  43         u8 rindex;
  44         u8 cntl;
  45 };
  46
  47 #include <console/btext.h>
  48
  49 #endif /*CONFIG_CONSOLE_BTEXT*/
  50
  51 #include "mach64.h"
  52
  53 #include "atyfb.h"
  54
  55 #include "mach64_ct.c"
  56
  57 #define MPLL_GAIN       0xad
  58 #define VPLL_GAIN       0xd5
  59
  60 #define HAS_VICTORIA 0
  61
  62 enum {
  63 #if HAS_VICTORIA==1
  64         VICTORIA = 0,
  65         XPERT98,
  66 #else
  67         XPERT98=0,
  68 #endif
  69         NUM_XL_CARDS
  70 };
  71
  72 //static struct aty_pll_ops aty_pll_ct;
  73
  74 #define DEFAULT_CARD XPERT98
  75 static int xl_card = DEFAULT_CARD;
  76
  77 static const struct xl_card_cfg_t {
  78         int ref_crystal; // 10^4 Hz
  79         int mem_type;
  80         int mem_size;
  81         u32 mem_cntl;
  82         u32 ext_mem_cntl;
  83         u32 mem_addr_config;
  84         u32 bus_cntl;
  85         u32 dac_cntl;
  86         u32 hw_debug;
  87         u32 custom_macro_cntl;
  88         u8  dll2_cntl;
  89         u8  pll_yclk_cntl;
  90 } card_cfg[NUM_XL_CARDS] = {
  91 #if HAS_VICTORIA==1
  92         // VICTORIA
  93         {       2700, SDRAM, 0x800000,
  94                 0x10757A3B, 0x64000C81, 0x00110202, 0x7b33A040,
  95                 0x82010102, 0x48803800, 0x005E0179,
  96                 0x50, 0x25
  97         },
  98 #endif
  99         // XPERT98
 100         {       1432,  WRAM, 0x800000,
 101                 0x00165A2B, 0xE0000CF1, 0x00200213, 0x7333A001,
 102                 0x8000000A, 0x48833800, 0x007F0779,
 103                 0x10, 0x19
 104         }
 105 };
 106
 107 typedef struct {
 108         u8 lcd_reg;
 109         u32 val;
 110 } lcd_tbl_t;
 111
 112 static const lcd_tbl_t lcd_tbl[] = {
 113         { 0x01, 0x000520C0 },
 114         { 0x08, 0x02000408 },
 115         { 0x03, 0x00000F00 },
 116         { 0x00, 0x00000000 },
 117         { 0x02, 0x00000000 },
 118         { 0x04, 0x00000000 },
 119         { 0x05, 0x00000000 },
 120         { 0x06, 0x00000000 },
 121         { 0x33, 0x00000000 },
 122         { 0x34, 0x00000000 },
 123         { 0x35, 0x00000000 },
 124         { 0x36, 0x00000000 },
 125         { 0x37, 0x00000000 }
 126 };
 127
 128 static inline u32 aty_ld_lcd(u8 lcd_reg, struct fb_info_aty *info)
 129 {
 130         aty_st_8(LCD_INDEX, lcd_reg, info);
 131         return aty_ld_le32(LCD_DATA, info);
 132 }
 133
 134 static inline void aty_st_lcd(u8 lcd_reg, u32 val,
 135                               struct fb_info_aty *info)
 136 {
 137         aty_st_8(LCD_INDEX, lcd_reg, info);
 138         aty_st_le32(LCD_DATA, val, info);
 139 }
 140
 141 static void reset_gui(struct fb_info_aty *info)
 142 {
 143         aty_st_8(GEN_TEST_CNTL+1, 0x01, info);
 144         aty_st_8(GEN_TEST_CNTL+1, 0x00, info);
 145         aty_st_8(GEN_TEST_CNTL+1, 0x02, info);
 146         mdelay(5);
 147 }
 148
 149
 150 static void reset_sdram(struct fb_info_aty *info)
 151 {
 152         u8 temp;
 153
 154         temp = aty_ld_8(EXT_MEM_CNTL, info);
 155         temp |= 0x02;
 156         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_SDRAM_RESET = 1b
 157         temp |= 0x08;
 158         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST    = 10b
 159         temp |= 0x0c;
 160         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST    = 11b
 161         mdelay(5);
 162         temp &= 0xf3;
 163         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST    = 00b
 164         temp &= 0xfd;
 165         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_SDRAM_REST  = 0b
 166         mdelay(5);
 167 }
 168
 169 static void init_dll(struct fb_info_aty *info)
 170 {
 171         // enable DLL
 172         aty_st_pll(PLL_GEN_CNTL,
 173                    aty_ld_pll(PLL_GEN_CNTL, info) & 0x7f,
 174                    info);
 175
 176         // reset DLL
 177         aty_st_pll(DLL_CNTL, 0x82, info);
 178         aty_st_pll(DLL_CNTL, 0xE2, info);
 179         mdelay(5);
 180         aty_st_pll(DLL_CNTL, 0x82, info);
 181         mdelay(6);
 182 }
 183
 184 static void reset_clocks(struct fb_info_aty *info, struct pll_ct *pll,
 185                          int hsync_enb)
 186 {
 187         reset_gui(info);
 188         aty_st_pll(MCLK_FB_DIV, pll->mclk_fb_div, info);
 189         aty_st_pll(SCLK_FB_DIV, pll->sclk_fb_div, info);
 190
 191         mdelay(15);
 192         init_dll(info);
 193         aty_st_8(GEN_TEST_CNTL+1, 0x00, info);
 194         mdelay(5);
 195         aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);
 196         mdelay(6);
 197         reset_sdram(info);
 198         aty_st_8(CRTC_GEN_CNTL+3,
 199                  hsync_enb ? 0x00 : 0x04, info);
 200
 201         aty_st_pll(SPLL_CNTL2, pll->spll_cntl2, info);
 202         aty_st_pll(PLL_GEN_CNTL, pll->pll_gen_cntl, info);
 203         aty_st_pll(PLL_VCLK_CNTL, pll->pll_vclk_cntl, info);
 204 }
 205
 206 static int atyfb_xl_init(struct fb_info_aty *info)
 207 {
 208         int i, err;
 209         u32 temp;
 210         union aty_pll pll;
 211         const struct xl_card_cfg_t * card = &card_cfg[xl_card];
 212
 213         aty_st_8(CONFIG_STAT0, 0x85, info);
 214         mdelay(10);
 215
 216         /*
 217          * The following needs to be set before the call
 218          * to var_to_pll() below. They'll be re-set again
 219          * to the same values in aty_init().
 220          */
 221         info->ref_clk_per = 100000000UL/card->ref_crystal;
 222         info->ram_type = card->mem_type;
 223         info->total_vram = card->mem_size;
 224 #if HAS_VICTORIA == 1
 225         if (xl_card == VICTORIA) {
 226                 // the MCLK, XCLK are 120MHz on victoria card
 227                 info->mclk_per = 1000000/120;
 228                 info->xclk_per = 1000000/120;
 229                 info->features &= ~M64F_MFB_TIMES_4;
 230         }
 231 #endif
 232
 233         /*
 234          * Calculate mclk and xclk dividers, etc. The passed
 235          * pixclock and bpp values don't matter yet, the vclk
 236          * isn't programmed until later.
 237          */
 238         if ((err = aty_var_to_pll_ct(info, 39726, 8, &pll))) return err;
 239 //        if ((err = aty_pll_ct.var_to_pll(info, 39726, 8, &pll))) return err;
 240
 241
 242         aty_st_pll(LVDS_CNTL0, 0x00, info);
 243         aty_st_pll(DLL2_CNTL, card->dll2_cntl, info);
 244         aty_st_pll(V2PLL_CNTL, 0x10, info);
 245         aty_st_pll(MPLL_CNTL, MPLL_GAIN, info);
 246         aty_st_pll(VPLL_CNTL, VPLL_GAIN, info);
 247         aty_st_pll(PLL_VCLK_CNTL, 0x00, info);
 248         aty_st_pll(VFC_CNTL, 0x1B, info);
 249         aty_st_pll(PLL_REF_DIV, pll.ct.pll_ref_div, info);
 250         aty_st_pll(PLL_EXT_CNTL, pll.ct.pll_ext_cntl, info);
 251         aty_st_pll(SPLL_CNTL2, 0x03, info);
 252         aty_st_pll(PLL_GEN_CNTL, 0x44, info);
 253
 254         reset_clocks(info, &pll.ct, 0);
 255         mdelay(10);
 256
 257         aty_st_pll(VCLK_POST_DIV, 0x03, info);
 258         aty_st_pll(VCLK0_FB_DIV, 0xDA, info);
 259         aty_st_pll(VCLK_POST_DIV, 0x0F, info);
 260         aty_st_pll(VCLK1_FB_DIV, 0xF5, info);
 261         aty_st_pll(VCLK_POST_DIV, 0x3F, info);
 262         aty_st_pll(PLL_EXT_CNTL, 0x40 | pll.ct.pll_ext_cntl, info);
 263         aty_st_pll(VCLK2_FB_DIV, 0x00, info);
 264         aty_st_pll(VCLK_POST_DIV, 0xFF, info);
 265         aty_st_pll(PLL_EXT_CNTL, 0xC0 | pll.ct.pll_ext_cntl, info);
 266         aty_st_pll(VCLK3_FB_DIV, 0x00, info);
 267
 268         aty_st_8(BUS_CNTL, 0x01, info);
 269         aty_st_le32(BUS_CNTL, card->bus_cntl | 0x08000000, info);
 270
 271         aty_st_le32(CRTC_GEN_CNTL, 0x04000200, info);
 272         aty_st_le16(CONFIG_STAT0, 0x0020, info);
 273         aty_st_le32(MEM_CNTL, 0x10151A33, info);
 274         aty_st_le32(EXT_MEM_CNTL, 0xE0000C01, info);
 275         aty_st_le16(CRTC_GEN_CNTL+2, 0x0000, info);
 276         aty_st_le32(DAC_CNTL, card->dac_cntl, info);
 277         aty_st_le16(GEN_TEST_CNTL, 0x0100, info);
 278         aty_st_le32(CUSTOM_MACRO_CNTL, 0x003C0171, info);
 279         aty_st_le32(MEM_BUF_CNTL, 0x00382848, info);
 280
 281         aty_st_le32(HW_DEBUG, card->hw_debug, info);
 282         aty_st_le16(MEM_ADDR_CONFIG, 0x0000, info);
 283         aty_st_le16(GP_IO+2, 0x0000, info);
 284         aty_st_le16(GEN_TEST_CNTL, 0x0000, info);
 285         aty_st_le16(EXT_DAC_REGS+2, 0x0000, info);
 286         aty_st_le32(CRTC_INT_CNTL, 0x00000000, info);
 287         aty_st_le32(TIMER_CONFIG, 0x00000000, info);
 288         aty_st_le32(0xEC, 0x00000000, info);
 289         aty_st_le32(0xFC, 0x00000000, info);
 290
 291         for (i=0; i<ARRAY_SIZE(lcd_tbl); i++) {
 292                 aty_st_lcd(lcd_tbl[i].lcd_reg, lcd_tbl[i].val, info);
 293         }
 294
 295         aty_st_le16(CONFIG_STAT0, 0x00A4, info);
 296         mdelay(10);
 297
 298         aty_st_8(BUS_CNTL+1, 0xA0, info);
 299         mdelay(10);
 300
 301         reset_clocks(info, &pll.ct, 1);
 302         mdelay(10);
 303
 304         // something about power management
 305         aty_st_8(LCD_INDEX, 0x08, info);
 306         aty_st_8(LCD_DATA, 0x0A, info);
 307         aty_st_8(LCD_INDEX, 0x08, info);
 308         aty_st_8(LCD_DATA+3, 0x02, info);
 309         aty_st_8(LCD_INDEX, 0x08, info);
 310         aty_st_8(LCD_DATA, 0x0B, info);
 311         mdelay(2);
 312
 313         // enable display requests, enable CRTC
 314         aty_st_8(CRTC_GEN_CNTL+3, 0x02, info);
 315         // disable display
 316         aty_st_8(CRTC_GEN_CNTL, 0x40, info);
 317         // disable display requests, disable CRTC
 318         aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);
 319         mdelay(10);
 320
 321         aty_st_pll(PLL_YCLK_CNTL, 0x25, info);
 322
 323         aty_st_le16(CUSTOM_MACRO_CNTL, 0x0179, info);
 324         aty_st_le16(CUSTOM_MACRO_CNTL+2, 0x005E, info);
 325         aty_st_le16(CUSTOM_MACRO_CNTL+2, card->custom_macro_cntl>>16, info);
 326         aty_st_8(CUSTOM_MACRO_CNTL+1,
 327                  (card->custom_macro_cntl>>8) & 0xff, info);
 328
 329         aty_st_le32(MEM_ADDR_CONFIG, card->mem_addr_config, info);
 330         aty_st_le32(MEM_CNTL, card->mem_cntl, info);
 331         aty_st_le32(EXT_MEM_CNTL, card->ext_mem_cntl, info);
 332
 333         aty_st_8(CONFIG_STAT0, 0xA0 | card->mem_type, info);
 334
 335         aty_st_pll(PLL_YCLK_CNTL, 0x01, info);
 336         mdelay(15);
 337         aty_st_pll(PLL_YCLK_CNTL, card->pll_yclk_cntl, info);
 338         mdelay(1);
 339
 340         reset_clocks(info, &pll.ct, 0);
 341         mdelay(50);
 342         reset_clocks(info, &pll.ct, 0);
 343         mdelay(50);
 344
 345         // enable extended register block
 346         aty_st_8(BUS_CNTL+3, 0x7B, info);
 347         mdelay(1);
 348         // disable extended register block
 349         aty_st_8(BUS_CNTL+3, 0x73, info);
 350
 351         aty_st_8(CONFIG_STAT0, 0x80 | card->mem_type, info);
 352
 353         // disable display requests, disable CRTC
 354         aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);
 355         // disable mapping registers in VGA aperture
 356         aty_st_8(CONFIG_CNTL, aty_ld_8(CONFIG_CNTL, info) & ~0x04, info);
 357         mdelay(50);
 358         // enable display requests, enable CRTC
 359         aty_st_8(CRTC_GEN_CNTL+3, 0x02, info);
 360
 361         // make GPIO's 14,15,16 all inputs
 362         aty_st_8(LCD_INDEX, 0x07, info);
 363         aty_st_8(LCD_DATA+3, 0x00, info);
 364
 365         // enable the display
 366         aty_st_8(CRTC_GEN_CNTL, 0x00, info);
 367         mdelay(17);
 368         // reset the memory controller
 369         aty_st_8(GEN_TEST_CNTL+1, 0x02, info);
 370         mdelay(15);
 371         aty_st_8(GEN_TEST_CNTL+1, 0x00, info);
 372         mdelay(30);
 373
 374         // enable extended register block
 375         aty_st_8(BUS_CNTL+3,
 376                  (u8)(aty_ld_8(BUS_CNTL+3, info) | 0x08),
 377                  info);
 378         // set FIFO size to 512 (PIO)
 379         aty_st_le32(GUI_CNTL,
 380                     aty_ld_le32(GUI_CNTL, info) & ~0x3,
 381                     info);
 382
 383         // enable CRT and disable lcd
 384         aty_st_8(LCD_INDEX, 0x01, info);
 385         temp = aty_ld_le32(LCD_DATA, info);
 386         temp = (temp | 0x01) & ~0x02;
 387         aty_st_le32(LCD_DATA, temp, info);
 388
 389         return 0;
 390 }
 391
 392 static char m64n_xl_33[] = "3D RAGE (XL PCI-33MHz)";
 393 static char m64n_xl_66[] = "3D RAGE (XL PCI-66MHz)";
 394
 395
 396 #if CONFIG_CONSOLE_BTEXT==1
 397 static void aty_set_crtc(const struct fb_info_aty *info,
 398                          const struct crtc *crtc);
 399 static int aty_var_to_crtc(const struct fb_info_aty *info,
 400                            const struct fb_var_screeninfo *var,
 401                            struct crtc *crtc);
 402 #if PLL_CRTC_DECODE==1
 403 static int aty_crtc_to_var(const struct crtc *crtc,
 404                            struct fb_var_screeninfo *var);
 405 #endif
 406
 407 static void atyfb_set_par(const struct atyfb_par *par,
 408                           struct fb_info_aty *info);
 409 static int atyfb_decode_var(const struct fb_var_screeninfo *var,
 410                             struct atyfb_par *par,
 411                             const struct fb_info_aty *info);
 412 #if PLL_CRTC_DECODE==1
 413 static int atyfb_encode_var(struct fb_var_screeninfo *var,
 414                             const struct atyfb_par *par,
 415                             const struct fb_info_aty *info);
 416 #endif
 417
 418 static void do_install_cmap(int con, struct fb_info_aty *info);
 419
 420 #if 0
 421 static u32 default_vram  = 0;
 422 #endif
 423
 424 unsigned char color_table[] = { 0, 4, 2, 6, 1, 5, 3, 7,
 425                                        8,12,10,14, 9,13,11,15 };
 426 #if 0
 427 /* the default colour table, for VGA+ colour systems */
 428 int default_red[] = {0x00,0xaa,0x00,0xaa,0x00,0xaa,0x00,0xaa,
 429     0x55,0xff,0x55,0xff,0x55,0xff,0x55,0xff};
 430 int default_grn[] = {0x00,0x00,0xaa,0x55,0x00,0x00,0xaa,0xaa,
 431     0x55,0x55,0xff,0xff,0x55,0x55,0xff,0xff};
 432 int default_blu[] = {0x00,0x00,0x00,0x00,0xaa,0xaa,0xaa,0xaa,
 433     0x55,0x55,0x55,0x55,0xff,0xff,0xff,0xff};
 434 #endif
 435
 436 struct fb_var_screeninfo default_var = {
 437         /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
 438         640, 480, 640, 480, 0, 0, 8, 0,
 439         {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
 440         0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
 441         0, FB_VMODE_NONINTERLACED
 442 };
 443
 444 #endif /*CONFIG_CONSOLE_BTEXT*/
 445
 446 static struct {
 447         u16 pci_id, chip_type;
 448         u8 rev_mask, rev_val;
 449         const char *name;
 450         int pll, mclk, xclk;
 451         u32 features;
 452 } aty_chips[] = {
 453         /* 3D RAGE XL PCI-66/BGA */
 454         { 0x474f, 0x474f, 0x00, 0x00, m64n_xl_66, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
 455         /* 3D RAGE XL PCI-33/BGA */
 456         { 0x4752, 0x4752, 0x00, 0x00, m64n_xl_33, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
 457 };
 458 #if CONFIG_CONSOLE_BTEXT==1
 459 static void aty_calc_mem_refresh(struct fb_info_aty *info, u16 id, int xclk)
 460 {
 461         int i, size;
 462 #if 0
 463         const int ragepro_tbl[] = {
 464                 44, 50, 55, 66, 75, 80, 100
 465         };
 466 #endif
 467         const int ragexl_tbl[] = {
 468                 50, 66, 75, 83, 90, 95, 100, 105,
 469                 110, 115, 120, 125, 133, 143, 166
 470         };
 471         const int *refresh_tbl;
 472 #if 0
 473         if (IS_XL(id)) {
 474 #endif
 475                 refresh_tbl = ragexl_tbl;
 476                 size = sizeof(ragexl_tbl)/sizeof(int);
 477 #if 0
 478         } else {
 479                 refresh_tbl = ragepro_tbl;
 480                 size = sizeof(ragepro_tbl)/sizeof(int);
 481         }
 482 #endif
 483
 484         for (i=0; i < size; i++) {
 485                 if (xclk < refresh_tbl[i])
 486                         break;
 487         }
 488
 489         info->mem_refresh_rate = i;
 490 }
 491 #endif /*CONFIG_CONSOLE_BTEXT */
 492 static void ati_ragexl_init(device_t dev)
 493 {
 494         u32 chip_id;
 495         int j;
 496         u16 type;
 497         u8 rev;
 498         const char *chipname = NULL;
 499 #if CONFIG_CONSOLE_BTEXT
 500         u32 i;
 501         const char *xtal;
 502 #endif
 503         int pll, mclk, xclk;
 504
 505 #if CONFIG_CONSOLE_BTEXT==1
 506
 507 #if 0
 508         int gtb_memsize, k;
 509 #endif
 510
 511         struct fb_var_screeninfo var;
 512 #if 0
 513         struct display *disp;
 514 #endif
 515
 516 #if 0
 517         u8 pll_ref_div;
 518 #endif
 519
 520 #endif /*CONFIG_CONSOLE_BTEXT==1 */
 521
 522         struct fb_info_aty *info;
 523         struct fb_info_aty info_t;
 524         struct resource *res;
 525         info = &info_t;
 526
 527 #define USE_AUX_REG 1
 528
 529
 530         res = dev->resource_list;
 531         if(res->flags & IORESOURCE_IO) {
 532                 res = res->next;
 533         }
 534
 535 #if CONFIG_CONSOLE_BTEXT==1
 536         info->frame_buffer = res->base;
 537 #endif /* CONFIG_CONSOLE_BTEXT */
 538
 539 #if USE_AUX_REG==0
 540         info->ati_regbase = res->base+0x7ff000+0xc00;
 541 #else
 542         /* Fix this to look for the correct index. */
 543         //if (dev->resource_list && dev->resource_list->next)
 544         res = dev->resource_list->next->next;
 545         if(res->flags & IORESOURCE_MEM) {
 546                 info->ati_regbase = res->base+0x400; //using auxiliary register
 547         }
 548
 549 #endif
 550
 551 #if CONFIG_CONSOLE_BTEXT==1
 552         info->aty_cmap_regs = (struct aty_cmap_regs *)(info->ati_regbase+0xc0);
 553 #endif
 554
 555 #if 0
 556         printk(BIOS_DEBUG, "ati_regbase = 0x%08x, frame_buffer = 0x%08x\n", info->ati_regbase, info->frame_buffer);
 557 #endif
 558
 559         chip_id = aty_ld_le32(CONFIG_CHIP_ID, info);
 560         type = chip_id & CFG_CHIP_TYPE;
 561         rev = (chip_id & CFG_CHIP_REV)>>24;
 562         for (j = 0; j < ARRAY_SIZE(aty_chips); j++)
 563                 if (type == aty_chips[j].chip_type &&
 564                         (rev & aty_chips[j].rev_mask) == aty_chips[j].rev_val) {
 565                         chipname = aty_chips[j].name;
 566                         pll = aty_chips[j].pll;
 567                         mclk = aty_chips[j].mclk;
 568                         xclk = aty_chips[j].xclk;
 569                         info->features = aty_chips[j].features;
 570                         goto found;
 571         }
 572         printk(BIOS_SPEW, "ati_ragexl_init: Unknown mach64 0x%04x rev 0x%04x\n", type, rev);
 573         return ;
 574
 575 found:
 576         printk(BIOS_INFO, "ati_ragexl_init: %s [0x%04x rev 0x%02x]\n", chipname, type, rev);
 577 #if 0
 578         if (M64_HAS(INTEGRATED)) {
 579                 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
 580                 if (mclk == 67 && info->ram_type < SDRAM)
 581                         mclk = 63;
 582         }
 583 #endif
 584 #if CONFIG_CONSOLE_BTEXT==1
 585         aty_calc_mem_refresh(info, type, xclk);
 586 #endif /* CONFIG_CONSOLE_BTEXT */
 587
 588         info->pll_per = 1000000/pll;
 589         info->mclk_per = 1000000/mclk;
 590         info->xclk_per = 1000000/xclk;
 591
 592 //        info->dac_ops = &aty_dac_ct;
 593 //        info->pll_ops = &aty_pll_ct;
 594         info->bus_type = PCI;
 595
 596
 597         atyfb_xl_init(info);
 598
 599 #if CONFIG_CONSOLE_BTEXT==1
 600
 601         info->ram_type = (aty_ld_le32(CONFIG_STAT0, info) & 0x07);
 602
 603         info->ref_clk_per = 1000000000000ULL/14318180;
 604         xtal = "14.31818";
 605 #if 0
 606         if (M64_HAS(GTB_DSP) && (pll_ref_div = aty_ld_pll(PLL_REF_DIV, info))) {
 607                 int diff1, diff2;
 608                 diff1 = 510*14/pll_ref_div-pll;
 609                 diff2 = 510*29/pll_ref_div-pll;
 610                 if (diff1 < 0)
 611                         diff1 = -diff1;
 612                 if (diff2 < 0)
 613                         diff2 = -diff2;
 614                 if (diff2 < diff1) {
 615                         info->ref_clk_per = 1000000000000ULL/29498928;
 616                         xtal = "29.498928";
 617                 }
 618         }
 619 #endif
 620
 621     i = aty_ld_le32(MEM_CNTL, info);
 622 #if 0
 623     gtb_memsize = M64_HAS(GTB_DSP);
 624     if (gtb_memsize)  // We have
 625 #endif
 626         switch (i & 0xF) {      /* 0xF used instead of MEM_SIZE_ALIAS */
 627             case MEM_SIZE_512K:
 628                 info->total_vram = 0x80000;
 629                 break;
 630             case MEM_SIZE_1M:
 631                 info->total_vram = 0x100000;
 632                 break;
 633             case MEM_SIZE_2M_GTB:
 634                 info->total_vram = 0x200000;
 635                 break;
 636             case MEM_SIZE_4M_GTB:
 637                 info->total_vram = 0x400000;
 638                 break;
 639             case MEM_SIZE_6M_GTB:
 640                 info->total_vram = 0x600000;
 641                 break;
 642             case MEM_SIZE_8M_GTB:
 643                 info->total_vram = 0x800000;
 644                 break;
 645             default:
 646                 info->total_vram = 0x80000;
 647         }
 648 #if 0
 649     else
 650         switch (i & MEM_SIZE_ALIAS) {
 651             case MEM_SIZE_512K:
 652                 info->total_vram = 0x80000;
 653                 break;
 654             case MEM_SIZE_1M:
 655                 info->total_vram = 0x100000;
 656                 break;
 657             case MEM_SIZE_2M:
 658                 info->total_vram = 0x200000;
 659                 break;
 660             case MEM_SIZE_4M:
 661                 info->total_vram = 0x400000;
 662                 break;
 663             case MEM_SIZE_6M:
 664                 info->total_vram = 0x600000;
 665                 break;
 666             case MEM_SIZE_8M:
 667                 info->total_vram = 0x800000;
 668                 break;
 669             default:
 670                 info->total_vram = 0x80000;
 671        }
 672 #endif
 673
 674     if (M64_HAS(MAGIC_VRAM_SIZE)) {
 675         if (aty_ld_le32(CONFIG_STAT1, info) & 0x40000000)
 676           info->total_vram += 0x400000;
 677     }
 678 #if 0
 679     if (default_vram) {
 680         info->total_vram = default_vram*1024;
 681         i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
 682         if (info->total_vram <= 0x80000)
 683             i |= MEM_SIZE_512K;
 684         else if (info->total_vram <= 0x100000)
 685             i |= MEM_SIZE_1M;
 686         else if (info->total_vram <= 0x200000)
 687             i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
 688         else if (info->total_vram <= 0x400000)
 689             i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
 690         else if (info->total_vram <= 0x600000)
 691             i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
 692         else
 693             i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
 694         aty_st_le32(MEM_CNTL, i, info);
 695     }
 696 #endif
 697
 698     /* Clear the video memory */
 699 //    fb_memset((void *)info->frame_buffer, 0, info->total_vram);
 700 #if 0
 701         disp = &info->disp;
 702
 703 //    strcpy(info->fb_info.modename, atyfb_name);
 704     info->fb_info.node = -1;
 705 //    info->fb_info.fbops = &atyfb_ops;
 706     info->fb_info.disp = disp;
 707 //    strcpy(info->fb_info.fontname, fontname);
 708     info->fb_info.changevar = NULL;
 709 //    info->fb_info.switch_con = &atyfbcon_switch;
 710 //    info->fb_info.updatevar = &atyfbcon_updatevar;
 711 //    info->fb_info.blank = &atyfbcon_blank;
 712     info->fb_info.flags = FBINFO_FLAG_DEFAULT;
 713 #endif
 714         var = default_var;
 715
 716 #if 0
 717     if (noaccel)  // We has noaccel in default
 718         var.accel_flags &= ~FB_ACCELF_TEXT;
 719     else
 720         var.accel_flags |= FB_ACCELF_TEXT;
 721 #endif
 722
 723     if (var.yres == var.yres_virtual) {
 724         u32 vram = info->total_vram ;
 725         var.yres_virtual = ((vram * 8) / var.bits_per_pixel) / var.xres_virtual;
 726         if (var.yres_virtual < var.yres)
 727                 var.yres_virtual = var.yres;
 728     }
 729
 730     if (atyfb_decode_var(&var, &info->default_par, info)) {
 731 #if 0
 732         printk(BIOS_DEBUG, "atyfb: can't set default video mode\n");
 733 #endif
 734         return ;
 735     }
 736 #if 0
 737     for (j = 0; j < 16; j++) {
 738         k = color_table[j];
 739         info->palette[j].red = default_red[k];
 740         info->palette[j].green = default_grn[k];
 741         info->palette[j].blue = default_blu[k];
 742     }
 743 #endif
 744
 745 #if 0
 746     if (curblink && M64_HAS(INTEGRATED)) {
 747         info->cursor = aty_init_cursor(info);
 748         if (info->cursor) {
 749             info->dispsw.cursor = atyfb_cursor;
 750             info->dispsw.set_font = atyfb_set_font;
 751         }
 752     }
 753 #endif
 754
 755 #if PLL_CRTC_DECODE==1
 756         atyfb_set_var(&var, -1, &info->fb_info);
 757 #else
 758             atyfb_set_par(&info->default_par, info);
 759 //            do_install_cmap(-1, &info->fb_info);
 760             do_install_cmap(-1, info);
 761 #endif
 762
 763 #if PLL_CRTC_DECODE==1
 764
 765     printk(BIOS_SPEW, "framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,
 766                          (((info->current_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
 767                          ((info->current_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
 768                          info->current_par.crtc.bpp,
 769                          info->current_par.crtc.vxres*info->default_par.crtc.bpp/8
 770                         );
 771  btext_setup_display(
 772                          (((info->current_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
 773                          ((info->current_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
 774                          info->current_par.crtc.bpp,
 775                          info->current_par.crtc.vxres*info->current_par.crtc.bpp/8,info->frame_buffer);
 776 #else
 777     printk(BIOS_SPEW, "framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,
 778                          (((info->default_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
 779                          ((info->default_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
 780                          info->default_par.crtc.bpp,
 781                          info->default_par.crtc.vxres*info->default_par.crtc.bpp/8
 782                         );
 783  btext_setup_display(
 784                          (((info->default_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
 785                          ((info->default_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
 786                          info->default_par.crtc.bpp,
 787                          info->default_par.crtc.vxres*info->default_par.crtc.bpp/8,info->frame_buffer);
 788 #endif
 789
 790  btext_clearscreen();
 791
 792  map_boot_text();
 793
 794 #if 0
 795
 796  btext_drawstring("test framebuffer\n");
 797
 798  mdelay(10000);
 799 // test end
 800 #endif
 801
 802 #endif /* CONFIG_CONSOLE_BTEXT */
 803
 804 }
 805
 806 #if CONFIG_CONSOLE_BTEXT==1
 807
 808 static int atyfb_decode_var(const struct fb_var_screeninfo *var,
 809                             struct atyfb_par *par,
 810                             const struct fb_info_aty *info)
 811 {
 812     int err;
 813
 814     if ((err = aty_var_to_crtc(info, var, &par->crtc)) ||
 815         (err = aty_var_to_pll_ct(info, var->pixclock, par->crtc.bpp,
 816                                          &par->pll)))
 817         return err;
 818
 819 #if 0
 820     if (var->accel_flags & FB_ACCELF_TEXT)
 821         par->accel_flags = FB_ACCELF_TEXT;
 822     else
 823 #endif
 824         par->accel_flags = 0;
 825
 826 #if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
 827     if (!fbmon_valid_timings(var->pixclock, htotal, vtotal, info))
 828         return -EINVAL;
 829 #endif
 830
 831     return 0;
 832 }
 833 #if PLL_CRTC_DECODE==1
 834 static int atyfb_encode_var(struct fb_var_screeninfo *var,
 835                             const struct atyfb_par *par,
 836                             const struct fb_info_aty *info)
 837 {
 838     int err;
 839
 840     memset(var, 0, sizeof(struct fb_var_screeninfo));
 841
 842     if ((err = aty_crtc_to_var(&par->crtc, var)))
 843         return err;
 844     var->pixclock = aty_pll_ct_to_var(info, &par->pll);
 845
 846     var->height = -1;
 847     var->width = -1;
 848     var->accel_flags = par->accel_flags;
 849
 850     return 0;
 851 }
 852 #endif
 853 static void aty_set_crtc(const struct fb_info_aty *info,
 854                          const struct crtc *crtc)
 855 {
 856     aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, info);
 857     aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, info);
 858     aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, info);
 859     aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, info);
 860     aty_st_le32(CRTC_VLINE_CRNT_VLINE, 0, info);
 861     aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, info);
 862     aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, info);
 863 }
 864
 865 static int aty_var_to_crtc(const struct fb_info_aty *info,
 866                            const struct fb_var_screeninfo *var,
 867                            struct crtc *crtc)
 868 {
 869     u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
 870     u32 left, right, upper, lower, hslen, vslen, sync, vmode;
 871     u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
 872     u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
 873     u32 pix_width, dp_pix_width, dp_chain_mask;
 874
 875     /* input */
 876     xres = var->xres;
 877     yres = var->yres;
 878     vxres = var->xres_virtual;
 879     vyres = var->yres_virtual;
 880     xoffset = var->xoffset;
 881     yoffset = var->yoffset;
 882     bpp = var->bits_per_pixel;
 883     left = var->left_margin;
 884     right = var->right_margin;
 885     upper = var->upper_margin;
 886     lower = var->lower_margin;
 887     hslen = var->hsync_len;
 888     vslen = var->vsync_len;
 889     sync = var->sync;
 890     vmode = var->vmode;
 891
 892     /* convert (and round up) and validate */
 893     xres = (xres+7) & ~7;
 894     xoffset = (xoffset+7) & ~7;
 895     vxres = (vxres+7) & ~7;
 896     if (vxres < xres+xoffset)
 897         vxres = xres+xoffset;
 898     h_disp = xres/8-1;
 899     if (h_disp > 0xff)
 900         FAIL("h_disp too large");
 901     h_sync_strt = h_disp+(right/8);
 902     if (h_sync_strt > 0x1ff)
 903         FAIL("h_sync_start too large");
 904     h_sync_dly = right & 7;
 905     h_sync_wid = (hslen+7)/8;
 906     if (h_sync_wid > 0x1f)
 907         FAIL("h_sync_wid too large");
 908     h_total = h_sync_strt+h_sync_wid+(h_sync_dly+left+7)/8;
 909     if (h_total > 0x1ff)
 910      FAIL("h_total too large");
 911     h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
 912
 913     if (vyres < yres+yoffset)
 914         vyres = yres+yoffset;
 915     v_disp = yres-1;
 916     if (v_disp > 0x7ff)
 917         FAIL("v_disp too large");
 918     v_sync_strt = v_disp+lower;
 919     if (v_sync_strt > 0x7ff)
 920         FAIL("v_sync_strt too large");
 921     v_sync_wid = vslen;
 922     if (v_sync_wid > 0x1f)
 923         FAIL("v_sync_wid too large");
 924     v_total = v_sync_strt+v_sync_wid+upper;
 925     if (v_total > 0x7ff)
 926         FAIL("v_total too large");
 927     v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
 928
 929     c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
 930
 931     if (bpp <= 8) {
 932         bpp = 8;
 933         pix_width = CRTC_PIX_WIDTH_8BPP;
 934         dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB;
 935         dp_chain_mask = 0x8080;
 936     }
 937 #if SUPPORT_8_BPP_ABOVE==1
 938    else if (bpp <= 16) {
 939         bpp = 16;
 940         pix_width = CRTC_PIX_WIDTH_15BPP;
 941         dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
 942                        BYTE_ORDER_LSB_TO_MSB;
 943         dp_chain_mask = 0x4210;
 944     } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
 945         bpp = 24;
 946         pix_width = CRTC_PIX_WIDTH_24BPP;
 947         dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB;
 948         dp_chain_mask = 0x8080;
 949     } else if (bpp <= 32) {
 950         bpp = 32;
 951         pix_width = CRTC_PIX_WIDTH_32BPP;
 952         dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
 953                        BYTE_ORDER_LSB_TO_MSB;
 954         dp_chain_mask = 0x8080;
 955     }
 956 #endif
 957 else
 958         FAIL("invalid bpp");
 959
 960     if (vxres*vyres*bpp/8 > info->total_vram)
 961         FAIL("not enough video RAM");
 962   if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
 963         FAIL("invalid vmode");
 964
 965     /* output */
 966     crtc->vxres = vxres;
 967     crtc->vyres = vyres;
 968     crtc->xoffset = xoffset;
 969     crtc->yoffset = yoffset;
 970     crtc->bpp = bpp;
 971     crtc->h_tot_disp = h_total | (h_disp<<16);
 972     crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
 973                             ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) |
 974                             (h_sync_pol<<21);
 975     crtc->v_tot_disp = v_total | (v_disp<<16);
 976     crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
 977     crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
 978     crtc->gen_cntl = pix_width | c_sync | CRTC_EXT_DISP_EN | CRTC_ENABLE;
 979     if (M64_HAS(MAGIC_FIFO)) {
 980         /* Not VTB/GTB */
 981         /* FIXME: magic FIFO values */
 982         crtc->gen_cntl |= aty_ld_le32(CRTC_GEN_CNTL, info) & 0x000e0000;
 983     }
 984     crtc->dp_pix_width = dp_pix_width;
 985     crtc->dp_chain_mask = dp_chain_mask;
 986
 987     return 0;
 988 }
 989 #if PLL_CRTC_DECODE==1
 990 static int aty_crtc_to_var(const struct crtc *crtc,
 991                            struct fb_var_screeninfo *var)
 992 {
 993     u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
 994     u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
 995     u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
 996     u32 pix_width;
 997
 998     /* input */
 999     h_total = crtc->h_tot_disp & 0x1ff;
1000     h_disp = (crtc->h_tot_disp>>16) & 0xff;
1001     h_sync_strt = (crtc->h_sync_strt_wid & 0xff) |
1002                   ((crtc->h_sync_strt_wid>>4) & 0x100);
1003     h_sync_dly = (crtc->h_sync_strt_wid>>8) & 0x7;
1004     h_sync_wid = (crtc->h_sync_strt_wid>>16) & 0x1f;
1005     h_sync_pol = (crtc->h_sync_strt_wid>>21) & 0x1;
1006     v_total = crtc->v_tot_disp & 0x7ff;
1007     v_disp = (crtc->v_tot_disp>>16) & 0x7ff;
1008     v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1009     v_sync_wid = (crtc->v_sync_strt_wid>>16) & 0x1f;
1010     v_sync_pol = (crtc->v_sync_strt_wid>>21) & 0x1;
1011     c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1012     pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1013
1014     /* convert */
1015     xres = (h_disp+1)*8;
1016     yres = v_disp+1;
1017     left = (h_total-h_sync_strt-h_sync_wid)*8-h_sync_dly;
1018     right = (h_sync_strt-h_disp)*8+h_sync_dly;
1019     hslen = h_sync_wid*8;
1020     upper = v_total-v_sync_strt-v_sync_wid;
1021     lower = v_sync_strt-v_disp;
1022     vslen = v_sync_wid;
1023     sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1024            (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1025            (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1026
1027     switch (pix_width) {
1028 #if 0
1029         case CRTC_PIX_WIDTH_4BPP:
1030             bpp = 4;
1031             var->red.offset = 0;
1032             var->red.length = 8;
1033             var->green.offset = 0;
1034             var->green.length = 8;
1035             var->blue.offset = 0;
1036             var->blue.length = 8;
1037             var->transp.offset = 0;
1038             var->transp.length = 0;
1039             break;
1040 #endif
1041         case CRTC_PIX_WIDTH_8BPP:
1042             bpp = 8;
1043             var->red.offset = 0;
1044             var->red.length = 8;
1045             var->green.offset = 0;
1046             var->green.length = 8;
1047             var->blue.offset = 0;
1048             var->blue.length = 8;
1049             var->transp.offset = 0;
1050             var->transp.length = 0;
1051             break;
1052 #if SUPPORT_8_BPP_ABOVE==1
1053         case CRTC_PIX_WIDTH_15BPP:      /* RGB 555 */
1054             bpp = 16;
1055             var->red.offset = 10;
1056             var->red.length = 5;
1057             var->green.offset = 5;
1058             var->green.length = 5;
1059             var->blue.offset = 0;
1060             var->blue.length = 5;
1061             var->transp.offset = 0;
1062             var->transp.length = 0;
1063             break;
1064         case CRTC_PIX_WIDTH_16BPP:      /* RGB 565 */
1065             bpp = 16;
1066             var->red.offset = 11;
1067             var->red.length = 5;
1068             var->green.offset = 5;
1069             var->green.length = 6;
1070             var->blue.offset = 0;
1071             var->blue.length = 5;
1072             var->transp.offset = 0;
1073             var->transp.length = 0;
1074             break;
1075         case CRTC_PIX_WIDTH_24BPP:      /* RGB 888 */
1076             bpp = 24;
1077             var->red.offset = 16;
1078             var->red.length = 8;
1079             var->green.offset = 8;
1080             var->green.length = 8;
1081             var->blue.offset = 0;
1082             var->blue.length = 8;
1083            var->transp.offset = 0;
1084             var->transp.length = 0;
1085             break;
1086         case CRTC_PIX_WIDTH_32BPP:      /* ARGB 8888 */
1087             bpp = 32;
1088             var->red.offset = 16;
1089             var->red.length = 8;
1090             var->green.offset = 8;
1091             var->green.length = 8;
1092             var->blue.offset = 0;
1093             var->blue.length = 8;
1094             var->transp.offset = 24;
1095             var->transp.length = 8;
1096             break;
1097 #endif
1098         default:
1099             FAIL("Invalid pixel width");
1100     }
1101
1102     /* output */
1103     var->xres = xres;
1104     var->yres = yres;
1105     var->xres_virtual = crtc->vxres;
1106     var->yres_virtual = crtc->vyres;
1107     var->bits_per_pixel = bpp;
1108     var->xoffset = crtc->xoffset;
1109     var->yoffset = crtc->yoffset;
1110     var->left_margin = left;
1111     var->right_margin = right;
1112     var->upper_margin = upper;
1113     var->lower_margin = lower;
1114     var->hsync_len = hslen;
1115     var->vsync_len = vslen;
1116     var->sync = sync;
1117     var->vmode = FB_VMODE_NONINTERLACED;
1118
1119     return 0;
1120 }
1121 #endif
1122
1123 #if 0
1124 static int encode_fix(struct fb_fix_screeninfo *fix,
1125                       const struct atyfb_par *par,
1126                       const struct fb_info_aty *info)
1127 {
1128     memset(fix, 0, sizeof(struct fb_fix_screeninfo));
1129
1130    // strcpy(fix->id, atyfb_name);
1131          memcpy(fix->id, "atyfb", 5);
1132     fix->smem_start = info->frame_buffer;
1133     fix->smem_len = (u32)info->total_vram;
1134
1135     /*
1136      *  Reg Block 0 (CT-compatible block) is at ati_regbase_phys
1137      *  Reg Block 1 (multimedia extensions) is at ati_regbase_phys-0x400
1138      */
1139     if (M64_HAS(GX)) {
1140         fix->mmio_start = info->ati_regbase;
1141         fix->mmio_len = 0x400;
1142         fix->accel = FB_ACCEL_ATI_MACH64GX;
1143     } else if (M64_HAS(CT)) {
1144         fix->mmio_start = info->ati_regbase;
1145         fix->mmio_len = 0x400;
1146         fix->accel = FB_ACCEL_ATI_MACH64CT;
1147     } else if (M64_HAS(VT)) {
1148         fix->mmio_start = info->ati_regbase-0x400;
1149         fix->mmio_len = 0x800;
1150         fix->accel = FB_ACCEL_ATI_MACH64VT;
1151     } else /* if (M64_HAS(GT)) */ {
1152         fix->mmio_start = info->ati_regbase-0x400;
1153         fix->mmio_len = 0x800;
1154         fix->accel = FB_ACCEL_ATI_MACH64GT;
1155     }
1156     fix->type = FB_TYPE_PACKED_PIXELS;
1157     fix->type_aux = 0;
1158     fix->line_length = par->crtc.vxres*par->crtc.bpp/8;
1159     fix->visual = par->crtc.bpp <= 8 ? FB_VISUAL_PSEUDOCOLOR
1160                                      : FB_VISUAL_DIRECTCOLOR;
1161     fix->ywrapstep = 0;
1162     fix->xpanstep = 8;
1163     fix->ypanstep = 1;
1164
1165     return 0;
1166 }
1167 #endif
1168    /*
1169      *  Set the User Defined Part of the Display
1170      */
1171 #if PLL_CRTC_DECODE==1
1172 static int atyfb_set_var(struct fb_var_screeninfo *var, int con,
1173                          struct fb_info *fb)
1174 {
1175     struct fb_info_aty *info = (struct fb_info_aty *)fb;
1176     struct atyfb_par par;
1177 #if 0
1178     struct display *display;
1179     int oldxres, oldyres, oldvxres, oldvyres, oldbpp, oldaccel, accel;
1180 #endif
1181     int err;
1182     int activate = var->activate;
1183
1184 #if 0
1185     if (con >= 0)
1186         display = &fb_display[con];
1187     else
1188 #endif
1189 #if 0
1190         display = fb->disp;     /* used during initialization */
1191 #endif
1192
1193     if ((err = atyfb_decode_var(var, &par, info)))
1194         return err;
1195
1196     atyfb_encode_var(var, &par, (struct fb_info_aty *)info);
1197
1198 #if 0
1199     printk(BIOS_INFO, "atyfb_set_var: activate=%d\n", activate & FB_ACTIVATE_MASK);
1200 #endif
1201
1202     if ((activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) {
1203 #if 0
1204         oldxres = display->var.xres;
1205         oldyres = display->var.yres;
1206         oldvxres = display->var.xres_virtual;
1207         oldvyres = display->var.yres_virtual;
1208         oldbpp = display->var.bits_per_pixel;
1209         oldaccel = display->var.accel_flags;
1210         display->var = *var;
1211         accel = var->accel_flags & FB_ACCELF_TEXT;
1212         if (oldxres != var->xres || oldyres != var->yres ||
1213             oldvxres != var->xres_virtual || oldvyres != var->yres_virtual ||
1214             oldbpp != var->bits_per_pixel || oldaccel != var->accel_flags) {
1215             struct fb_fix_screeninfo fix;
1216
1217             encode_fix(&fix, &par, info);
1218             display->screen_base = (char *)info->frame_buffer;
1219             display->visual = fix.visual;
1220             display->type = fix.type;
1221             display->type_aux = fix.type_aux;
1222             display->ypanstep = fix.ypanstep;
1223             display->ywrapstep = fix.ywrapstep;
1224             display->line_length = fix.line_length;
1225             display->can_soft_blank = 1;
1226             display->inverse = 0;
1227 #if 0
1228            if (accel)
1229                 display->scrollmode = (info->bus_type == PCI) ? SCROLL_YNOMOVE : 0;
1230             else
1231 #endif
1232                 display->scrollmode = SCROLL_YREDRAW;
1233 #if 0
1234             if (info->fb_info.changevar)
1235                 (*info->fb_info.changevar)(con);
1236 #endif
1237         }
1238 #endif
1239 //        if (!info->fb_info.display_fg ||
1240 //            info->fb_info.display_fg->vc_num == con) {
1241             atyfb_set_par(&par, info);
1242 #if 0
1243             atyfb_set_dispsw(display, info, par.crtc.bpp, accel);
1244 #endif
1245 //        }
1246 #if 0
1247         if (oldbpp != var->bits_per_pixel) {
1248             if ((err = fb_alloc_cmap(&display->cmap, 0, 0)))
1249                 return err;
1250 #endif
1251             do_install_cmap(con, info);
1252 #if 0
1253         }
1254 #endif
1255     }
1256
1257     return 0;
1258 }
1259
1260 #endif
1261 /* ------------------------------------------------------------------------- */
1262
1263 static void atyfb_set_par(const struct atyfb_par *par,
1264                           struct fb_info_aty *info)
1265 {
1266     u32 i;
1267     int accelmode;
1268     u8 tmp;
1269
1270     accelmode = par->accel_flags;  /* hack */
1271
1272 #if PLL_CRTC_DECODE==1
1273     info->current_par = *par;
1274 #endif
1275
1276     if (info->blitter_may_be_busy)
1277         wait_for_idle(info);
1278     tmp = aty_ld_8(CRTC_GEN_CNTL + 3, info);
1279     aty_set_crtc(info, &par->crtc);
1280     aty_st_8(CLOCK_CNTL + info->clk_wr_offset, 0, info);
1281                                         /* better call aty_StrobeClock ?? */
1282     aty_st_8(CLOCK_CNTL + info->clk_wr_offset, CLOCK_STROBE, info);
1283
1284     //info->dac_ops->set_dac(info, &par->pll, par->crtc.bpp, accelmode);
1285     //info->pll_ops->set_pll(info, &par->pll);
1286    aty_set_pll_ct(info, &par->pll);
1287
1288
1289     if (!M64_HAS(INTEGRATED)) {
1290         /* Don't forget MEM_CNTL */
1291         i = aty_ld_le32(MEM_CNTL, info) & 0xf0ffffff;
1292         switch (par->crtc.bpp) {
1293             case 8:
1294                 i |= 0x02000000;
1295                 break;
1296 #if SUPPORT_8_BPP_ABOVE==1
1297             case 16:
1298                 i |= 0x03000000;
1299                 break;
1300             case 32:
1301                 i |= 0x06000000;
1302                 break;
1303 #endif
1304         }
1305         aty_st_le32(MEM_CNTL, i, info);
1306     } else {
1307         i = aty_ld_le32(MEM_CNTL, info) & 0xf00fffff;
1308         if (!M64_HAS(MAGIC_POSTDIV))
1309                 i |= info->mem_refresh_rate << 20;
1310         switch (par->crtc.bpp) {
1311             case 8:
1312 #if SUPPORT_8_BPP_ABOVE==1
1313             case 24:
1314 #endif
1315                 i |= 0x00000000;
1316                break;
1317 #if SUPPORT_8_BPP_ABOVE==1
1318             case 16:
1319                 i |= 0x04000000;
1320                 break;
1321             case 32:
1322                 i |= 0x08000000;
1323                 break;
1324 #endif
1325         }
1326         if (M64_HAS(CT_BUS)) {
1327             aty_st_le32(DAC_CNTL, 0x87010184, info);
1328             aty_st_le32(BUS_CNTL, 0x680000f9, info);
1329         } else if (M64_HAS(VT_BUS)) {
1330             aty_st_le32(DAC_CNTL, 0x87010184, info);
1331             aty_st_le32(BUS_CNTL, 0x680000f9, info);
1332         }  else if (M64_HAS(MOBIL_BUS)) {
1333             aty_st_le32(DAC_CNTL, 0x80010102, info);
1334             aty_st_le32(BUS_CNTL, 0x7b33a040, info);
1335         }  else {
1336             /* GT */
1337             aty_st_le32(DAC_CNTL, 0x86010102, info);
1338             aty_st_le32(BUS_CNTL, 0x7b23a040, info);
1339             aty_st_le32(EXT_MEM_CNTL,
1340                         aty_ld_le32(EXT_MEM_CNTL, info) | 0x5000001, info);
1341         }
1342
1343         aty_st_le32(MEM_CNTL, i, info);
1344     }
1345     aty_st_8(DAC_MASK, 0xff, info);
1346
1347     /* Initialize the graphics engine */
1348 #if 0
1349     if (par->accel_flags & FB_ACCELF_TEXT)
1350         aty_init_engine(par, info);
1351 #endif
1352
1353
1354 }
1355 #if 0
1356 static u16 red2[] = {
1357     0x0000, 0xaaaa
1358 };
1359 static u16 green2[] = {
1360     0x0000, 0xaaaa
1361 };
1362 static u16 blue2[] = {
1363     0x0000, 0xaaaa
1364 };
1365
1366 static u16 red4[] = {
1367     0x0000, 0xaaaa, 0x5555, 0xffff
1368 };
1369 static u16 green4[] = {
1370     0x0000, 0xaaaa, 0x5555, 0xffff
1371 };
1372 static u16 blue4[] = {
1373     0x0000, 0xaaaa, 0x5555, 0xffff
1374 };
1375
1376 static u16 red8[] = {
1377     0x0000, 0x0000, 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa
1378 };
1379 static u16 green8[] = {
1380     0x0000, 0x0000, 0xaaaa, 0xaaaa, 0x0000, 0x0000, 0x5555, 0xaaaa
1381 };
1382 static u16 blue8[] = {
1383     0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa
1384 };
1385 #endif
1386 static u16 red16[] = {
1387     0x0000, 0x0000, 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
1388     0x5555, 0x5555, 0x5555, 0x5555, 0xffff, 0xffff, 0xffff, 0xffff
1389 };
1390 static u16 green16[] = {
1391     0x0000, 0x0000, 0xaaaa, 0xaaaa, 0x0000, 0x0000, 0x5555, 0xaaaa,
1392     0x5555, 0x5555, 0xffff, 0xffff, 0x5555, 0x5555, 0xffff, 0xffff
1393 };
1394 static u16 blue16[] = {
1395     0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa,
1396     0x5555, 0xffff, 0x5555, 0xffff, 0x5555, 0xffff, 0x5555, 0xffff
1397 };
1398 #if 0
1399 static struct fb_cmap default_2_colors = {
1400     0, 2, red2, green2, blue2, NULL
1401 };
1402 static struct fb_cmap default_8_colors = {
1403     0, 8, red8, green8, blue8, NULL
1404 };
1405 static struct fb_cmap default_4_colors = {
1406     0, 4, red4, green4, blue4, NULL
1407 };
1408 #endif
1409 static struct fb_cmap default_16_colors = {
1410     0, 16, red16, green16, blue16, NULL
1411 };
1412
1413
1414
1415 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
1416                            u_int transp, struct fb_info_aty *info)
1417 {
1418     int i, scale;
1419
1420     if (regno > 255)
1421         return 1;
1422     red >>= 8;
1423     green >>= 8;
1424     blue >>= 8;
1425 #if 0
1426 //We don't need to store it
1427     info->palette[regno].red = red;
1428     info->palette[regno].green = green;
1429     info->palette[regno].blue = blue;
1430 #endif
1431     i = aty_ld_8(DAC_CNTL, info) & 0xfc;
1432     if (M64_HAS(EXTRA_BRIGHT))
1433         i |= 0x2;       /*DAC_CNTL|0x2 turns off the extra brightness for gt*/
1434     aty_st_8(DAC_CNTL, i, info);
1435     aty_st_8(DAC_MASK, 0xff, info);
1436 #if PLL_CRTC_DECODE==1
1437     scale = (M64_HAS(INTEGRATED) && info->current_par.crtc.bpp == 16) ? 3 : 0;
1438 #else
1439     scale = (M64_HAS(INTEGRATED) && info->default_par.crtc.bpp == 16) ? 3 : 0;
1440 #endif
1441     write8(&info->aty_cmap_regs->windex, regno << scale)
1442     write8(&info->aty_cmap_regs->lut, red);
1443     write8(&info->aty_cmap_regs->lut, green);
1444     write8(&info->aty_cmap_regs->lut, blue);
1445     return 0;
1446 }
1447
1448 int fb_set_cmap(struct fb_cmap *cmap, int kspc,
1449                 int (*setcolreg)(u_int, u_int, u_int, u_int, u_int,
1450                                  struct fb_info_aty *),
1451                 struct fb_info_aty *info)
1452 {
1453     int i, start;
1454     u16 *red, *green, *blue, *transp;
1455     u_int hred, hgreen, hblue, htransp;
1456
1457     red = cmap->red;
1458     green = cmap->green;
1459     blue = cmap->blue;
1460     transp = cmap->transp;
1461     start = cmap->start;
1462
1463     if (start < 0)
1464         return -EINVAL;
1465     for (i = 0; i < cmap->len; i++) {
1466             hred = *red;
1467             hgreen = *green;
1468             hblue = *blue;
1469             htransp = transp ? *transp : 0;
1470         red++;
1471         green++;
1472         blue++;
1473         if (transp)
1474             transp++;
1475         if (setcolreg(start++, hred, hgreen, hblue, htransp, info))
1476             return 0;
1477     }
1478     return 0;
1479 }
1480
1481 struct fb_cmap *fb_default_cmap(int len)
1482 {
1483 #if 0
1484     if (len <= 2)
1485         return &default_2_colors;
1486     if (len <= 4)
1487         return &default_4_colors;
1488     if (len <= 8)
1489         return &default_8_colors;
1490 #endif
1491     return &default_16_colors;
1492 }
1493
1494 static void do_install_cmap(int con, struct fb_info_aty *info)
1495 {
1496 #if PLL_CRTC_DECODE==1
1497         int size = info->current_par.crtc.bpp == 16 ? 32 : 256;
1498 #else
1499         int size = 256;
1500 #endif
1501         fb_set_cmap(fb_default_cmap(size), 1, atyfb_setcolreg, info);
1502 }
1503
1504 #endif /*CONFIG_CONSOLE_BTEXT */
1505
1506 static struct device_operations ati_ragexl_graph_ops  = {
1507         .read_resources   = pci_dev_read_resources,
1508         .set_resources    = pci_dev_set_resources,
1509         .enable_resources = pci_dev_enable_resources,
1510         .init             = ati_ragexl_init,
1511         .scan_bus         = 0,
1512 };
1513
1514 static const struct pci_driver ati_ragexl_graph_driver __pci_driver = {
1515         .ops    = &ati_ragexl_graph_ops,
1516         .vendor = PCI_VENDOR_ID_ATI,
1517         .device = PCI_DEVICE_ID_ATI_215XL,
1518 };
1519
1520