2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #ifndef _SB700_SMBUS_C_
21 #define _SB700_SMBUS_C_
25 void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
29 outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX);
32 * For certain revisions of the chip, the ABCFG registers,
33 * with an address of 0x100NN (where 'N' is any hexadecimal
34 * number), require an extra programming step.*/
35 reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL;
40 /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */
41 outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
43 reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL;
46 /* space = 0: AX_INDXC, AX_DATAC
47 * space = 1: AX_INDXP, AX_DATAP
49 void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val)
53 /* read axindc to tmp */
54 outl(space << 30 | space << 3 | 0x30, AB_INDX);
55 outl(axindc, AB_DATA);
56 outl(space << 30 | space << 3 | 0x34, AB_INDX);
63 outl(space << 30 | space << 3 | 0x30, AB_INDX);
64 outl(axindc, AB_DATA);
65 outl(space << 30 | space << 3 | 0x34, AB_INDX);
70 static inline void smbus_delay(void)
72 outb(inb(0x80), 0x80);
75 static int smbus_wait_until_ready(u32 smbus_io_base)
78 loops = SMBUS_TIMEOUT;
81 val = inb(smbus_io_base + SMBHSTSTAT);
83 if (val == 0) { /* ready now */
86 outb(val, smbus_io_base + SMBHSTSTAT);
88 return -2; /* time out */
91 static int smbus_wait_until_done(u32 smbus_io_base)
94 loops = SMBUS_TIMEOUT;
98 val = inb(smbus_io_base + SMBHSTSTAT);
99 val &= 0x1f; /* mask off reserved bits */
101 return -5; /* error */
104 outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */
108 return -3; /* timeout */
111 int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
115 if (smbus_wait_until_ready(smbus_io_base) < 0) {
116 return -2; /* not ready */
119 /* set the device I'm talking too */
120 outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
122 byte = inb(smbus_io_base + SMBHSTCTRL);
123 byte &= 0xe3; /* Clear [4:2] */
124 byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */
125 outb(byte, smbus_io_base + SMBHSTCTRL);
127 /* poll for transaction completion */
128 if (smbus_wait_until_done(smbus_io_base) < 0) {
129 return -3; /* timeout or error */
132 /* read results of transaction */
133 byte = inb(smbus_io_base + SMBHSTCMD);
138 int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
142 if (smbus_wait_until_ready(smbus_io_base) < 0) {
143 return -2; /* not ready */
146 /* set the command... */
147 outb(val, smbus_io_base + SMBHSTCMD);
149 /* set the device I'm talking too */
150 outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
152 byte = inb(smbus_io_base + SMBHSTCTRL);
153 byte &= 0xe3; /* Clear [4:2] */
154 byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */
155 outb(byte, smbus_io_base + SMBHSTCTRL);
157 /* poll for transaction completion */
158 if (smbus_wait_until_done(smbus_io_base) < 0) {
159 return -3; /* timeout or error */
165 int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
169 if (smbus_wait_until_ready(smbus_io_base) < 0) {
170 return -2; /* not ready */
173 /* set the command/address... */
174 outb(address & 0xff, smbus_io_base + SMBHSTCMD);
176 /* set the device I'm talking too */
177 outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
179 byte = inb(smbus_io_base + SMBHSTCTRL);
180 byte &= 0xe3; /* Clear [4:2] */
181 byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */
182 outb(byte, smbus_io_base + SMBHSTCTRL);
184 /* poll for transaction completion */
185 if (smbus_wait_until_done(smbus_io_base) < 0) {
186 return -3; /* timeout or error */
189 /* read results of transaction */
190 byte = inb(smbus_io_base + SMBHSTDAT0);
195 int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
199 if (smbus_wait_until_ready(smbus_io_base) < 0) {
200 return -2; /* not ready */
203 /* set the command/address... */
204 outb(address & 0xff, smbus_io_base + SMBHSTCMD);
206 /* set the device I'm talking too */
207 outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
210 outb(val, smbus_io_base + SMBHSTDAT0);
212 byte = inb(smbus_io_base + SMBHSTCTRL);
213 byte &= 0xe3; /* Clear [4:2] */
214 byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */
215 outb(byte, smbus_io_base + SMBHSTCTRL);
217 /* poll for transaction completion */
218 if (smbus_wait_until_done(smbus_io_base) < 0) {
219 return -3; /* timeout or error */