2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee>
5 * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com>
6 * Copyright (C) 2007 Advanced Micro Devices, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 /**************************************************************************
27 ;*************************************************************************/
28 #include "cpu/x86/msr.h"
34 * Delay Control Settings table from AMD (MCP 0x4C00000F).
36 static const msrinit_t delay_msr_table[] = {
37 {CPU_BC_MSS_ARRAY_CTL0, {.hi = 0x00000000, .lo = 0x2814D352}},
38 {CPU_BC_MSS_ARRAY_CTL1, {.hi = 0x00000000, .lo = 0x1068334D}},
39 {CPU_BC_MSS_ARRAY_CTL2, {.hi = 0x00000106, .lo = 0x83104104}},
44 static const struct delay_controls {
51 } delay_control_table[] = {
52 /* DIMMs Devs Slow (<=333MHz) Fast (>334MHz) */
53 { 1, 4, 0x0837100FF, 0x056960004, 0x0827100FF, 0x056960004 },
54 { 1, 8, 0x0837100AA, 0x056960004, 0x0827100AA, 0x056960004 },
55 { 1, 16, 0x0837100AA, 0x056960004, 0x082710055, 0x056960004 },
56 { 2, 8, 0x0837100A5, 0x056960004, 0x082710000, 0x056960004 },
57 { 2, 16, 0x0937100A5, 0x056960004, 0x0C27100A5, 0x056960004 },
58 { 2, 20, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 },
59 { 2, 24, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 },
60 { 2, 32, 0x0B37100A5, 0x056960004, 0x0B2710000, 0x056960004 },
64 * Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM
65 * in slot 0, but it should be clear for all 2 DIMM settings and if a
66 * single DIMM is in slot 1. Bits 54:52 should always be set to '111'.
68 * Settings for single DIMM and no VTT termination (like DB800 platform)
69 * 0xF2F100FF 0x56960004
70 * -------------------------------------
71 * ADDR/CTL have 22 ohm series R
72 * DQ/DQM/DQS have 33 ohm series R
76 * This is Black Magic DRAM timing juju[1].
78 * DRAM delay depends on CPU clock, memory bus clock, memory bus loading,
79 * memory bus termination, your middle initial (ha! caught you!), GeodeLink
80 * clock rate, and DRAM timing specifications.
82 * From this the code computes a number which is "known to work". No,
83 * hardware is not an exact science. And, finally, if an FS2 (JTAG debugger)
84 * is hooked up, then just don't do anything. This code was written by a master
85 * of the Dark Arts at AMD and should not be modified in any way.
87 * [1] (http://www.thefreedictionary.com/juju)
89 * @param dimm0 The SMBus address of DIMM 0 (mainboard dependent).
90 * @param dimm1 The SMBus address of DIMM 1 (mainboard dependent).
91 * @param terminated The bus is terminated. (mainboard dependent).
93 static void SetDelayControl(u8 dimm0, u8 dimm1, int terminated)
96 u8 spdbyte0, spdbyte1, dimms, i;
99 glspeed = GeodeLinkSpeed();
101 /* Fix delay controls for DM and IM arrays. */
102 for (i = 0; i < ARRAY_SIZE(delay_msr_table); i++)
103 wrmsr(delay_msr_table[i].index, delay_msr_table[i].msr);
105 msr = rdmsr(GLCP_FIFOCTL);
107 wrmsr(GLCP_FIFOCTL, msr);
109 /* Enable setting. */
112 wrmsr(CPU_BC_MSS_ARRAY_CTL_ENA, msr);
114 /* Debug Delay Control setup check.
115 * Leave it alone if it has been setup. FS2 or something is here.
117 msr = rdmsr(GLCP_DELAY_CONTROLS);
118 if (msr.lo & ~(DELAY_LOWER_STATUS_MASK))
121 /* Delay Controls based on DIMM loading. UGH!
122 * Number of devices = module width (SPD 6) / device width (SPD 13)
123 * * physical banks (SPD 5)
125 * Note: We only support a module width of 64.
128 spdbyte0 = spd_read_byte(dimm0, SPD_PRIMARY_SDRAM_WIDTH);
129 if (spdbyte0 != 0xFF) {
131 spdbyte0 = (u8)64 / spdbyte0 *
132 (u8)(spd_read_byte(dimm0, SPD_NUM_DIMM_BANKS));
137 spdbyte1 = spd_read_byte(dimm1, SPD_PRIMARY_SDRAM_WIDTH);
138 if (spdbyte1 != 0xFF) {
140 spdbyte1 = (u8)64 / spdbyte1 *
141 (u8)(spd_read_byte(dimm1, SPD_NUM_DIMM_BANKS));
146 /* Zero GLCP_DELAY_CONTROLS MSR */
149 /* Save some power, disable clock to second DIMM if it is empty. */
151 msr.hi |= DELAY_UPPER_DISABLE_CLK135;
153 spdbyte0 += spdbyte1;
155 if ((dimms == 1) && (terminated == DRAM_TERMINATED)) {
158 } else for (i = 0; i < ARRAY_SIZE(delay_control_table); i++) {
159 if ((dimms == delay_control_table[i].dimms) &&
160 (spdbyte0 <= delay_control_table[i].devices)) {
162 msr.hi |= delay_control_table[i].slow_hi;
163 msr.lo |= delay_control_table[i].slow_low;
165 msr.hi |= delay_control_table[i].fast_hi;
166 msr.lo |= delay_control_table[i].fast_low;
171 wrmsr(GLCP_DELAY_CONTROLS, msr);
174 /* ***************************************************************************/
176 /* ***************************************************************************/
177 void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated)
182 /* Castle 2.0 BTM periodic sync period. */
183 /* [40:37] 1 sync record per 256 bytes */
184 print_debug("Castle 2.0 BTM periodic sync period.\n");
185 msrnum = CPU_PF_CONF;
187 msr.hi |= (0x8 << 5);
191 * LX performance setting.
192 * Enable Quack for fewer re-RAS on the MC
194 print_debug("Enable Quack for fewer re-RAS on the MC\n");
197 msr.hi &= ~ARB_UPPER_DACK_EN_SET;
198 msr.hi |= ARB_UPPER_QUACK_EN_SET;
203 msr.hi &= ~ARB_UPPER_DACK_EN_SET;
204 msr.hi |= ARB_UPPER_QUACK_EN_SET;
207 /* GLIU port active enable, limit south pole masters
208 * (AES and PCI) to one outstanding transaction.
210 print_debug(" GLIU port active enable\n");
211 msrnum = GLIU1_PORT_ACTIVE;
216 /* Set the Delay Control in GLCP */
217 print_debug("Set the Delay Control in GLCP\n");
218 SetDelayControl(dimm0, dimm1, terminated);
221 print_debug("Enable RSDC\n");
222 msrnum = CPU_AC_SMM_CTL;
224 msr.lo |= SMM_INST_EN_SET;
227 /* FPU imprecise exceptions bit */
228 print_debug("FPU imprecise exceptions bit\n");
229 msrnum = CPU_FPU_MSR_MODE;
231 msr.lo |= FPU_IE_SET;
234 /* Power Savers (Do after BIST) */
235 /* Enable Suspend on HLT & PAUSE instructions */
236 print_debug("Enable Suspend on HLT & PAUSE instructions\n");
237 msrnum = CPU_XC_CONFIG;
239 msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE;
242 /* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */
243 print_debug("Enable SUSP and allow TSC to run in Suspend\n");
244 msrnum = CPU_BC_CONF_0;
246 msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
247 msr.lo &= 0x0F0FFFFFF;
248 msr.lo |= 0x002000000; /* PBZ213: Set PAUSEDLY = 2 */
251 /* Disable the debug clock to save power. */
252 /* NOTE: leave it enabled for fs2 debug */
253 if (debug_clock_disable && 0) {
254 msrnum = GLCP_DBGCLKCTL;
260 /* Setup throttling delays to proper mode if it is ever enabled. */
261 print_debug("Setup throttling delays to proper mode\n");
264 msr.lo = 0x00000603C;
266 print_debug("Done cpuRegInit\n");