2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
5 * Copyright (C) 2008 Carl-Daniel Hailfinger
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <device/device.h>
24 #include <device/pci.h>
25 #include <device/pci_ids.h>
26 #include <device/pci_ops.h>
29 #include <pc80/mc146818rtc.h>
31 #define SATA_MODE_IDE 1
32 #define SATA_MODE_AHCI 0
34 static int sata_drive_detect(int portnum, u16 iobar)
38 outb(0xA0 + 0x10 * (portnum % 2), iobar + 0x6);
39 while (byte = inb(iobar + 0x6), byte2 = inb(iobar + 0x7),
40 (byte != (0xA0 + 0x10 * (portnum % 2))) ||
41 ((byte2 & 0x88) != 0)) {
42 printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2);
43 if (byte != (0xA0 + 0x10 * (portnum % 2))) {
44 /* This will happen at the first iteration of this loop
45 * if the first SATA port is unpopulated and the
46 * second SATA port is populated.
48 printk(BIOS_DEBUG, "drive no longer selected after %i ms, "
49 "retrying init\n", i * 10);
52 printk(BIOS_SPEW, "drive detection not yet completed, "
57 printk(BIOS_SPEW, "drive detection done after %i ms\n", i * 10);
61 static void sata_init(struct device *dev)
67 u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
70 struct southbridge_ati_sb600_config *conf;
71 conf = dev->chip_info;
74 /* SATA SMBus Disable */
75 /* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */
76 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
77 /* Disable SATA SMBUS */
78 byte = pci_read_config8(sm_dev, 0xad);
80 /* Enable SATA and power saving */
81 byte = pci_read_config8(sm_dev, 0xad);
84 pci_write_config8(sm_dev, 0xad, byte);
85 /* Set the interrupt Mapping to INTG# */
86 byte = pci_read_config8(sm_dev, 0xaf);
88 pci_write_config8(sm_dev, 0xaf, byte);
90 /* get base address */
91 sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
92 sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
93 sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
94 sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
95 sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x3;
96 sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf;
98 printk(BIOS_SPEW, "sata_bar0=%x\n", sata_bar0); /* 3030 */
99 printk(BIOS_SPEW, "sata_bar1=%x\n", sata_bar1); /* 3070 */
100 printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2); /* 3040 */
101 printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3); /* 3080 */
102 printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */
103 printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5); /* e0309000 */
106 word = pci_read_config16(dev, 0x04);
108 pci_write_config16(dev, 0x04, word);
110 /* Dynamic power saving */
111 byte = pci_read_config8(dev, 0x40);
113 pci_write_config8(dev, 0x40, byte);
115 /* Set SATA Operation Mode */
116 byte = pci_read_config8(dev, 0x40);
119 pci_write_config8(dev, 0x40, byte);
121 // 1 means IDE, 0 means AHCI
122 if( get_option(&i, "sata_mode") < 0 ) {
124 i = CONFIG_SATA_MODE;
126 printk(BIOS_INFO, "%s: setting sata mode = %s\n", __func__, (i == SATA_MODE_IDE)?"ide":"ahci" );
128 dword = pci_read_config32(dev, 0x8);
130 if (i == SATA_MODE_IDE)
131 dword |= 0x00018f00; // IDE mode
133 dword |= 0x00060100; // AHCI mode
134 pci_write_config32(dev, 0x8, dword);
136 byte = pci_read_config8(dev, 0x40);
138 pci_write_config8(dev, 0x40, byte);
140 /* Enable the SATA watchdog counter */
141 byte = pci_read_config8(dev, 0x44);
143 pci_write_config8(dev, 0x44, byte);
145 /* Program the watchdog counter to 0x10 */
147 pci_write_config8(dev, 0x46, byte);
149 /* RPR6.5 Program the PHY Global Control to 0x2C00 for A13 */
151 pci_write_config16(dev, 0x86, word);
153 /* RPR6.5 Program the Phy Tuning4Ports */
155 pci_write_config32(dev, 0x88, dword);
156 pci_write_config32(dev, 0x8c, dword);
157 pci_write_config32(dev, 0x90, dword);
158 pci_write_config32(dev, 0x94, dword);
161 pci_write_config8(dev, 0xA5, byte);
162 pci_write_config8(dev, 0xAD, byte);
163 pci_write_config8(dev, 0xB5, byte);
164 pci_write_config8(dev, 0xBD, byte);
167 word = pci_read_config16(dev, 0x42);
169 pci_write_config16(dev, 0x42, word);
171 dword = pci_read_config32(dev, 0x40);
173 pci_write_config32(dev, 0x40, dword);
175 /* Enable the I/O, MM, BusMaster access for SATA */
176 byte = pci_read_config8(dev, 0x4);
178 pci_write_config8(dev, 0x4, byte);
180 /* RPR6.6 SATA drive detection. */
181 /* Use BAR5+0x128,BAR0 for Primary Slave */
182 /* Use BAR5+0x1A8,BAR0 for Primary Slave */
183 /* Use BAR5+0x228,BAR2 for Secondary Master */
184 /* Use BAR5+0x2A8,BAR2 for Secondary Slave */
186 for (i = 0; i < 4; i++) {
187 byte = read8(sata_bar5 + 0x128 + 0x80 * i);
188 printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
192 /* If the drive status is 0x1 then we see it but we aren't talking to it. */
193 /* Try to do something about it. */
194 printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
196 /* Read in Port-N Serial ATA Control Register */
197 byte = read8(sata_bar5 + 0x12C + 0x80 * i);
199 /* Set Reset Bit and 1.5g bit */
201 write8((sata_bar5 + 0x12C + 0x80 * i), byte);
206 /* Clear Reset Bit */
208 write8((sata_bar5 + 0x12C + 0x80 * i), byte);
214 byte = read8(sata_bar5 + 0x128 + 0x80 * i);
215 printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
220 for (j = 0; j < 10; j++) {
221 if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2))
224 printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n",
225 (i / 2) ? "Secondary" : "Primary",
226 (i % 2 ) ? "Slave" : "Master",
227 (j == 10) ? "not " : "",
228 (j == 10) ? j : j + 1);
230 printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n",
231 (i / 2) ? "Secondary" : "Primary",
232 (i % 2 ) ? "Slave" : "Master", i);
236 /* Below is CIM InitSataLateFar */
237 /* Enable interrupts from the HBA */
238 byte = read8(sata_bar5 + 0x4);
240 write8((sata_bar5 + 0x4), byte);
242 /* Clear error status */
243 write32((sata_bar5 + 0x130), 0xFFFFFFFF);
244 write32((sata_bar5 + 0x1b0), 0xFFFFFFFF);
245 write32((sata_bar5 + 0x230), 0xFFFFFFFF);
246 write32((sata_bar5 + 0x2b0), 0xFFFFFFFF);
248 /* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */
249 /* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */
252 /* word = pm_ioread(0x28); */
253 /* byte = pm_ioread(0x29); */
254 /* word |= byte<<8; */
255 /* printk(BIOS_DEBUG, "AcpiGpe0Blk addr = %x\n", word); */
256 /* write32(word, 0x80000000); */
259 static struct pci_operations lops_pci = {
260 .set_subsystem = pci_dev_set_subsystem,
263 static struct device_operations sata_ops = {
264 .read_resources = pci_dev_read_resources,
265 .set_resources = pci_dev_set_resources,
266 .enable_resources = pci_dev_enable_resources,
267 /* .enable = sb600_enable, */
270 .ops_pci = &lops_pci,
273 static const struct pci_driver sata0_driver __pci_driver = {
275 .vendor = PCI_VENDOR_ID_ATI,
276 .device = PCI_DEVICE_ID_ATI_SB600_SATA,