The base is now calculated automatically, and all mentions of that
config option were typical anyway (4GB - XIP_ROM_SIZE).
Change-Id: Icdf908dc043719f3810f7b5b85ad9938f362ea40
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/366
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
17 files changed:
-config XIP_ROM_BASE
- hex
- default 0xfff80000
-
config XIP_ROM_SIZE
hex
default 0x80000
config XIP_ROM_SIZE
hex
default 0x80000
default 0x18
depends on CPU_AMD_AGESA_FAMILY12
default 0x18
depends on CPU_AMD_AGESA_FAMILY12
-config XIP_ROM_BASE
- hex
- default 0xfff80000
- depends on CPU_AMD_AGESA_FAMILY12
-
config XIP_ROM_SIZE
hex
default 0x80000
config XIP_ROM_SIZE
hex
default 0x80000
default 0x18
depends on CPU_AMD_AGESA_FAMILY14
default 0x18
depends on CPU_AMD_AGESA_FAMILY14
-config XIP_ROM_BASE
- hex
- default 0xfff80000
- depends on CPU_AMD_AGESA_FAMILY14
-
config XIP_ROM_SIZE
hex
default 0x80000
config XIP_ROM_SIZE
hex
default 0x80000
movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
wrmsr
movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
wrmsr
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
/* Enable write base caching so we can do execute in place (XIP)
* on the flash ROM.
/* Enable write base caching so we can do execute in place (XIP)
* on the flash ROM.
wbcache_post_fam10_setup:
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
wbcache_post_fam10_setup:
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE */
/* Set the default memory type and enable fixed and variable MTRRs. */
movl $MTRRdefType_MSR, %ecx
/* Set the default memory type and enable fixed and variable MTRRs. */
movl $MTRRdefType_MSR, %ecx
default 0x18
depends on CPU_AMD_SOCKET_AM2R2
default 0x18
depends on CPU_AMD_SOCKET_AM2R2
-config XIP_ROM_BASE
- hex
- default 0xfff80000
- depends on CPU_AMD_SOCKET_AM2R2
-
config XIP_ROM_SIZE
hex
default 0x80000
config XIP_ROM_SIZE
hex
default 0x80000
default 0x18
depends on CPU_AMD_SOCKET_AM3
default 0x18
depends on CPU_AMD_SOCKET_AM3
-config XIP_ROM_BASE
- hex
- default 0xfff80000
- depends on CPU_AMD_SOCKET_AM3
-
config XIP_ROM_SIZE
hex
default 0x80000
config XIP_ROM_SIZE
hex
default 0x80000
default 0x18
depends on CPU_AMD_SOCKET_ASB2
default 0x18
depends on CPU_AMD_SOCKET_ASB2
-config XIP_ROM_BASE
- hex
- default 0xfff80000
- depends on CPU_AMD_SOCKET_ASB2
-
config XIP_ROM_SIZE
hex
default 0x80000
config XIP_ROM_SIZE
hex
default 0x80000
default 0x18
depends on CPU_AMD_SOCKET_C32
default 0x18
depends on CPU_AMD_SOCKET_C32
-config XIP_ROM_BASE
- hex
- default 0xfff80000
- depends on CPU_AMD_SOCKET_C32
-
config XIP_ROM_SIZE
hex
default 0x80000
config XIP_ROM_SIZE
hex
default 0x80000
default 0x18
depends on CPU_AMD_SOCKET_F_1207
default 0x18
depends on CPU_AMD_SOCKET_F_1207
-config XIP_ROM_BASE
- hex
- default 0xfff80000
- depends on CPU_AMD_SOCKET_F_1207
-
config XIP_ROM_SIZE
hex
default 0x80000
config XIP_ROM_SIZE
hex
default 0x80000
simplemask CacheSize, 0
wrmsr
simplemask CacheSize, 0
wrmsr
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
/*
* Enable write base caching so we can do execute in place (XIP)
/*
* Enable write base caching so we can do execute in place (XIP)
movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE */
/* Enable cache. */
movl %cr0, %eax
/* Enable cache. */
movl %cr0, %eax
orl $(1 << 30), %eax
movl %eax, %cr0
orl $(1 << 30), %eax
movl %eax, %cr0
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
xorl %edx, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr
xorl %edx, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE */
/* Enable cache. */
movl %cr0, %eax
/* Enable cache. */
movl %cr0, %eax
orl $(1 << 30), %eax
movl %eax, %cr0
orl $(1 << 30), %eax
movl %eax, %cr0
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE */
/* Enable cache. */
movl %cr0, %eax
/* Enable cache. */
movl %cr0, %eax
orl $(1 << 30), %eax
movl %eax, %cr0
orl $(1 << 30), %eax
movl %eax, %cr0
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE */
/* Enable cache. */
movl %cr0, %eax
/* Enable cache. */
movl %cr0, %eax
movl $(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRRphysMaskValid), %eax
wrmsr
movl $(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRRphysMaskValid), %eax
wrmsr
- /* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */
+ /* Cache XIP_ROM area to speedup coreboot code. */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
/*
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
/*
-config XIP_ROM_BASE
- hex
- default 0xffff0000
-
config XIP_ROM_SIZE
hex
default 0x10000
config XIP_ROM_SIZE
hex
default 0x10000
void x86_setup_fixed_mtrrs(void);
#endif
void x86_setup_fixed_mtrrs(void);
#endif
-/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */
-#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE)
-# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE"
-#endif
-#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE)
-# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE"
-#endif
#if !defined(CONFIG_RAMTOP)
# error "CONFIG_RAMTOP not defined"
#endif
#if !defined(CONFIG_RAMTOP)
# error "CONFIG_RAMTOP not defined"
#endif
-#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
+#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
#endif
# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
#endif
-#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0)
-# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"
-#endif
#if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0
# error "CONFIG_RAMTOP must be a power of 2"
#if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0
# error "CONFIG_RAMTOP must be a power of 2"
-mansoor@iwavesystems.com said, about the last issue:
-
- Try enabling CONFIG_XIP_ROM_BASE. It solved the same problem for me in my board.
-
-So, that's a todo.