src/mainboard/siemens/sitemp_g1p1/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2010 Siemens AG, Inc.
   6  * (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20  */
  21
  22 #define RC0 (6<<8)
  23 #define RC1 (7<<8)
  24
  25 #define DIMM0 0x50
  26 #define DIMM1 0x51
  27
  28 #define ICS951462_ADDRESS       0x69
  29 #define SMBUS_HUB 0x71
  30
  31 #include <stdint.h>
  32 #include <string.h>
  33 #include <device/pci_def.h>
  34 #include <arch/io.h>
  35 #include <device/pnp_def.h>
  36 #include <arch/romcc_io.h>
  37 #include <cpu/x86/lapic.h>
  38 #include <pc80/mc146818rtc.h>
  39 #include <console/console.h>
  40
  41 #include <cpu/amd/model_fxx_rev.h>
  42 #include "northbridge/amd/amdk8/raminit.h"
  43 #include "cpu/amd/model_fxx/apic_timer.c"
  44 #include "lib/delay.c"
  45
  46 #include "cpu/x86/lapic/boot_cpu.c"
  47 #include "northbridge/amd/amdk8/reset_test.c"
  48 #include "superio/ite/it8712f/early_serial.c"
  49
  50 #include "cpu/x86/mtrr/earlymtrr.c"
  51 #include "cpu/x86/bist.h"
  52
  53 #include "northbridge/amd/amdk8/setup_resource_map.c"
  54
  55 #include "southbridge/amd/rs690/early_setup.c"
  56 #include "southbridge/amd/sb600/early_setup.c"
  57 #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
  58
  59 /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
  60 static void memreset(int controllers, const struct mem_controller *ctrl)
  61 {
  62 }
  63
  64 /* called in raminit_f.c */
  65 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  66 {
  67 }
  68
  69 /*called in raminit_f.c */
  70 static inline int spd_read_byte(u32 device, u32 address)
  71 {
  72         return smbus_read_byte(device, address);
  73 }
  74
  75 #include "northbridge/amd/amdk8/amdk8.h"
  76 #include "northbridge/amd/amdk8/incoherent_ht.c"
  77 #include "northbridge/amd/amdk8/raminit_f.c"
  78 #include "northbridge/amd/amdk8/coherent_ht.c"
  79 #include "lib/generic_sdram.c"
  80 #include "resourcemap.c"
  81 #include "cpu/amd/dualcore/dualcore.c"
  82 #include "cpu/amd/car/post_cache_as_ram.c"
  83 #include "cpu/amd/model_fxx/init_cpus.c"
  84 #include "cpu/amd/model_fxx/fidvid.c"
  85 #include "northbridge/amd/amdk8/early_ht.c"
  86
  87 #define __WARNING__(fmt, arg...) do_printk(BIOS_WARNING ,fmt, ##arg)
  88 #define __DEBUG__(fmt, arg...) do_printk(BIOS_DEBUG ,fmt, ##arg)
  89 #define __INFO__(fmt, arg...) do_printk(BIOS_INFO ,fmt, ##arg)
  90
  91 #if CONFIG_USE_OPTION_TABLE
  92 #define DUMP_CMOS_RAM 0
  93 static inline int cmos_error(void) {
  94         unsigned char reg_d;
  95         /* See if the cmos error condition has been flagged */
  96         outb(0xd, 0x72);
  97         reg_d = inb(0x73);
  98 #if DUMP_CMOS_RAM
  99         __DEBUG__("RTC_VRT = %x\n", reg_d & RTC_VRT);
 100 #endif
 101         return (reg_d & RTC_VRT) == 0;
 102 }
 103
 104 static inline void set_chksum(int range_start, int range_end, int cks_loc)
 105 {
 106         int addr;
 107         unsigned sum;
 108         sum = 0;
 109         for( addr = range_start; addr <= range_end; addr++) {
 110                 outb(addr, 0x72);
 111                 sum += inb(0x73);
 112         }
 113         sum = ~(sum & 0x0ffff);
 114         outb(cks_loc, 0x72);
 115         outb(((sum >> 8) & 0x0ff),0x73);
 116         outb(cks_loc+1,0x72);
 117         outb((sum & 0x0ff),0x73);
 118 }
 119
 120 static inline int cmos_chksum_valid(void) {
 121         unsigned char addr, val;
 122         unsigned long sum, old_sum;
 123
 124 #if DUMP_CMOS_RAM
 125         u8 i;
 126         /* Compute the cmos checksum */
 127         for (addr = 14, i = 0; addr < LB_CKS_RANGE_START; addr++,i++) {
 128                 outb(addr, 0x72);
 129                 val = inb(0x73);
 130                 if( i%16 == 0 ) __DEBUG__("%02x:", addr);
 131                 __DEBUG__(" %02x",val);
 132                 if( i%16 == 15 ) __DEBUG__("\n");
 133         }
 134 #endif
 135         sum = 0;
 136         for(addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
 137                 outb(addr, 0x72);
 138                 val = inb(0x73);
 139 #if DUMP_CMOS_RAM
 140                 if( i%16 == 0 ) __DEBUG__("%02x:", addr);
 141                 __DEBUG__(" %02x",val);
 142                 if( i%16 == 15 ) __DEBUG__("\n");
 143                 i++;
 144 #endif
 145                 sum += val;
 146         }
 147 #if DUMP_CMOS_RAM
 148         __DEBUG__("\n");
 149 #endif
 150         sum = (sum & 0xffff) ^ 0xffff;
 151
 152         /* Read the stored checksum */
 153         outb(LB_CKS_LOC, 0x72);
 154         old_sum = inb(0x73) << 8;
 155         outb(LB_CKS_LOC+1, 0x72);
 156         old_sum |=  inb(0x73);
 157 #if DUMP_CMOS_RAM
 158         __DEBUG__("CMOS checksum: old = %lx, new = %lx\n", old_sum, sum);
 159 #endif
 160         return sum == old_sum;
 161 }
 162
 163 #include <cbfs.h>
 164 static inline void check_cmos( void ) {
 165
 166         char *cmos_default = NULL;
 167         int i;
 168 #if DUMP_CMOS_RAM
 169         u8 c = 0;
 170 #endif
 171         if (cmos_error() || !cmos_chksum_valid()) {
 172                 cmos_default = cbfs_find_file("cmos.default", 0xaa);
 173                 if (cmos_default) {
 174 #if DUMP_CMOS_RAM
 175                         __DEBUG__("Write cmos default ...\n");
 176 #endif
 177                         outb(0x0a,0x72);
 178                         i = inb(0x73);
 179                         i &= ~(1 << 4);
 180                         outb(i,0x73);
 181
 182                         for (i = 14; i < 128; i++) {
 183 #if DUMP_CMOS_RAM
 184                                 if( c%16 == 0 ) __DEBUG__("%02x:", i);
 185                                 __DEBUG__(" %02x", (u8)cmos_default[i]);
 186                                 if( c%16 == 15 ) __DEBUG__("\n");
 187                                 c++;
 188 #endif
 189                                 outb(i,0x72);
 190                                 outb(cmos_default[i],0x73);
 191                         }
 192
 193 #if DUMP_CMOS_RAM
 194                         __DEBUG__("\n");
 195 #endif
 196                         if( !cmos_chksum_valid() )
 197                                 __DEBUG__("CMOS CHECKSUM ERROR\n");
 198                         /* Now reboot to run with default cmos. */
 199                         outb(0x06, 0xcf9);
 200                         for (;;) asm("hlt"); /* Wait for reset! */
 201                 }
 202         }
 203
 204         // update altcentury
 205         outb(0x32, 0x72);
 206         i = inb(0x73);
 207         if ( i != 0x20 ) {
 208                 outb(0x20,0x73);
 209                 set_chksum(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC);
 210         }
 211
 212 }
 213
 214 #endif
 215
 216 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 217 {
 218         static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
 219         int needs_reset = 0;
 220         u32 bsp_apicid = 0;
 221         msr_t msr;
 222         struct cpuid_result cpuid1;
 223         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 224
 225         if (!cpu_init_detectedx && boot_cpu()) {
 226                 /* Nothing special needs to be done to find bus 0 */
 227                 /* Allow the HT devices to be found */
 228                 enumerate_ht_chain();
 229
 230                 /* sb600_lpc_port80(); */
 231                 sb600_pci_port80();
 232         }
 233
 234         if (bist == 0) {
 235                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 236         }
 237
 238         enable_rs690_dev8(); // enable CFG access to Dev8, which is the SB P2P Bridge
 239         sb600_lpc_init();
 240 #if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 0)
 241         check_cmos();  // rebooting in case of corrupted cmos !!!!!
 242 #endif
 243         /* it8712f_enable_serial does not use its 1st parameter. */
 244         it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
 245         it8712f_kill_watchdog();
 246
 247         console_init();
 248 #if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 1)
 249         check_cmos();  // rebooting in case of corrupted cmos !!!!!
 250 #endif
 251         post_code(0x03);
 252
 253         /* Halt if there was a built in self test failure */
 254         report_bist_failure(bist);
 255         __DEBUG__("bsp_apicid=0x%x\n", bsp_apicid);
 256
 257         setup_sitemp_resource_map();
 258
 259         setup_coherent_ht_domain();
 260
 261 #if CONFIG_LOGICAL_CPUS==1
 262         /* It is said that we should start core1 after all core0 launched */
 263         wait_all_core0_started();
 264         start_other_cores();
 265 #endif
 266         wait_all_aps_started(bsp_apicid);
 267
 268         ht_setup_chains_x(sysinfo);
 269
 270         /* run _early_setup before soft-reset. */
 271         rs690_early_setup();
 272         sb600_early_setup();
 273
 274         post_code(0x04);
 275
 276         /* Check to see if processor is capable of changing FIDVID  */
 277         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 278         cpuid1 = cpuid(0x80000007);
 279         if( (cpuid1.edx & 0x6) == 0x6 ) {
 280
 281                 /* Read FIDVID_STATUS */
 282                 msr=rdmsr(0xc0010042);
 283                 __DEBUG__("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 284
 285                 enable_fid_change();
 286                 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 287                 init_fidvid_bsp(bsp_apicid);
 288
 289                 /* show final fid and vid */
 290                 msr=rdmsr(0xc0010042);
 291                 __DEBUG__("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 292
 293         } else {
 294                 __DEBUG__("Changing FIDVID not supported\n");
 295         }
 296
 297         post_code(0x05);
 298
 299         needs_reset = optimize_link_coherent_ht();
 300         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 301         rs690_htinit();
 302         __DEBUG__("needs_reset=0x%x\n", needs_reset);
 303
 304         post_code(0x06);
 305
 306         if (needs_reset) {
 307                 __INFO__("ht reset -\n");
 308                 soft_reset();
 309         }
 310
 311         allow_all_aps_stop(bsp_apicid);
 312
 313         /* It's the time to set ctrl now; */
 314         __DEBUG__("sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
 315                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
 316         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 317
 318         post_code(0x07);
 319
 320         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 321
 322         post_code(0x08);
 323
 324         rs690_before_pci_init(); // does nothing
 325         sb600_before_pci_init();
 326
 327 #if CONFIG_USE_OPTION_TABLE
 328         if( read_option(cmos_defaults_loaded, 0) )
 329                 __WARNING__("WARNING: CMOS DEFAULTS LOADED. PLEASE CHECK CMOS OPTION \"cmos_default_loaded\" !\n");
 330 #endif
 331
 332         post_cache_as_ram();
 333 }
 334