2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include "CommonReturns.h"
22 #include "AdvancedApi.h"
23 #include <PlatformMemoryConfiguration.h>
25 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
27 /* AGESA will check the OEM configuration during preprocessing stage,
28 * coreboot enable -Wundef option, so we should make sure we have all contanstand defined
30 /* MEMORY_BUS_SPEED */
31 #define DDR400_FREQUENCY 200 ///< DDR 400
32 #define DDR533_FREQUENCY 266 ///< DDR 533
33 #define DDR667_FREQUENCY 333 ///< DDR 667
34 #define DDR800_FREQUENCY 400 ///< DDR 800
35 #define DDR1066_FREQUENCY 533 ///< DDR 1066
36 #define DDR1333_FREQUENCY 667 ///< DDR 1333
37 #define DDR1600_FREQUENCY 800 ///< DDR 1600
38 #define DDR1866_FREQUENCY 933 ///< DDR 1866
39 #define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
42 #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
43 #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
45 /* USER_MEMORY_TIMING_MODE */
46 #define TIMING_MODE_AUTO 0 ///< Use best rate possible
47 #define TIMING_MODE_LIMITED 1 ///< Set user top limit
48 #define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
51 #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
52 #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
54 /* User makes option selections here
55 * Comment out the items wanted to be included in the build.
56 * Uncomment those items you with to REMOVE from the build.
58 //#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
59 //#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
60 //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
61 //#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
62 //#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
63 //#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
64 //#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
65 //#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
66 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
67 //#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
68 ////#define BLDOPT_REMOVE_ACPI_PSTATES TRUE
69 ////#define BLDOPT_REMOVE_SRAT TRUE
70 ////#define BLDOPT_REMOVE_SLIT TRUE
71 //#define BLDOPT_REMOVE_WHEA TRUE
72 //#define BLDOPT_REMOVE_DMI TRUE
73 //#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
74 //#define BLDOPT_REMOVE_HT_ASSIST TRUE
75 //#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE
76 //#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
77 //#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
78 //#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
79 //#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
80 //#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
82 /* Build configuration values here.
84 #define BLDCFG_VRM_CURRENT_LIMIT 120000
85 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
86 #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0
87 #define BLDCFG_PLAT_NUM_IO_APICS 3
88 #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
89 #define BLDCFG_MEM_INIT_PSTATE 0
90 #define BLDCFG_AMD_PSTATE_CAP_VALUE 0
92 #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER
94 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY//1600
95 #define BLDCFG_MEMORY_MODE_UNGANGED TRUE
96 #define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
97 #define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
98 #define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE
99 #define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
100 #define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
101 #define BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE
102 #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE//TRUE
103 #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE//TRUE
104 #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE//TRUE
105 #define BLDCFG_MEMORY_POWER_DOWN FALSE
106 #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHANNEL
107 #define BLDCFG_ONLINE_SPARE FALSE
108 #define BLDCFG_BANK_SWIZZLE TRUE
109 #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
110 #define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
111 #define BLDCFG_DQS_TRAINING_CONTROL TRUE
112 #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
113 #define BLDCFG_USE_BURST_MODE FALSE
114 #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
115 #define BLDCFG_ENABLE_ECC_FEATURE TRUE
116 #define BLDCFG_ECC_REDIRECTION FALSE
117 #define BLDCFG_SCRUB_IC_RATE 0
118 #define BLDCFG_ECC_SYNC_FLOOD TRUE
119 #define BLDCFG_ECC_SYMBOL_SIZE 4
121 #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
122 #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
125 * Enable Message Based C1e CPU feature in multi-socket systems.
126 * BLDCFG_PLATFORM_C1E_OPDATA element be defined with a valid IO port value,
127 * else the feature cannot be enabled.
129 #define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased
130 #define BLDCFG_PLATFORM_C1E_OPDATA 0x80//TODO
131 //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0
132 //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0
134 #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
135 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
136 #define BLDCFG_1GB_ALIGN FALSE
137 //#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C'
138 //#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
141 // Select the platform control flow mode for performance tuning.
142 #define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm
145 * Enable the probe filtering performance tuning feature.
146 * The probe filter provides filtering of broadcast probes to
147 * improve link bandwidth and performance for multi- node systems.
149 * This feature may interact with other performance features.
150 * TRUE -Enable the feature (default) if supported by all processors,
151 * based on revision and presence of L3 cache.
152 * The feature is not enabled if there are no coherent HT links.
153 * FALSE -Do not enable the feature regardless of the configuration.
156 //but AGESA set PFMode = 0; //PF Disable, HW never set PFInitDone
157 //hang in F10HtAssistInit() do{...} while(PFInitDone != 1)
158 #define BLDCFG_USE_HT_ASSIST FALSE
161 * The socket and link match values are platform specific
163 CONST MANUAL_BUID_SWAP_LIST ROMDATA h8qgi_manual_swaplist[2] =
166 /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
167 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
171 /* Each Non-coherent chain may have a list of device swaps,
172 * Each item specify a device will be swap from its current id to a new one
174 /* FromID 0x00 is the chain with the southbridge */
175 /* 'Move' device zero to device zero, All others are non applicable */
176 {0x00, 0x00}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
177 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
178 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
179 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
180 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
181 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
182 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
183 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
186 { //The ordered final BUIDs
187 /* Specify the final BUID to be zero, All others are non applicable */
188 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
189 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
190 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
191 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
196 /* The 2nd element in the array merely terminates the list */
202 #if CONFIG_HT3_SUPPORT == 1
204 * The socket and link match values are platform specific
207 CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8qgi_cpu2cpu_limit_list[2] =
210 /* On the reference platform, these settings apply to all coherent links */
211 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
213 /* Set incoming and outgoing links to 16 bit widths, and 3.2GHz frequencies */
214 HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M,
217 /* The 2nd element in the array merely terminates the list */
223 CONST IO_PCB_LIMITS ROMDATA h8qgi_io_limit_list[2] =
226 /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
227 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
229 /* Set upstream and downstream links to 16 bit widths, and limit frequencies to 3.2GHz */
230 HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M, //Actually IO hub only support 2600M MAX
233 /* The 2nd element in the array merely terminates the list */
238 #else //CONFIG_HT3_SUPPORT == 0
239 CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8qgi_cpu2cpu_limit_list[2] =
242 /* On the reference platform, these settings apply to all coherent links */
243 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
245 /* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */
246 HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY,
249 /* The 2nd element in the array merely terminates the list */
255 CONST IO_PCB_LIMITS ROMDATA h8qgi_io_limit_list[2] =
258 /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
259 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
261 /* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */
262 HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY,
265 /* The 2nd element in the array merely terminates the list */
270 #endif //CONFIG_HT3_SUPPORT == 0
273 * HyperTransport links will typically require an equalization at high frequencies.
274 * This is called deemphasis.
276 * Deemphasis is specified as levels, for example, -3 db.
277 * There are two levels for each link, its receiver deemphasis level and its DCV level,
278 * which is based on the far side transmitter's deemphasis.
279 * For each link, different levels may be required at each link frequency.
281 * Coherent connections between processors should have an entry for the port on each processor.
282 * There should be one entry for the host root port of each non-coherent chain.
284 * AGESA initialization code does not set deemphasis on IO Devices.
285 * A default is provided for internal links of MCM processors, and
286 * those links will generally not need deemphasis structures.
288 CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA h8qgi_deemphasis_list[] =
290 /* Socket, Link, LowFreq, HighFreq, Receiver Deemphasis, Dcv Deemphasis */
292 /* Non-coherent link deemphasis. */
293 {0, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
294 {0, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
295 {0, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
296 {0, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
297 {0, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
298 {0, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
300 /* Coherent link deemphasis. */
301 {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
302 {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus3},
303 {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus6},
304 {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus6},
305 {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus8},
306 {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2600M, HT_FREQUENCY_MAX, DeemphasisLevelMinus11pre8, DcvLevelMinus11},
308 /* End of the list */
315 * For systems using socket infrastructure that permits strapping the SBI
316 * address for each socket, this should be used to provide a socket ID value.
317 * This is referred to as the hardware method for socket naming, and is the
318 * preferred solution.
321 * I do NOT know howto config socket id in simnow,
322 * so use this software way to make HT works in simnow,
323 * real hardware do not need this Socket Map.
325 * A physical socket map for a 4 G34 Sockets MCM processors topology,
326 * reference the mainboard schemantic in detail.
329 CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA h8qgi_socket_map[] =
337 * 0-3 are sublink 0, 4-7 are sublink 1
348 /* Source Socket, Link, Target Socket */
349 {HT_SOCKET0, HT_LINK0A, HT_SOCKET1},
350 {HT_SOCKET0, HT_LINK0B, HT_SOCKET3},
351 {HT_SOCKET0, HT_LINK1A, HT_SOCKET1},
352 {HT_SOCKET0, HT_LINK1B, HT_SOCKET3},
353 {HT_SOCKET0, HT_LINK3A, HT_SOCKET2},
354 {HT_SOCKET0, HT_LINK3B, HT_SOCKET2},
356 {HT_SOCKET1, HT_LINK0A, HT_SOCKET2},
357 {HT_SOCKET1, HT_LINK0B, HT_SOCKET3},
358 {HT_SOCKET1, HT_LINK1A, HT_SOCKET0},
359 {HT_SOCKET1, HT_LINK1B, HT_SOCKET2},
360 {HT_SOCKET1, HT_LINK3A, HT_SOCKET0},
361 {HT_SOCKET1, HT_LINK3B, HT_SOCKET3},
363 {HT_SOCKET2, HT_LINK0A, HT_SOCKET3},
364 {HT_SOCKET2, HT_LINK0B, HT_SOCKET0},
365 {HT_SOCKET2, HT_LINK1A, HT_SOCKET3},
366 {HT_SOCKET2, HT_LINK1B, HT_SOCKET1},
367 {HT_SOCKET2, HT_LINK3A, HT_SOCKET1},
368 {HT_SOCKET2, HT_LINK3B, HT_SOCKET0},
370 {HT_SOCKET3, HT_LINK0A, HT_SOCKET2},
371 {HT_SOCKET3, HT_LINK0B, HT_SOCKET1},
372 {HT_SOCKET3, HT_LINK1A, HT_SOCKET1},
373 {HT_SOCKET3, HT_LINK1B, HT_SOCKET0},
374 {HT_SOCKET3, HT_LINK3A, HT_SOCKET0},
375 {HT_SOCKET3, HT_LINK3B, HT_SOCKET2},
379 CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
381 {AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull},
382 {AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull},
383 {AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull},
384 {AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000ull},
385 {AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000ull},
386 {AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000ull},
387 {AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000ull},
388 {AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818ull},
389 {AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818ull},
390 {AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818ull},
391 {AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818ull},
395 #define BLDCFG_BUID_SWAP_LIST &h8qgi_manual_swaplist
396 #define BLDCFG_HTFABRIC_LIMITS_LIST &h8qgi_cpu2cpu_limit_list
397 #define BLDCFG_HTCHAIN_LIMITS_LIST &h8qgi_io_limit_list
398 #define BLDCFG_PLATFORM_DEEMPHASIS_LIST &h8qgi_deemphasis_list
399 #define BLDCFG_AP_MTRR_SETTINGS_LIST &h8qgi_ap_mtrr_list
400 //#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP &h8qgi_socket_map
403 /* Process the options...
404 * This file include MUST occur AFTER the user option selection settings
406 #define AGESA_ENTRY_INIT_RESET FALSE//TRUE
407 #define AGESA_ENTRY_INIT_RECOVERY FALSE
408 #define AGESA_ENTRY_INIT_EARLY TRUE
409 #define AGESA_ENTRY_INIT_POST TRUE
410 #define AGESA_ENTRY_INIT_ENV TRUE
411 #define AGESA_ENTRY_INIT_MID TRUE
412 #define AGESA_ENTRY_INIT_LATE TRUE
413 #define AGESA_ENTRY_INIT_S3SAVE TRUE
414 #define AGESA_ENTRY_INIT_RESUME TRUE
415 #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
416 #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
418 #include "GnbInterface.h" /*prototype for GnbInterfaceStub*/
419 #include "MaranelloInstall.h"
421 /*----------------------------------------------------------------------------------------
422 * CUSTOMER OVERIDES MEMORY TABLE
423 *----------------------------------------------------------------------------------------
427 * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
428 * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
429 * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
430 * use its default conservative settings.
432 CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
434 // The following macros are supported (use comma to separate macros):
436 // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
437 // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
438 // AGESA will base on this value to disable unused MemClk to save power.
440 // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
441 // Bit AM3/S1g3 pin name
442 // 0 M[B,A]_CLK_H/L[0]
443 // 1 M[B,A]_CLK_H/L[1]
444 // 2 M[B,A]_CLK_H/L[2]
445 // 3 M[B,A]_CLK_H/L[3]
446 // 4 M[B,A]_CLK_H/L[4]
447 // 5 M[B,A]_CLK_H/L[5]
448 // 6 M[B,A]_CLK_H/L[6]
449 // 7 M[B,A]_CLK_H/L[7]
450 // And platform has the following routing:
451 // CS0 M[B,A]_CLK_H/L[4]
452 // CS1 M[B,A]_CLK_H/L[2]
453 // CS2 M[B,A]_CLK_H/L[3]
454 // CS3 M[B,A]_CLK_H/L[5]
455 // Then platform can specify the following macro:
456 // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
458 // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
459 // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
460 // AGESA will base on this value to tristate unused CKE to save power.
462 // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
463 // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
464 // AGESA will base on this value to tristate unused ODT pins to save power.
466 // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
467 // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
468 // AGESA will base on this value to tristate unused Chip select to save power.
470 // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
471 // Specifies the number of DIMM slots per channel.
473 // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
474 // Specifies the number of Chip selects per channel.
476 // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
477 // Specifies the number of channels per socket.
479 // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
480 // Specifies DDR bus speed of channel ChannelID on socket SocketID.
482 // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
483 // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
485 // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
486 // Byte6Seed, Byte7Seed, ByteEccSeed)
487 // Specifies the write leveling seed for a channel of a socket.
489 NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), //max 3
494 * These tables are optional and may be used to adjust memory timing settings
498 UINT8 AGESA_MEM_TABLE_HY[][sizeof (MEM_TABLE_ALIAS)] =
500 // Hardcoded Memory Training Values
502 // The following macro should be used to override training values for your platform
504 // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
507 // The following training hardcode values are example values that were taken from a tilapia motherboard
508 // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in
509 // the table and replace the byte lane values with your own.
511 // ------------------ BYTE LANES ----------------------
512 // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC
514 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
515 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
516 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0
517 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
519 // DQS Receiver Enable
520 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
521 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
522 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0
523 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
526 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
527 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
528 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0
529 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
532 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0
533 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
534 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0
535 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
536 //--------------------------------------------------------------------------------------------------------------------------------------------------
538 NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table
540 UINT8 SizeOfTableHy = sizeof (AGESA_MEM_TABLE_HY) / sizeof (AGESA_MEM_TABLE_HY[0]);