2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <cpu/x86/msr.h>
22 #include <cpu/amd/mtrr.h>
23 #include <device/device.h>
24 #include <device/pci.h>
26 #include <cpu/x86/msr.h>
27 #include <cpu/x86/pae.h>
28 #include <pc80/mc146818rtc.h>
29 #include <cpu/x86/lapic.h>
32 #include <cpu/x86/cache.h>
33 #include <cpu/x86/mtrr.h>
34 #include "northbridge/amd/agesa/family10/amdfam10.h"
36 #define MCI_STATUS 0x401
38 static msr_t rdmsr_amd(u32 index)
43 :"=a"(result.lo), "=d"(result.hi)
44 :"c"(index), "D"(0x9c5a203a)
49 static void wrmsr_amd(u32 index, msr_t msr)
54 :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a)
58 static void model_10_init(device_t dev)
60 printk(BIOS_DEBUG, "Model 10 Init - a no-op.\n");
64 #if CONFIG_LOGICAL_CPUS == 1
68 /* Turn on caching if we haven't already */
75 /* zero the machine check error status registers */
78 for (i = 0; i < 6; i++) {
79 wrmsr(MCI_STATUS + (i * 4), msr);
84 /* Enable the local cpu apics */
87 /* Set the processor name string */
88 // init_processor_name();
91 #if CONFIG_LOGICAL_CPUS == 1
92 siblings = cpuid_ecx(0x80000008) & 0xff;
95 msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
97 wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
99 msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
100 msr.hi |= 1 << (33 - 32);
101 wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
103 printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
106 /* DisableCf8ExtCfg */
107 msr = rdmsr(NB_CFG_MSR);
108 msr.hi &= ~(1 << (46 - 32));
109 wrmsr(NB_CFG_MSR, msr);
112 /* Write protect SMM space with SMMLOCK. */
113 msr = rdmsr(HWCR_MSR);
115 wrmsr(HWCR_MSR, msr);
118 static struct device_operations cpu_dev_ops = {
119 .init = model_10_init,
122 static struct cpu_device_id cpu_table[] = {
123 { X86_VENDOR_AMD, 0x100F80}, /* HY-D0 */
124 { X86_VENDOR_AMD, 0x100F90}, /* HY-D0 */
125 { X86_VENDOR_AMD, 0x100F81}, /* HY-D1 */
126 { X86_VENDOR_AMD, 0x100F91}, /* HY-D1 */
130 static const struct cpu_driver model_10 __cpu_driver = {
132 .id_table = cpu_table,