2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 * AMD User options selection for a Sabine/Lynx platform solution system
25 * This file is placed in the user's platform directory and contains the
26 * build option selections desired for that platform.
28 * For Information about this file, see @ref platforminstall.
30 * @xrefitem bom "File Content Label" "Release Content"
32 * @e sub-project: Core
33 * @e \$Revision: 6049 $ @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $
36 #include "CommonReturns.h"
38 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
41 /* Select the cpu family. */
42 #define INSTALL_FAMILY_10_SUPPORT FALSE
43 #define INSTALL_FAMILY_12_SUPPORT TRUE
44 #define INSTALL_FAMILY_14_SUPPORT FALSE
45 #define INSTALL_FAMILY_15_SUPPORT FALSE
47 /* Select the cpu socket type. */
48 #define INSTALL_G34_SOCKET_SUPPORT FALSE
49 #define INSTALL_C32_SOCKET_SUPPORT FALSE
50 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
51 #define INSTALL_S1G4_SOCKET_SUPPORT FALSE
52 #define INSTALL_ASB2_SOCKET_SUPPORT FALSE
53 #define INSTALL_FS1_SOCKET_SUPPORT TRUE
54 #define INSTALL_FM1_SOCKET_SUPPORT FALSE
55 #define INSTALL_FP1_SOCKET_SUPPORT TRUE
56 #define INSTALL_FT1_SOCKET_SUPPORT FALSE
57 #define INSTALL_AM3_SOCKET_SUPPORT FALSE
60 * Agesa optional capabilities selection.
61 * Uncomment and mark FALSE those features you wish to include in the build.
62 * Comment out or mark TRUE those features you want to REMOVE from the build.
65 #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE
66 #define BLDOPT_REMOVE_RDIMMS_SUPPORT FALSE
67 #define BLDOPT_REMOVE_ECC_SUPPORT FALSE
68 #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE
69 #define BLDOPT_REMOVE_DCT_INTERLEAVE FALSE
70 #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
71 #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
72 #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
73 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE
74 #define BLDOPT_REMOVE_DDR2_SUPPORT TRUE
75 #define BLDOPT_REMOVE_DDR3_SUPPORT FALSE
76 #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
77 #define BLDOPT_REMOVE_ACPI_PSTATES FALSE
78 #define BLDOPT_REMOVE_SRAT TRUE
79 #define BLDOPT_REMOVE_SLIT TRUE
80 #define BLDOPT_REMOVE_WHEA TRUE
81 #define BLDOPT_REMOVE_DMI FALSE
82 #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
83 #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE
84 #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE
85 #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE
86 #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE
87 #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE
89 //For revision C single-link processors
90 #define BLDCFG_SUPPORT_ACPI_PSTATES_PSD_INDPX TRUE
93 * Agesa entry points used in this implementation.
95 #define AGESA_ENTRY_INIT_RESET TRUE
96 #define AGESA_ENTRY_INIT_RECOVERY FALSE
97 #define AGESA_ENTRY_INIT_EARLY TRUE
98 #define AGESA_ENTRY_INIT_POST TRUE
99 #define AGESA_ENTRY_INIT_ENV TRUE
100 #define AGESA_ENTRY_INIT_MID TRUE
101 #define AGESA_ENTRY_INIT_LATE TRUE
102 #define AGESA_ENTRY_INIT_S3SAVE TRUE
103 #define AGESA_ENTRY_INIT_RESUME TRUE
104 #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
105 #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
107 /*****************************************************************************
108 * Define the RELEASE VERSION string
110 * The Release Version string should identify the next planned release.
111 * When a branch is made in preparation for a release, the release manager
112 * should change/confirm that the branch version of this file contains the
113 * string matching the desired version for the release. The trunk version of
114 * the file should always contain a trailing 'X'. This will make sure that a
115 * development build from trunk will not be confused for a released version.
116 * The release manager will need to remove the trailing 'X' and update the
117 * version string as appropriate for the release. The trunk copy of this file
118 * should also be updated/incremented for the next expected version, + trailing 'X'
119 ****************************************************************************/
120 // This is the delivery package title, "LlanoPI "
121 // This string MUST be exactly 8 characters long
122 #define AGESA_PACKAGE_STRING {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '}
124 // This is the release version number of the AGESA component
125 // This string MUST be exactly 12 characters long
126 #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '}
128 // The following definitions specify the default values for various parameters in which there are
129 // no clearly defined defaults to be used in the common file. The values below are based on product
130 // and BKDG content, please consult the AGESA Memory team for consultation.
131 #define DFLT_SCRUB_DRAM_RATE (0)
132 #define DFLT_SCRUB_L2_RATE (0)
133 #define DFLT_SCRUB_L3_RATE (0)
134 #define DFLT_SCRUB_IC_RATE (0)
135 #define DFLT_SCRUB_DC_RATE (0)
136 #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
137 #define DFLT_VRM_SLEW_RATE (5000)
139 /* Build configuration values here.
141 #define BLDCFG_VRM_CURRENT_LIMIT 65000 //240000 //120000
142 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 15000 // 0
143 #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0
144 #define BLDCFG_PLAT_NUM_IO_APICS 3
145 #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
146 #define BLDCFG_MEM_INIT_PSTATE 0
148 #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
150 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY //DDR1066_FREQUENCY
151 #define BLDCFG_MEMORY_MODE_UNGANGED TRUE
152 #define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
153 #define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
154 #define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE
155 #define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
156 #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
157 #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
158 #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
159 #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
160 #define BLDCFG_MEMORY_POWER_DOWN TRUE
161 #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
162 #define BLDCFG_ONLINE_SPARE FALSE
163 #define BLDCFG_MEMORY_PARITY_ENABLE FALSE
164 #define BLDCFG_BANK_SWIZZLE TRUE
165 #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
166 #define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
167 #define BLDCFG_DQS_TRAINING_CONTROL TRUE
168 #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
169 #define BLDCFG_USE_BURST_MODE FALSE
170 #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
171 #define BLDCFG_ENABLE_ECC_FEATURE TRUE
172 #define BLDCFG_ECC_REDIRECTION FALSE
173 #define BLDCFG_SCRUB_DRAM_RATE 0
174 #define BLDCFG_SCRUB_L2_RATE 0
175 #define BLDCFG_SCRUB_L3_RATE 0
176 #define BLDCFG_SCRUB_IC_RATE 0
177 #define BLDCFG_SCRUB_DC_RATE 0
178 #define BLDCFG_ECC_SYNC_FLOOD FALSE
179 #define BLDCFG_ECC_SYMBOL_SIZE 4
180 #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
181 #define BLDCFG_1GB_ALIGN FALSE
182 #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
183 //#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C'
184 //#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
187 #define BLDCFG_PLATFORM_C1E_MODE 0 //C1eModeHardware
188 //#define BLDCFG_PLATFORM_C1E_OPDATA 0x415
189 #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 //0 //CStateModeC6
190 //#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6
191 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6
194 //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario
195 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L. Default is Zero.
196 //#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime per BKDG. Defaults to 5000, same as core VRM. Cannot be zero.
197 //#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Llano/Ontario
198 //#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Llano/Ontario
199 //#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario
201 #define BLDCFG_UMA_ABOVE4G_SUPPORT TRUE
202 #define BLDCFG_STEREO_3D_PINOUT TRUE
204 /* Process the options...
205 * This file include MUST occur AFTER the user option selection settings
207 CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] =
209 { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
210 { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
211 { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
212 { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000ull },
213 { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000ull },
214 { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000ull },
215 { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000ull },
216 { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818ull },
217 { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818ull },
218 { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818ull },
219 { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818ull },
220 { CPU_LIST_TERMINAL }
223 #define BLDCFG_AP_MTRR_SETTINGS_LIST &LlanoApMtrrSettingsList
224 //#define OPTION_NB_LCLK_DPM_INIT FALSE
225 //#define OPTION_POWER_GATE FALSE
226 //#define OPTION_PCIE_POWER_GATE FALSE
227 //#define OPTION_ALIB FALSE
228 //#define OPTION_PCIe_MID_INIT FALSE
229 //#define OPTION_NB_MID_INIT FALSE
231 #include "cpuRegisters.h"
232 #include "cpuFamRegisters.h"
233 #include "cpuFamilyTranslation.h"
234 #include "AdvancedApi.h"
235 #include "heapManager.h"
236 #include "CreateStruct.h"
237 #include "cpuFeatures.h"
239 #include "CommonReturns.h"
240 #include "cpuEarlyInit.h"
241 #include "cpuLateInit.h"
242 #include "GnbInterface.h"
243 #include "PlatformInstall.h"
245 /*----------------------------------------------------------------------------------------
246 * CUSTOMER OVERIDES MEMORY TABLE
247 *----------------------------------------------------------------------------------------
251 * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
252 * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
253 * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
254 * use its default conservative settings.
256 CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
258 // The following macros are supported (use comma to separate macros):
260 // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
261 // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
262 // AGESA will base on this value to disable unused MemClk to save power.
264 // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
265 // Bit AM3/S1g3 pin name
266 // 0 M[B,A]_CLK_H/L[0]
267 // 1 M[B,A]_CLK_H/L[1]
268 // 2 M[B,A]_CLK_H/L[2]
269 // 3 M[B,A]_CLK_H/L[3]
270 // 4 M[B,A]_CLK_H/L[4]
271 // 5 M[B,A]_CLK_H/L[5]
272 // 6 M[B,A]_CLK_H/L[6]
273 // 7 M[B,A]_CLK_H/L[7]
274 // And platform has the following routing:
275 // CS0 M[B,A]_CLK_H/L[4]
276 // CS1 M[B,A]_CLK_H/L[2]
277 // CS2 M[B,A]_CLK_H/L[3]
278 // CS3 M[B,A]_CLK_H/L[5]
279 // Then platform can specify the following macro:
280 // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
282 // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
283 // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
284 // AGESA will base on this value to tristate unused CKE to save power.
286 // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
287 // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
288 // AGESA will base on this value to tristate unused ODT pins to save power.
290 // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
291 // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
292 // AGESA will base on this value to tristate unused Chip select to save power.
294 // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
295 // Specifies the number of DIMM slots per channel.
297 // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
298 // Specifies the number of Chip selects per channel.
300 // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
301 // Specifies the number of channels per socket.
303 // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
304 // Specifies DDR bus speed of channel ChannelID on socket SocketID.
306 // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
307 // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
309 // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
310 // Byte6Seed, Byte7Seed, ByteEccSeed)
311 // Specifies the write leveling seed for a channel of a socket.
313 NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
314 NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
319 * These tables are optional and may be used to adjust memory timing settings
325 UINT8 AGESA_MEM_TABLE_LN[][sizeof (MEM_TABLE_ALIAS)] =
327 // Hardcoded Memory Training Values
329 // The following macro should be used to override training values for your platform
331 // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
334 // The following training hardcode values are example values that were taken from a tilapia motherboard
335 // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in
336 // the table and replace the byte lane values with your own.
338 // ------------------ BYTE LANES ----------------------
339 // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC
341 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x15, 0x14, 0x21, 0x11, 0x40, 0x2A, 0x34, 0x2D, 0x15),// DCT0, DIMM0
342 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
343 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x17, 0x16, 0x21, 0x11, 0x3F, 0x2A, 0x35, 0x2E, 0x17),// DCT1, DIMM0
344 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
346 // DQS Receiver Enable
347 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x77, 0x70, 0x77, 0x60, 0x95, 0x83, 0x8F, 0x90, 0x77),// DCT0, DIMM0
348 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
349 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x7D, 0x75, 0x7F, 0x6C, 0x9A, 0x8D, 0x94, 0x98, 0x7D),// DCT1, DIMM0
350 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
353 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x03, 0x04, 0x0F, 0x00, 0x2D, 0x1B, 0x23, 0x1C, 0x00),// DCT0, DIMM0
354 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
355 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x05, 0x05, 0x0F, 0x00, 0x2E, 0x19, 0x24, 0x1C, 0x00),// DCT1, DIMM0
356 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
359 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x0C, 0x0A, 0x0A, 0x0E, 0x0A, 0x0C, 0x0C, 0x0A, 0x0C),// DCT0, DIMM0
360 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
361 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x0A, 0x0C, 0x0E, 0x0A, 0x0C, 0x0A, 0x0C, 0x0E, 0x0A),// DCT1, DIMM0
362 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
363 // --------------------------------------------------------------------------------------------------------------------------------------------------
366 // NBACCESS (MTAfterMaxRdLatTrn, MTNode0, MTDct0, BFMaxLatency, MTOverride, 0x0C),
367 // NBACCESS (MTAfterMaxRdLatTrn, MTNode0, MTDct1, BFMaxLatency, MTOverride, 0x0C),
369 NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table
371 UINT8 SizeOfTableLN = sizeof (AGESA_MEM_TABLE_LN) / sizeof (AGESA_MEM_TABLE_LN[0]);
373 /* ***************************************************************************
374 * Optional User code to be included into the AGESA build
375 * These may be 32-bit call-out routines...
380 // IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
383 // /* platform code to read an SPD... */