2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <arch/romcc_io.h>
26 #include <console/console.h>
27 #include <arch/stages.h>
28 #include "cpu/x86/bist.h"
29 #include "cpu/x86/lapic/boot_cpu.c"
30 #include "agesawrapper.h"
31 #include "northbridge/amd/agesa/family10/reset_test.h"
32 #include "southbridge/amd/sr5650/sr5650.h"
33 #include "southbridge/amd/sb700/sb700.h"
34 #include "superio/nuvoton/wpcm450/wpcm450.h"
36 extern void disable_cache_as_ram(void); /* cache_as_ram.inc */
38 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
42 agesawrapper_amdinitmmio();
43 if (!cpu_init_detectedx && boot_cpu()) {
45 /* SR56x0 pcie bridges block pci_locate_device() before pcie training.
46 * disable all pcie bridges on SR56x0 to work around it
48 sr5650_disable_pcie_bridge();
50 sb7xx_51xx_lpc_port80();
54 /* Halt if there was a built in self test failure */
56 report_bist_failure(bist);
59 sb7xx_51xx_lpc_init();
60 sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */
61 wpcm450_enable_dev(WPCM450_SP1, CONFIG_SIO_PORT, CONFIG_TTYS0_BASE);
62 sb7xx_51xx_disable_wideio(0);
70 printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
71 printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
74 val = agesawrapper_amdinitreset();
76 printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
78 printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n");
82 val = agesawrapper_amdinitearly();
84 printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
86 printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n");
92 sb7xx_51xx_early_setup();
94 /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
95 if (!warm_reset_detect(0)) {
96 print_info("...WARM RESET...\n\n\n");
97 distinguish_cpu_resets(0);
99 die("After soft_reset_x - shouldn't see this message!!!\n");
103 val = agesawrapper_amdinitpost();
105 printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
107 printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n");
110 val = agesawrapper_amdinitenv();
112 printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
114 printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n");
117 sr5650_before_pci_init();
118 sb7xx_51xx_before_pci_init();
121 print_debug("Disabling cache as ram ");
122 disable_cache_as_ram();
123 print_debug("done\n");
128 /* We will not return, Should never see this message and post code. */
129 print_debug("should not be here -\n");